Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 2 | # |
| 3 | # For a description of the syntax of this configuration file, |
Paul Bolle | 395cf96 | 2011-08-15 02:02:26 +0200 | [diff] [blame] | 4 | # see Documentation/kbuild/kconfig-language.txt. |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 5 | # |
| 6 | |
| 7 | config OPENRISC |
| 8 | def_bool y |
Christoph Hellwig | 5600779 | 2018-07-19 06:02:32 -0700 | [diff] [blame] | 9 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 10 | select OF |
| 11 | select OF_EARLY_FLATTREE |
Jonas Bonn | b4c4c6e | 2012-04-06 12:52:54 +0200 | [diff] [blame] | 12 | select IRQ_DOMAIN |
Marc Zyngier | d1f6f28 | 2014-08-26 11:03:19 +0100 | [diff] [blame] | 13 | select HANDLE_DOMAIN_IRQ |
Linus Walleij | 8636f34 | 2016-04-19 13:15:43 +0200 | [diff] [blame] | 14 | select GPIOLIB |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 15 | select HAVE_ARCH_TRACEHOOK |
Jonas Bonn | c0fcaf5 | 2012-05-09 23:19:44 +0200 | [diff] [blame] | 16 | select SPARSE_IRQ |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 17 | select GENERIC_IRQ_CHIP |
| 18 | select GENERIC_IRQ_PROBE |
| 19 | select GENERIC_IRQ_SHOW |
| 20 | select GENERIC_IOMAP |
Ben Hutchings | 9f13a1f | 2012-01-10 03:04:32 +0000 | [diff] [blame] | 21 | select GENERIC_CPU_DEVICES |
Andrew Morton | 04ea1e9 | 2015-07-17 16:23:28 -0700 | [diff] [blame] | 22 | select HAVE_UID16 |
Richard Weinberger | 0662d33 | 2012-03-02 01:55:11 +0100 | [diff] [blame] | 23 | select GENERIC_ATOMIC64 |
Anna-Maria Gleixner | 5bf8f6b | 2012-05-18 16:45:51 +0000 | [diff] [blame] | 24 | select GENERIC_CLOCKEVENTS |
Stefan Kristiansson | 8e6d08e | 2014-05-11 21:49:34 +0300 | [diff] [blame] | 25 | select GENERIC_CLOCKEVENTS_BROADCAST |
Jonas Bonn | 603d6637 | 2012-05-25 08:24:49 +0200 | [diff] [blame] | 26 | select GENERIC_STRNCPY_FROM_USER |
Jonas Bonn | b48b2c3 | 2012-05-27 10:25:47 +0200 | [diff] [blame] | 27 | select GENERIC_STRNLEN_USER |
Stefan Kristiansson | 8e6d08e | 2014-05-11 21:49:34 +0300 | [diff] [blame] | 28 | select GENERIC_SMP_IDLE_THREAD |
David Howells | 786d35d | 2012-09-28 14:31:03 +0930 | [diff] [blame] | 29 | select MODULES_USE_ELF_RELA |
Dave Hansen | d1a1dc0 | 2013-07-01 13:04:42 -0700 | [diff] [blame] | 30 | select HAVE_DEBUG_STACKOVERFLOW |
Stefan Kristiansson | 4db8e6d | 2014-05-26 23:31:42 +0300 | [diff] [blame] | 31 | select OR1K_PIC |
Zhaoxiu Zeng | fff7fb0 | 2016-05-20 17:03:57 -0700 | [diff] [blame] | 32 | select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 |
Stafford Horne | b5f8217 | 2017-03-24 07:13:03 +0900 | [diff] [blame] | 33 | select ARCH_USE_QUEUED_SPINLOCKS |
| 34 | select ARCH_USE_QUEUED_RWLOCKS |
Stafford Horne | 9b54470 | 2017-10-30 21:38:35 +0900 | [diff] [blame] | 35 | select OMPIC if SMP |
Stafford Horne | eecac38 | 2017-07-24 21:44:35 +0900 | [diff] [blame] | 36 | select ARCH_WANT_FRAME_POINTERS |
Palmer Dabbelt | c5ca456 | 2018-06-22 10:01:25 -0700 | [diff] [blame] | 37 | select GENERIC_IRQ_MULTI_HANDLER |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 38 | |
Babu Moger | 4c97a0c | 2017-09-08 16:14:22 -0700 | [diff] [blame] | 39 | config CPU_BIG_ENDIAN |
| 40 | def_bool y |
| 41 | |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 42 | config MMU |
| 43 | def_bool y |
| 44 | |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 45 | config RWSEM_GENERIC_SPINLOCK |
| 46 | def_bool y |
| 47 | |
| 48 | config RWSEM_XCHGADD_ALGORITHM |
| 49 | def_bool n |
| 50 | |
| 51 | config GENERIC_HWEIGHT |
| 52 | def_bool y |
| 53 | |
Uwe Kleine-König | ce816fa | 2014-04-07 15:39:19 -0700 | [diff] [blame] | 54 | config NO_IOPORT_MAP |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 55 | def_bool y |
| 56 | |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 57 | config TRACE_IRQFLAGS_SUPPORT |
| 58 | def_bool y |
| 59 | |
| 60 | # For now, use generic checksum functions |
| 61 | #These can be reimplemented in assembly later if so inclined |
| 62 | config GENERIC_CSUM |
| 63 | def_bool y |
| 64 | |
Stafford Horne | eecac38 | 2017-07-24 21:44:35 +0900 | [diff] [blame] | 65 | config STACKTRACE_SUPPORT |
| 66 | def_bool y |
| 67 | |
Stafford Horne | 78cdfb5 | 2017-07-24 21:55:16 +0900 | [diff] [blame] | 68 | config LOCKDEP_SUPPORT |
| 69 | def_bool y |
| 70 | |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 71 | menu "Processor type and features" |
| 72 | |
| 73 | choice |
| 74 | prompt "Subarchitecture" |
| 75 | default OR1K_1200 |
| 76 | |
| 77 | config OR1K_1200 |
| 78 | bool "OR1200" |
| 79 | help |
| 80 | Generic OpenRISC 1200 architecture |
| 81 | |
| 82 | endchoice |
| 83 | |
Jan Henrik Weinstock | 4ee93d8 | 2015-11-04 17:26:10 +0100 | [diff] [blame] | 84 | config DCACHE_WRITETHROUGH |
| 85 | bool "Have write through data caches" |
| 86 | default n |
| 87 | help |
| 88 | Select this if your implementation features write through data caches. |
| 89 | Selecting 'N' here will allow the kernel to force flushing of data |
| 90 | caches at relevant times. Most OpenRISC implementations support write- |
| 91 | through data caches. |
| 92 | |
| 93 | If unsure say N here |
| 94 | |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 95 | config OPENRISC_BUILTIN_DTB |
| 96 | string "Builtin DTB" |
| 97 | default "" |
| 98 | |
| 99 | menu "Class II Instructions" |
| 100 | |
| 101 | config OPENRISC_HAVE_INST_FF1 |
| 102 | bool "Have instruction l.ff1" |
| 103 | default y |
| 104 | help |
| 105 | Select this if your implementation has the Class II instruction l.ff1 |
| 106 | |
| 107 | config OPENRISC_HAVE_INST_FL1 |
| 108 | bool "Have instruction l.fl1" |
| 109 | default y |
| 110 | help |
| 111 | Select this if your implementation has the Class II instruction l.fl1 |
| 112 | |
| 113 | config OPENRISC_HAVE_INST_MUL |
| 114 | bool "Have instruction l.mul for hardware multiply" |
| 115 | default y |
| 116 | help |
| 117 | Select this if your implementation has a hardware multiply instruction |
| 118 | |
| 119 | config OPENRISC_HAVE_INST_DIV |
| 120 | bool "Have instruction l.div for hardware divide" |
| 121 | default y |
| 122 | help |
| 123 | Select this if your implementation has a hardware divide instruction |
| 124 | endmenu |
| 125 | |
Stafford Horne | 34bbdcd | 2016-09-24 22:20:42 +0900 | [diff] [blame] | 126 | config NR_CPUS |
Stefan Kristiansson | 8e6d08e | 2014-05-11 21:49:34 +0300 | [diff] [blame] | 127 | int "Maximum number of CPUs (2-32)" |
| 128 | range 2 32 |
| 129 | depends on SMP |
| 130 | default "2" |
| 131 | |
| 132 | config SMP |
| 133 | bool "Symmetric Multi-Processing support" |
| 134 | help |
| 135 | This enables support for systems with more than one CPU. If you have |
| 136 | a system with only one CPU, say N. If you have a system with more |
| 137 | than one CPU, say Y. |
| 138 | |
| 139 | If you don't know what to do here, say N. |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 140 | |
Masahiro Yamada | 8636a1f | 2018-12-11 20:01:04 +0900 | [diff] [blame] | 141 | source "kernel/Kconfig.hz" |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 142 | |
| 143 | config OPENRISC_NO_SPR_SR_DSX |
| 144 | bool "use SPR_SR_DSX software emulation" if OR1K_1200 |
| 145 | default y |
| 146 | help |
| 147 | SPR_SR_DSX bit is status register bit indicating whether |
| 148 | the last exception has happened in delay slot. |
| 149 | |
| 150 | OpenRISC architecture makes it optional to have it implemented |
| 151 | in hardware and the OR1200 does not have it. |
| 152 | |
| 153 | Say N here if you know that your OpenRISC processor has |
| 154 | SPR_SR_DSX bit implemented. Say Y if you are unsure. |
| 155 | |
Stefan Kristiansson | 91993c8 | 2014-05-11 12:08:37 +0300 | [diff] [blame] | 156 | config OPENRISC_HAVE_SHADOW_GPRS |
| 157 | bool "Support for shadow gpr files" if !SMP |
| 158 | default y if SMP |
| 159 | help |
| 160 | Say Y here if your OpenRISC processor features shadowed |
| 161 | register files. They will in such case be used as a |
| 162 | scratch reg storage on exception entry. |
| 163 | |
| 164 | On SMP systems, this feature is mandatory. |
| 165 | On a unicore system it's safe to say N here if you are unsure. |
| 166 | |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 167 | config CMDLINE |
| 168 | string "Default kernel command string" |
| 169 | default "" |
| 170 | help |
| 171 | On some architectures there is currently no way for the boot loader |
| 172 | to pass arguments to the kernel. For these architectures, you should |
| 173 | supply some command-line options at build time by entering them |
| 174 | here. |
| 175 | |
| 176 | menu "Debugging options" |
| 177 | |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 178 | config JUMP_UPON_UNHANDLED_EXCEPTION |
| 179 | bool "Try to die gracefully" |
| 180 | default y |
| 181 | help |
| 182 | Now this puts kernel into infinite loop after first oops. Till |
| 183 | your kernel crashes this doesn't have any influence. |
| 184 | |
| 185 | Say Y if you are unsure. |
| 186 | |
Jonas Bonn | f8c4a27 | 2011-06-04 21:52:05 +0300 | [diff] [blame] | 187 | config OPENRISC_ESR_EXCEPTION_BUG_CHECK |
| 188 | bool "Check for possible ESR exception bug" |
| 189 | default n |
| 190 | help |
| 191 | This option enables some checks that might expose some problems |
| 192 | in kernel. |
| 193 | |
| 194 | Say N if you are unsure. |
| 195 | |
| 196 | endmenu |
| 197 | |
| 198 | endmenu |