blob: 09ab59e942ae2366f726fa3dee8b7309a7c5a970 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001# SPDX-License-Identifier: GPL-2.0
Jonas Bonnf8c4a272011-06-04 21:52:05 +03002#
3# For a description of the syntax of this configuration file,
Paul Bolle395cf962011-08-15 02:02:26 +02004# see Documentation/kbuild/kconfig-language.txt.
Jonas Bonnf8c4a272011-06-04 21:52:05 +03005#
6
7config OPENRISC
8 def_bool y
Christoph Hellwig56007792018-07-19 06:02:32 -07009 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
Jonas Bonnf8c4a272011-06-04 21:52:05 +030010 select OF
11 select OF_EARLY_FLATTREE
Jonas Bonnb4c4c6e2012-04-06 12:52:54 +020012 select IRQ_DOMAIN
Marc Zyngierd1f6f282014-08-26 11:03:19 +010013 select HANDLE_DOMAIN_IRQ
Linus Walleij8636f342016-04-19 13:15:43 +020014 select GPIOLIB
Jonas Bonnf8c4a272011-06-04 21:52:05 +030015 select HAVE_ARCH_TRACEHOOK
Jonas Bonnc0fcaf52012-05-09 23:19:44 +020016 select SPARSE_IRQ
Jonas Bonnf8c4a272011-06-04 21:52:05 +030017 select GENERIC_IRQ_CHIP
18 select GENERIC_IRQ_PROBE
19 select GENERIC_IRQ_SHOW
20 select GENERIC_IOMAP
Ben Hutchings9f13a1f2012-01-10 03:04:32 +000021 select GENERIC_CPU_DEVICES
Andrew Morton04ea1e92015-07-17 16:23:28 -070022 select HAVE_UID16
Richard Weinberger0662d332012-03-02 01:55:11 +010023 select GENERIC_ATOMIC64
Anna-Maria Gleixner5bf8f6b2012-05-18 16:45:51 +000024 select GENERIC_CLOCKEVENTS
Stefan Kristiansson8e6d08e2014-05-11 21:49:34 +030025 select GENERIC_CLOCKEVENTS_BROADCAST
Jonas Bonn603d66372012-05-25 08:24:49 +020026 select GENERIC_STRNCPY_FROM_USER
Jonas Bonnb48b2c32012-05-27 10:25:47 +020027 select GENERIC_STRNLEN_USER
Stefan Kristiansson8e6d08e2014-05-11 21:49:34 +030028 select GENERIC_SMP_IDLE_THREAD
David Howells786d35d2012-09-28 14:31:03 +093029 select MODULES_USE_ELF_RELA
Dave Hansend1a1dc02013-07-01 13:04:42 -070030 select HAVE_DEBUG_STACKOVERFLOW
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +030031 select OR1K_PIC
Zhaoxiu Zengfff7fb02016-05-20 17:03:57 -070032 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
Stafford Horneb5f82172017-03-24 07:13:03 +090033 select ARCH_USE_QUEUED_SPINLOCKS
34 select ARCH_USE_QUEUED_RWLOCKS
Stafford Horne9b544702017-10-30 21:38:35 +090035 select OMPIC if SMP
Stafford Horneeecac382017-07-24 21:44:35 +090036 select ARCH_WANT_FRAME_POINTERS
Palmer Dabbeltc5ca4562018-06-22 10:01:25 -070037 select GENERIC_IRQ_MULTI_HANDLER
Jonas Bonnf8c4a272011-06-04 21:52:05 +030038
Babu Moger4c97a0c2017-09-08 16:14:22 -070039config CPU_BIG_ENDIAN
40 def_bool y
41
Jonas Bonnf8c4a272011-06-04 21:52:05 +030042config MMU
43 def_bool y
44
Jonas Bonnf8c4a272011-06-04 21:52:05 +030045config RWSEM_GENERIC_SPINLOCK
46 def_bool y
47
48config RWSEM_XCHGADD_ALGORITHM
49 def_bool n
50
51config GENERIC_HWEIGHT
52 def_bool y
53
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -070054config NO_IOPORT_MAP
Jonas Bonnf8c4a272011-06-04 21:52:05 +030055 def_bool y
56
Jonas Bonnf8c4a272011-06-04 21:52:05 +030057config TRACE_IRQFLAGS_SUPPORT
58 def_bool y
59
60# For now, use generic checksum functions
61#These can be reimplemented in assembly later if so inclined
62config GENERIC_CSUM
63 def_bool y
64
Stafford Horneeecac382017-07-24 21:44:35 +090065config STACKTRACE_SUPPORT
66 def_bool y
67
Stafford Horne78cdfb52017-07-24 21:55:16 +090068config LOCKDEP_SUPPORT
69 def_bool y
70
Jonas Bonnf8c4a272011-06-04 21:52:05 +030071menu "Processor type and features"
72
73choice
74 prompt "Subarchitecture"
75 default OR1K_1200
76
77config OR1K_1200
78 bool "OR1200"
79 help
80 Generic OpenRISC 1200 architecture
81
82endchoice
83
Jan Henrik Weinstock4ee93d82015-11-04 17:26:10 +010084config DCACHE_WRITETHROUGH
85 bool "Have write through data caches"
86 default n
87 help
88 Select this if your implementation features write through data caches.
89 Selecting 'N' here will allow the kernel to force flushing of data
90 caches at relevant times. Most OpenRISC implementations support write-
91 through data caches.
92
93 If unsure say N here
94
Jonas Bonnf8c4a272011-06-04 21:52:05 +030095config OPENRISC_BUILTIN_DTB
96 string "Builtin DTB"
97 default ""
98
99menu "Class II Instructions"
100
101config OPENRISC_HAVE_INST_FF1
102 bool "Have instruction l.ff1"
103 default y
104 help
105 Select this if your implementation has the Class II instruction l.ff1
106
107config OPENRISC_HAVE_INST_FL1
108 bool "Have instruction l.fl1"
109 default y
110 help
111 Select this if your implementation has the Class II instruction l.fl1
112
113config OPENRISC_HAVE_INST_MUL
114 bool "Have instruction l.mul for hardware multiply"
115 default y
116 help
117 Select this if your implementation has a hardware multiply instruction
118
119config OPENRISC_HAVE_INST_DIV
120 bool "Have instruction l.div for hardware divide"
121 default y
122 help
123 Select this if your implementation has a hardware divide instruction
124endmenu
125
Stafford Horne34bbdcd2016-09-24 22:20:42 +0900126config NR_CPUS
Stefan Kristiansson8e6d08e2014-05-11 21:49:34 +0300127 int "Maximum number of CPUs (2-32)"
128 range 2 32
129 depends on SMP
130 default "2"
131
132config SMP
133 bool "Symmetric Multi-Processing support"
134 help
135 This enables support for systems with more than one CPU. If you have
136 a system with only one CPU, say N. If you have a system with more
137 than one CPU, say Y.
138
139 If you don't know what to do here, say N.
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300140
Masahiro Yamada8636a1f2018-12-11 20:01:04 +0900141source "kernel/Kconfig.hz"
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300142
143config OPENRISC_NO_SPR_SR_DSX
144 bool "use SPR_SR_DSX software emulation" if OR1K_1200
145 default y
146 help
147 SPR_SR_DSX bit is status register bit indicating whether
148 the last exception has happened in delay slot.
149
150 OpenRISC architecture makes it optional to have it implemented
151 in hardware and the OR1200 does not have it.
152
153 Say N here if you know that your OpenRISC processor has
154 SPR_SR_DSX bit implemented. Say Y if you are unsure.
155
Stefan Kristiansson91993c82014-05-11 12:08:37 +0300156config OPENRISC_HAVE_SHADOW_GPRS
157 bool "Support for shadow gpr files" if !SMP
158 default y if SMP
159 help
160 Say Y here if your OpenRISC processor features shadowed
161 register files. They will in such case be used as a
162 scratch reg storage on exception entry.
163
164 On SMP systems, this feature is mandatory.
165 On a unicore system it's safe to say N here if you are unsure.
166
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300167config CMDLINE
168 string "Default kernel command string"
169 default ""
170 help
171 On some architectures there is currently no way for the boot loader
172 to pass arguments to the kernel. For these architectures, you should
173 supply some command-line options at build time by entering them
174 here.
175
176menu "Debugging options"
177
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300178config JUMP_UPON_UNHANDLED_EXCEPTION
179 bool "Try to die gracefully"
180 default y
181 help
182 Now this puts kernel into infinite loop after first oops. Till
183 your kernel crashes this doesn't have any influence.
184
185 Say Y if you are unsure.
186
Jonas Bonnf8c4a272011-06-04 21:52:05 +0300187config OPENRISC_ESR_EXCEPTION_BUG_CHECK
188 bool "Check for possible ESR exception bug"
189 default n
190 help
191 This option enables some checks that might expose some problems
192 in kernel.
193
194 Say N if you are unsure.
195
196endmenu
197
198endmenu