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Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +01001/* SPDX-License-Identifier: GPL-2.0 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
3 * include/asm-parisc/cache.h
4 */
5
6#ifndef __ARCH_PARISC_CACHE_H
7#define __ARCH_PARISC_CACHE_H
8
Helge Deller3847dab2018-10-16 22:38:22 +02009#include <asm/alternative.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070010
11/*
John David Anglina01fece2015-10-14 20:32:11 -040012 * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
13 * have 32-byte cachelines. The L1 length appears to be 16 bytes but this
14 * is not clearly documented.
Linus Torvalds1da177e2005-04-16 15:20:36 -070015 */
John David Anglina01fece2015-10-14 20:32:11 -040016#define L1_CACHE_BYTES 16
17#define L1_CACHE_SHIFT 4
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
19#ifndef __ASSEMBLY__
20
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#define SMP_CACHE_BYTES L1_CACHE_BYTES
Linus Torvalds1da177e2005-04-16 15:20:36 -070022
FUJITA Tomonori7896bfa2010-08-10 18:03:23 -070023#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
24
Joe Perches33def842020-10-21 19:36:07 -070025#define __read_mostly __section(".data..read_mostly")
Kyle McMartin804f1592006-03-23 03:00:16 -080026
Randolph Chungd6ce8622006-12-12 05:51:54 -080027void parisc_cache_init(void); /* initializes cache-flushing */
28void disable_sr_hashing_asm(int); /* low level support for above */
29void disable_sr_hashing(void); /* turns off space register hashing */
30void free_sid(unsigned long);
Linus Torvalds1da177e2005-04-16 15:20:36 -070031unsigned long alloc_sid(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070032
33struct seq_file;
34extern void show_cache_info(struct seq_file *m);
35
36extern int split_tlb;
37extern int dcache_stride;
38extern int icache_stride;
39extern struct pdc_cache_info cache_info;
Randolph Chungd6ce8622006-12-12 05:51:54 -080040void parisc_setup_cache_timing(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070041
Helge Deller3847dab2018-10-16 22:38:22 +020042#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" \
43 ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
John David Anglin44224bd2019-04-21 19:47:17 -040044 : : "r" (addr) : "memory")
Helge Deller3847dab2018-10-16 22:38:22 +020045#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" \
46 ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
47 ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
John David Anglin44224bd2019-04-21 19:47:17 -040048 : : "r" (addr) : "memory")
Helge Deller3847dab2018-10-16 22:38:22 +020049#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" \
50 ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
John David Anglin44224bd2019-04-21 19:47:17 -040051 : : "r" (addr) : "memory")
Helge Deller3847dab2018-10-16 22:38:22 +020052
53#define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
54 ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
55 ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
Helge Deller2d94a832019-04-27 23:57:49 +020056 : : "r" (addr) : "memory")
Helge Deller3847dab2018-10-16 22:38:22 +020057#define asm_io_sync() asm volatile("sync" \
58 ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
Helge Deller2d94a832019-04-27 23:57:49 +020059 ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
Linus Torvalds1da177e2005-04-16 15:20:36 -070060
61#endif /* ! __ASSEMBLY__ */
62
63/* Classes of processor wrt: disabling space register hashing */
64
65#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
66#define SRHASH_PCXL 1 /* pcxl */
67#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
68
69#endif