Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | /* |
| 3 | * include/asm-parisc/cache.h |
| 4 | */ |
| 5 | |
| 6 | #ifndef __ARCH_PARISC_CACHE_H |
| 7 | #define __ARCH_PARISC_CACHE_H |
| 8 | |
Helge Deller | 3847dab | 2018-10-16 22:38:22 +0200 | [diff] [blame] | 9 | #include <asm/alternative.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | |
| 11 | /* |
John David Anglin | a01fece | 2015-10-14 20:32:11 -0400 | [diff] [blame] | 12 | * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors |
| 13 | * have 32-byte cachelines. The L1 length appears to be 16 bytes but this |
| 14 | * is not clearly documented. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | */ |
John David Anglin | a01fece | 2015-10-14 20:32:11 -0400 | [diff] [blame] | 16 | #define L1_CACHE_BYTES 16 |
| 17 | #define L1_CACHE_SHIFT 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | |
| 19 | #ifndef __ASSEMBLY__ |
| 20 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #define SMP_CACHE_BYTES L1_CACHE_BYTES |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | |
FUJITA Tomonori | 7896bfa | 2010-08-10 18:03:23 -0700 | [diff] [blame] | 23 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES |
| 24 | |
Joe Perches | 33def84 | 2020-10-21 19:36:07 -0700 | [diff] [blame] | 25 | #define __read_mostly __section(".data..read_mostly") |
Kyle McMartin | 804f159 | 2006-03-23 03:00:16 -0800 | [diff] [blame] | 26 | |
Randolph Chung | d6ce862 | 2006-12-12 05:51:54 -0800 | [diff] [blame] | 27 | void parisc_cache_init(void); /* initializes cache-flushing */ |
| 28 | void disable_sr_hashing_asm(int); /* low level support for above */ |
| 29 | void disable_sr_hashing(void); /* turns off space register hashing */ |
| 30 | void free_sid(unsigned long); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 31 | unsigned long alloc_sid(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | |
| 33 | struct seq_file; |
| 34 | extern void show_cache_info(struct seq_file *m); |
| 35 | |
| 36 | extern int split_tlb; |
| 37 | extern int dcache_stride; |
| 38 | extern int icache_stride; |
| 39 | extern struct pdc_cache_info cache_info; |
Randolph Chung | d6ce862 | 2006-12-12 05:51:54 -0800 | [diff] [blame] | 40 | void parisc_setup_cache_timing(void); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | |
Helge Deller | 3847dab | 2018-10-16 22:38:22 +0200 | [diff] [blame] | 42 | #define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" \ |
| 43 | ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ |
John David Anglin | 44224bd | 2019-04-21 19:47:17 -0400 | [diff] [blame] | 44 | : : "r" (addr) : "memory") |
Helge Deller | 3847dab | 2018-10-16 22:38:22 +0200 | [diff] [blame] | 45 | #define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" \ |
| 46 | ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ |
| 47 | ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \ |
John David Anglin | 44224bd | 2019-04-21 19:47:17 -0400 | [diff] [blame] | 48 | : : "r" (addr) : "memory") |
Helge Deller | 3847dab | 2018-10-16 22:38:22 +0200 | [diff] [blame] | 49 | #define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" \ |
| 50 | ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \ |
John David Anglin | 44224bd | 2019-04-21 19:47:17 -0400 | [diff] [blame] | 51 | : : "r" (addr) : "memory") |
Helge Deller | 3847dab | 2018-10-16 22:38:22 +0200 | [diff] [blame] | 52 | |
| 53 | #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \ |
| 54 | ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \ |
| 55 | ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \ |
Helge Deller | 2d94a83 | 2019-04-27 23:57:49 +0200 | [diff] [blame] | 56 | : : "r" (addr) : "memory") |
Helge Deller | 3847dab | 2018-10-16 22:38:22 +0200 | [diff] [blame] | 57 | #define asm_io_sync() asm volatile("sync" \ |
| 58 | ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \ |
Helge Deller | 2d94a83 | 2019-04-27 23:57:49 +0200 | [diff] [blame] | 59 | ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory") |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | |
| 61 | #endif /* ! __ASSEMBLY__ */ |
| 62 | |
| 63 | /* Classes of processor wrt: disabling space register hashing */ |
| 64 | |
| 65 | #define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */ |
| 66 | #define SRHASH_PCXL 1 /* pcxl */ |
| 67 | #define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */ |
| 68 | |
| 69 | #endif |