blob: 937b6bb82b303ce89cfd9b1ba92360144cb71b20 [file] [log] [blame]
Thomas Gleixneraf873fc2019-05-28 09:57:21 -07001// SPDX-License-Identifier: GPL-2.0-only
Ulf Hansson3b01f872012-08-27 15:45:50 +02002/*
3 * PRCMU clock implementation for ux500 platform.
4 *
5 * Copyright (C) 2012 ST-Ericsson SA
6 * Author: Ulf Hansson <ulf.hansson@linaro.org>
Ulf Hansson3b01f872012-08-27 15:45:50 +02007 */
8
9#include <linux/clk-provider.h>
Ulf Hansson3b01f872012-08-27 15:45:50 +020010#include <linux/mfd/dbx500-prcmu.h>
11#include <linux/slab.h>
12#include <linux/io.h>
13#include <linux/err.h>
14#include "clk.h"
15
16#define to_clk_prcmu(_hw) container_of(_hw, struct clk_prcmu, hw)
17
18struct clk_prcmu {
19 struct clk_hw hw;
20 u8 cg_sel;
Ulf Hansson28509852013-03-12 20:26:05 +010021 int is_prepared;
Ulf Hansson3b01f872012-08-27 15:45:50 +020022 int is_enabled;
Ulf Hansson28509852013-03-12 20:26:05 +010023 int opp_requested;
Ulf Hansson3b01f872012-08-27 15:45:50 +020024};
25
26/* PRCMU clock operations. */
27
28static int clk_prcmu_prepare(struct clk_hw *hw)
29{
Ulf Hansson28509852013-03-12 20:26:05 +010030 int ret;
Ulf Hansson3b01f872012-08-27 15:45:50 +020031 struct clk_prcmu *clk = to_clk_prcmu(hw);
Ulf Hansson28509852013-03-12 20:26:05 +010032
33 ret = prcmu_request_clock(clk->cg_sel, true);
34 if (!ret)
35 clk->is_prepared = 1;
36
Sachin Kamat24c039f2013-10-08 16:47:47 +053037 return ret;
Ulf Hansson3b01f872012-08-27 15:45:50 +020038}
39
40static void clk_prcmu_unprepare(struct clk_hw *hw)
41{
42 struct clk_prcmu *clk = to_clk_prcmu(hw);
43 if (prcmu_request_clock(clk->cg_sel, false))
44 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
Stephen Boyd836ee0f2015-08-12 11:42:23 -070045 clk_hw_get_name(hw));
Ulf Hansson28509852013-03-12 20:26:05 +010046 else
47 clk->is_prepared = 0;
48}
49
50static int clk_prcmu_is_prepared(struct clk_hw *hw)
51{
52 struct clk_prcmu *clk = to_clk_prcmu(hw);
53 return clk->is_prepared;
Ulf Hansson3b01f872012-08-27 15:45:50 +020054}
55
56static int clk_prcmu_enable(struct clk_hw *hw)
57{
58 struct clk_prcmu *clk = to_clk_prcmu(hw);
59 clk->is_enabled = 1;
60 return 0;
61}
62
63static void clk_prcmu_disable(struct clk_hw *hw)
64{
65 struct clk_prcmu *clk = to_clk_prcmu(hw);
66 clk->is_enabled = 0;
67}
68
69static int clk_prcmu_is_enabled(struct clk_hw *hw)
70{
71 struct clk_prcmu *clk = to_clk_prcmu(hw);
72 return clk->is_enabled;
73}
74
75static unsigned long clk_prcmu_recalc_rate(struct clk_hw *hw,
76 unsigned long parent_rate)
77{
78 struct clk_prcmu *clk = to_clk_prcmu(hw);
79 return prcmu_clock_rate(clk->cg_sel);
80}
81
82static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate,
83 unsigned long *parent_rate)
84{
85 struct clk_prcmu *clk = to_clk_prcmu(hw);
86 return prcmu_round_clock_rate(clk->cg_sel, rate);
87}
88
89static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate,
90 unsigned long parent_rate)
91{
92 struct clk_prcmu *clk = to_clk_prcmu(hw);
93 return prcmu_set_clock_rate(clk->cg_sel, rate);
94}
95
Ulf Hansson3b01f872012-08-27 15:45:50 +020096static int clk_prcmu_opp_prepare(struct clk_hw *hw)
97{
98 int err;
99 struct clk_prcmu *clk = to_clk_prcmu(hw);
100
Ulf Hansson28509852013-03-12 20:26:05 +0100101 if (!clk->opp_requested) {
102 err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
Stephen Boyd836ee0f2015-08-12 11:42:23 -0700103 (char *)clk_hw_get_name(hw),
Ulf Hansson28509852013-03-12 20:26:05 +0100104 100);
105 if (err) {
106 pr_err("clk_prcmu: %s fail req APE OPP for %s.\n",
Stephen Boyd836ee0f2015-08-12 11:42:23 -0700107 __func__, clk_hw_get_name(hw));
Ulf Hansson28509852013-03-12 20:26:05 +0100108 return err;
109 }
110 clk->opp_requested = 1;
Ulf Hansson3b01f872012-08-27 15:45:50 +0200111 }
112
113 err = prcmu_request_clock(clk->cg_sel, true);
Ulf Hansson28509852013-03-12 20:26:05 +0100114 if (err) {
115 prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
Stephen Boyd836ee0f2015-08-12 11:42:23 -0700116 (char *)clk_hw_get_name(hw));
Ulf Hansson28509852013-03-12 20:26:05 +0100117 clk->opp_requested = 0;
118 return err;
119 }
Ulf Hansson3b01f872012-08-27 15:45:50 +0200120
Ulf Hansson28509852013-03-12 20:26:05 +0100121 clk->is_prepared = 1;
122 return 0;
Ulf Hansson3b01f872012-08-27 15:45:50 +0200123}
124
125static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
126{
127 struct clk_prcmu *clk = to_clk_prcmu(hw);
128
Ulf Hansson28509852013-03-12 20:26:05 +0100129 if (prcmu_request_clock(clk->cg_sel, false)) {
130 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
Stephen Boyd836ee0f2015-08-12 11:42:23 -0700131 clk_hw_get_name(hw));
Ulf Hansson28509852013-03-12 20:26:05 +0100132 return;
133 }
Ulf Hansson3b01f872012-08-27 15:45:50 +0200134
Ulf Hansson28509852013-03-12 20:26:05 +0100135 if (clk->opp_requested) {
136 prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
Stephen Boyd836ee0f2015-08-12 11:42:23 -0700137 (char *)clk_hw_get_name(hw));
Ulf Hansson28509852013-03-12 20:26:05 +0100138 clk->opp_requested = 0;
139 }
140
141 clk->is_prepared = 0;
Ulf Hansson3b01f872012-08-27 15:45:50 +0200142}
143
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200144static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw)
145{
146 int err;
147 struct clk_prcmu *clk = to_clk_prcmu(hw);
148
Ulf Hansson28509852013-03-12 20:26:05 +0100149 if (!clk->opp_requested) {
150 err = prcmu_request_ape_opp_100_voltage(true);
151 if (err) {
152 pr_err("clk_prcmu: %s fail req APE OPP VOLT for %s.\n",
Stephen Boyd836ee0f2015-08-12 11:42:23 -0700153 __func__, clk_hw_get_name(hw));
Ulf Hansson28509852013-03-12 20:26:05 +0100154 return err;
155 }
156 clk->opp_requested = 1;
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200157 }
158
159 err = prcmu_request_clock(clk->cg_sel, true);
Ulf Hansson28509852013-03-12 20:26:05 +0100160 if (err) {
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200161 prcmu_request_ape_opp_100_voltage(false);
Ulf Hansson28509852013-03-12 20:26:05 +0100162 clk->opp_requested = 0;
163 return err;
164 }
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200165
Ulf Hansson28509852013-03-12 20:26:05 +0100166 clk->is_prepared = 1;
167 return 0;
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200168}
169
170static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw)
171{
172 struct clk_prcmu *clk = to_clk_prcmu(hw);
173
Ulf Hansson28509852013-03-12 20:26:05 +0100174 if (prcmu_request_clock(clk->cg_sel, false)) {
175 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
Stephen Boyd836ee0f2015-08-12 11:42:23 -0700176 clk_hw_get_name(hw));
Ulf Hansson28509852013-03-12 20:26:05 +0100177 return;
178 }
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200179
Ulf Hansson28509852013-03-12 20:26:05 +0100180 if (clk->opp_requested) {
181 prcmu_request_ape_opp_100_voltage(false);
182 clk->opp_requested = 0;
183 }
184
185 clk->is_prepared = 0;
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200186}
187
Arvind Yadavdf4f45a2017-08-28 12:32:39 +0530188static const struct clk_ops clk_prcmu_scalable_ops = {
Ulf Hansson3b01f872012-08-27 15:45:50 +0200189 .prepare = clk_prcmu_prepare,
190 .unprepare = clk_prcmu_unprepare,
Ulf Hansson28509852013-03-12 20:26:05 +0100191 .is_prepared = clk_prcmu_is_prepared,
Ulf Hansson3b01f872012-08-27 15:45:50 +0200192 .enable = clk_prcmu_enable,
193 .disable = clk_prcmu_disable,
194 .is_enabled = clk_prcmu_is_enabled,
195 .recalc_rate = clk_prcmu_recalc_rate,
196 .round_rate = clk_prcmu_round_rate,
197 .set_rate = clk_prcmu_set_rate,
198};
199
Arvind Yadavdf4f45a2017-08-28 12:32:39 +0530200static const struct clk_ops clk_prcmu_gate_ops = {
Ulf Hansson3b01f872012-08-27 15:45:50 +0200201 .prepare = clk_prcmu_prepare,
202 .unprepare = clk_prcmu_unprepare,
Ulf Hansson28509852013-03-12 20:26:05 +0100203 .is_prepared = clk_prcmu_is_prepared,
Ulf Hansson3b01f872012-08-27 15:45:50 +0200204 .enable = clk_prcmu_enable,
205 .disable = clk_prcmu_disable,
206 .is_enabled = clk_prcmu_is_enabled,
207 .recalc_rate = clk_prcmu_recalc_rate,
208};
209
Arvind Yadavdf4f45a2017-08-28 12:32:39 +0530210static const struct clk_ops clk_prcmu_scalable_rate_ops = {
Ulf Hanssona816d252012-10-10 13:42:27 +0200211 .is_enabled = clk_prcmu_is_enabled,
212 .recalc_rate = clk_prcmu_recalc_rate,
213 .round_rate = clk_prcmu_round_rate,
214 .set_rate = clk_prcmu_set_rate,
215};
216
Arvind Yadavdf4f45a2017-08-28 12:32:39 +0530217static const struct clk_ops clk_prcmu_rate_ops = {
Ulf Hansson70b1fce2012-08-31 14:21:29 +0200218 .is_enabled = clk_prcmu_is_enabled,
219 .recalc_rate = clk_prcmu_recalc_rate,
220};
221
Arvind Yadavdf4f45a2017-08-28 12:32:39 +0530222static const struct clk_ops clk_prcmu_opp_gate_ops = {
Ulf Hansson3b01f872012-08-27 15:45:50 +0200223 .prepare = clk_prcmu_opp_prepare,
224 .unprepare = clk_prcmu_opp_unprepare,
Ulf Hansson28509852013-03-12 20:26:05 +0100225 .is_prepared = clk_prcmu_is_prepared,
Ulf Hansson3b01f872012-08-27 15:45:50 +0200226 .enable = clk_prcmu_enable,
227 .disable = clk_prcmu_disable,
228 .is_enabled = clk_prcmu_is_enabled,
229 .recalc_rate = clk_prcmu_recalc_rate,
230};
231
Arvind Yadavdf4f45a2017-08-28 12:32:39 +0530232static const struct clk_ops clk_prcmu_opp_volt_scalable_ops = {
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200233 .prepare = clk_prcmu_opp_volt_prepare,
234 .unprepare = clk_prcmu_opp_volt_unprepare,
Ulf Hansson28509852013-03-12 20:26:05 +0100235 .is_prepared = clk_prcmu_is_prepared,
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200236 .enable = clk_prcmu_enable,
237 .disable = clk_prcmu_disable,
238 .is_enabled = clk_prcmu_is_enabled,
239 .recalc_rate = clk_prcmu_recalc_rate,
240 .round_rate = clk_prcmu_round_rate,
241 .set_rate = clk_prcmu_set_rate,
242};
243
Ulf Hansson3b01f872012-08-27 15:45:50 +0200244static struct clk *clk_reg_prcmu(const char *name,
245 const char *parent_name,
246 u8 cg_sel,
247 unsigned long rate,
248 unsigned long flags,
Arvind Yadavdf4f45a2017-08-28 12:32:39 +0530249 const struct clk_ops *clk_prcmu_ops)
Ulf Hansson3b01f872012-08-27 15:45:50 +0200250{
251 struct clk_prcmu *clk;
252 struct clk_init_data clk_prcmu_init;
253 struct clk *clk_reg;
254
255 if (!name) {
256 pr_err("clk_prcmu: %s invalid arguments passed\n", __func__);
257 return ERR_PTR(-EINVAL);
258 }
259
Markus Elfring0b10adb2017-09-27 20:30:53 +0200260 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
Markus Elfring7a294dc2017-09-27 20:23:58 +0200261 if (!clk)
Ulf Hansson3b01f872012-08-27 15:45:50 +0200262 return ERR_PTR(-ENOMEM);
Ulf Hansson3b01f872012-08-27 15:45:50 +0200263
264 clk->cg_sel = cg_sel;
Ulf Hansson28509852013-03-12 20:26:05 +0100265 clk->is_prepared = 1;
Ulf Hansson3b01f872012-08-27 15:45:50 +0200266 clk->is_enabled = 1;
Ulf Hansson28509852013-03-12 20:26:05 +0100267 clk->opp_requested = 0;
Ulf Hansson3b01f872012-08-27 15:45:50 +0200268 /* "rate" can be used for changing the initial frequency */
269 if (rate)
270 prcmu_set_clock_rate(cg_sel, rate);
271
272 clk_prcmu_init.name = name;
273 clk_prcmu_init.ops = clk_prcmu_ops;
274 clk_prcmu_init.flags = flags;
275 clk_prcmu_init.parent_names = (parent_name ? &parent_name : NULL);
276 clk_prcmu_init.num_parents = (parent_name ? 1 : 0);
277 clk->hw.init = &clk_prcmu_init;
278
279 clk_reg = clk_register(NULL, &clk->hw);
280 if (IS_ERR_OR_NULL(clk_reg))
281 goto free_clk;
282
283 return clk_reg;
284
285free_clk:
286 kfree(clk);
287 pr_err("clk_prcmu: %s failed to register clk\n", __func__);
288 return ERR_PTR(-ENOMEM);
289}
290
291struct clk *clk_reg_prcmu_scalable(const char *name,
292 const char *parent_name,
293 u8 cg_sel,
294 unsigned long rate,
295 unsigned long flags)
296{
297 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
298 &clk_prcmu_scalable_ops);
299}
300
301struct clk *clk_reg_prcmu_gate(const char *name,
302 const char *parent_name,
303 u8 cg_sel,
304 unsigned long flags)
305{
306 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
307 &clk_prcmu_gate_ops);
308}
309
Ulf Hanssona816d252012-10-10 13:42:27 +0200310struct clk *clk_reg_prcmu_scalable_rate(const char *name,
311 const char *parent_name,
312 u8 cg_sel,
313 unsigned long rate,
314 unsigned long flags)
315{
316 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
317 &clk_prcmu_scalable_rate_ops);
318}
319
Ulf Hansson70b1fce2012-08-31 14:21:29 +0200320struct clk *clk_reg_prcmu_rate(const char *name,
321 const char *parent_name,
322 u8 cg_sel,
323 unsigned long flags)
324{
325 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
326 &clk_prcmu_rate_ops);
327}
328
Ulf Hansson3b01f872012-08-27 15:45:50 +0200329struct clk *clk_reg_prcmu_opp_gate(const char *name,
330 const char *parent_name,
331 u8 cg_sel,
332 unsigned long flags)
333{
334 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
335 &clk_prcmu_opp_gate_ops);
336}
Ulf Hanssonb0ea0fc2012-09-24 16:43:18 +0200337
338struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
339 const char *parent_name,
340 u8 cg_sel,
341 unsigned long rate,
342 unsigned long flags)
343{
344 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
345 &clk_prcmu_opp_volt_scalable_ops);
346}