Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) |
| 2 | // Copyright(c) 2015-17 Intel Corporation. |
| 3 | |
| 4 | /* |
| 5 | * Soundwire Intel Master Driver |
| 6 | */ |
| 7 | |
| 8 | #include <linux/acpi.h> |
| 9 | #include <linux/delay.h> |
| 10 | #include <linux/interrupt.h> |
| 11 | #include <linux/platform_device.h> |
Vinod Koul | 37a2d22 | 2018-04-26 18:38:58 +0530 | [diff] [blame] | 12 | #include <sound/pcm_params.h> |
| 13 | #include <sound/soc.h> |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 14 | #include <linux/soundwire/sdw_registers.h> |
| 15 | #include <linux/soundwire/sdw.h> |
| 16 | #include <linux/soundwire/sdw_intel.h> |
| 17 | #include "cadence_master.h" |
| 18 | #include "intel.h" |
| 19 | |
| 20 | /* Intel SHIM Registers Definition */ |
| 21 | #define SDW_SHIM_LCAP 0x0 |
| 22 | #define SDW_SHIM_LCTL 0x4 |
| 23 | #define SDW_SHIM_IPPTR 0x8 |
| 24 | #define SDW_SHIM_SYNC 0xC |
| 25 | |
| 26 | #define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * x) |
| 27 | #define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * x) |
| 28 | #define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * x) |
| 29 | #define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * x) |
| 30 | #define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * x) |
| 31 | #define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * x) |
| 32 | |
| 33 | #define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * x) + (0x2 * y)) |
| 34 | #define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * x) + (0x2 * y)) |
| 35 | #define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * x) |
| 36 | #define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * x) |
| 37 | #define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * x) |
| 38 | |
| 39 | #define SDW_SHIM_WAKEEN 0x190 |
| 40 | #define SDW_SHIM_WAKESTS 0x192 |
| 41 | |
| 42 | #define SDW_SHIM_LCTL_SPA BIT(0) |
| 43 | #define SDW_SHIM_LCTL_CPA BIT(8) |
| 44 | |
| 45 | #define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F |
| 46 | #define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0) |
| 47 | #define SDW_SHIM_SYNC_SYNCCPU BIT(15) |
| 48 | #define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16) |
| 49 | #define SDW_SHIM_SYNC_CMDSYNC BIT(16) |
| 50 | #define SDW_SHIM_SYNC_SYNCGO BIT(24) |
| 51 | |
| 52 | #define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0) |
| 53 | #define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4) |
| 54 | #define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8) |
| 55 | |
| 56 | #define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0) |
| 57 | #define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4) |
| 58 | #define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8) |
| 59 | #define SDW_SHIM_PCMSYCM_DIR BIT(15) |
| 60 | |
| 61 | #define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0) |
| 62 | #define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4) |
| 63 | #define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8) |
| 64 | #define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13) |
| 65 | |
| 66 | #define SDW_SHIM_IOCTL_MIF BIT(0) |
| 67 | #define SDW_SHIM_IOCTL_CO BIT(1) |
| 68 | #define SDW_SHIM_IOCTL_COE BIT(2) |
| 69 | #define SDW_SHIM_IOCTL_DO BIT(3) |
| 70 | #define SDW_SHIM_IOCTL_DOE BIT(4) |
| 71 | #define SDW_SHIM_IOCTL_BKE BIT(5) |
| 72 | #define SDW_SHIM_IOCTL_WPDD BIT(6) |
| 73 | #define SDW_SHIM_IOCTL_CIBD BIT(8) |
| 74 | #define SDW_SHIM_IOCTL_DIBD BIT(9) |
| 75 | |
| 76 | #define SDW_SHIM_CTMCTL_DACTQE BIT(0) |
| 77 | #define SDW_SHIM_CTMCTL_DODS BIT(1) |
| 78 | #define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3) |
| 79 | |
| 80 | #define SDW_SHIM_WAKEEN_ENABLE BIT(0) |
| 81 | #define SDW_SHIM_WAKESTS_STATUS BIT(0) |
| 82 | |
| 83 | /* Intel ALH Register definitions */ |
| 84 | #define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * x)) |
| 85 | |
| 86 | #define SDW_ALH_STRMZCFG_DMAT_VAL 0x3 |
| 87 | #define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0) |
| 88 | #define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16) |
| 89 | |
Vinod Koul | c46302e | 2018-04-26 18:39:05 +0530 | [diff] [blame] | 90 | enum intel_pdi_type { |
| 91 | INTEL_PDI_IN = 0, |
| 92 | INTEL_PDI_OUT = 1, |
| 93 | INTEL_PDI_BD = 2, |
| 94 | }; |
| 95 | |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 96 | struct sdw_intel { |
| 97 | struct sdw_cdns cdns; |
| 98 | int instance; |
| 99 | struct sdw_intel_link_res *res; |
| 100 | }; |
| 101 | |
| 102 | #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns) |
| 103 | |
| 104 | /* |
| 105 | * Read, write helpers for HW registers |
| 106 | */ |
| 107 | static inline int intel_readl(void __iomem *base, int offset) |
| 108 | { |
| 109 | return readl(base + offset); |
| 110 | } |
| 111 | |
| 112 | static inline void intel_writel(void __iomem *base, int offset, int value) |
| 113 | { |
| 114 | writel(value, base + offset); |
| 115 | } |
| 116 | |
| 117 | static inline u16 intel_readw(void __iomem *base, int offset) |
| 118 | { |
| 119 | return readw(base + offset); |
| 120 | } |
| 121 | |
| 122 | static inline void intel_writew(void __iomem *base, int offset, u16 value) |
| 123 | { |
| 124 | writew(value, base + offset); |
| 125 | } |
| 126 | |
| 127 | static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask) |
| 128 | { |
| 129 | int timeout = 10; |
| 130 | u32 reg_read; |
| 131 | |
| 132 | writel(value, base + offset); |
| 133 | do { |
| 134 | reg_read = readl(base + offset); |
| 135 | if (!(reg_read & mask)) |
| 136 | return 0; |
| 137 | |
| 138 | timeout--; |
| 139 | udelay(50); |
| 140 | } while (timeout != 0); |
| 141 | |
| 142 | return -EAGAIN; |
| 143 | } |
| 144 | |
| 145 | static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask) |
| 146 | { |
| 147 | int timeout = 10; |
| 148 | u32 reg_read; |
| 149 | |
| 150 | writel(value, base + offset); |
| 151 | do { |
| 152 | reg_read = readl(base + offset); |
| 153 | if (reg_read & mask) |
| 154 | return 0; |
| 155 | |
| 156 | timeout--; |
| 157 | udelay(50); |
| 158 | } while (timeout != 0); |
| 159 | |
| 160 | return -EAGAIN; |
| 161 | } |
| 162 | |
| 163 | /* |
| 164 | * shim ops |
| 165 | */ |
| 166 | |
| 167 | static int intel_link_power_up(struct sdw_intel *sdw) |
| 168 | { |
| 169 | unsigned int link_id = sdw->instance; |
| 170 | void __iomem *shim = sdw->res->shim; |
| 171 | int spa_mask, cpa_mask; |
| 172 | int link_control, ret; |
| 173 | |
| 174 | /* Link power up sequence */ |
| 175 | link_control = intel_readl(shim, SDW_SHIM_LCTL); |
| 176 | spa_mask = (SDW_SHIM_LCTL_SPA << link_id); |
| 177 | cpa_mask = (SDW_SHIM_LCTL_CPA << link_id); |
| 178 | link_control |= spa_mask; |
| 179 | |
| 180 | ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); |
| 181 | if (ret < 0) |
| 182 | return ret; |
| 183 | |
| 184 | sdw->cdns.link_up = true; |
| 185 | return 0; |
| 186 | } |
| 187 | |
| 188 | static int intel_shim_init(struct sdw_intel *sdw) |
| 189 | { |
| 190 | void __iomem *shim = sdw->res->shim; |
| 191 | unsigned int link_id = sdw->instance; |
| 192 | int sync_reg, ret; |
| 193 | u16 ioctl = 0, act = 0; |
| 194 | |
| 195 | /* Initialize Shim */ |
| 196 | ioctl |= SDW_SHIM_IOCTL_BKE; |
| 197 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
| 198 | |
| 199 | ioctl |= SDW_SHIM_IOCTL_WPDD; |
| 200 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
| 201 | |
| 202 | ioctl |= SDW_SHIM_IOCTL_DO; |
| 203 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
| 204 | |
| 205 | ioctl |= SDW_SHIM_IOCTL_DOE; |
| 206 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
| 207 | |
| 208 | /* Switch to MIP from Glue logic */ |
| 209 | ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); |
| 210 | |
| 211 | ioctl &= ~(SDW_SHIM_IOCTL_DOE); |
| 212 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
| 213 | |
| 214 | ioctl &= ~(SDW_SHIM_IOCTL_DO); |
| 215 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
| 216 | |
| 217 | ioctl |= (SDW_SHIM_IOCTL_MIF); |
| 218 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
| 219 | |
| 220 | ioctl &= ~(SDW_SHIM_IOCTL_BKE); |
| 221 | ioctl &= ~(SDW_SHIM_IOCTL_COE); |
| 222 | |
| 223 | intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); |
| 224 | |
| 225 | act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS); |
| 226 | act |= SDW_SHIM_CTMCTL_DACTQE; |
| 227 | act |= SDW_SHIM_CTMCTL_DODS; |
| 228 | intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); |
| 229 | |
| 230 | /* Now set SyncPRD period */ |
| 231 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); |
| 232 | sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL << |
| 233 | SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD)); |
| 234 | |
| 235 | /* Set SyncCPU bit */ |
| 236 | sync_reg |= SDW_SHIM_SYNC_SYNCCPU; |
| 237 | ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, |
| 238 | SDW_SHIM_SYNC_SYNCCPU); |
| 239 | if (ret < 0) |
| 240 | dev_err(sdw->cdns.dev, "Failed to set sync period: %d", ret); |
| 241 | |
| 242 | return ret; |
| 243 | } |
| 244 | |
Vinod Koul | 37a2d22 | 2018-04-26 18:38:58 +0530 | [diff] [blame] | 245 | /* |
| 246 | * PDI routines |
| 247 | */ |
| 248 | static void intel_pdi_init(struct sdw_intel *sdw, |
| 249 | struct sdw_cdns_stream_config *config) |
| 250 | { |
| 251 | void __iomem *shim = sdw->res->shim; |
| 252 | unsigned int link_id = sdw->instance; |
| 253 | int pcm_cap, pdm_cap; |
| 254 | |
| 255 | /* PCM Stream Capability */ |
| 256 | pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id)); |
| 257 | |
| 258 | config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >> |
| 259 | SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS); |
| 260 | config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >> |
| 261 | SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS); |
| 262 | config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >> |
| 263 | SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS); |
| 264 | |
| 265 | /* PDM Stream Capability */ |
| 266 | pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); |
| 267 | |
| 268 | config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >> |
| 269 | SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS); |
| 270 | config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >> |
| 271 | SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS); |
| 272 | config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >> |
| 273 | SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS); |
| 274 | } |
| 275 | |
| 276 | static int |
| 277 | intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm) |
| 278 | { |
| 279 | void __iomem *shim = sdw->res->shim; |
| 280 | unsigned int link_id = sdw->instance; |
| 281 | int count; |
| 282 | |
| 283 | if (pcm) { |
| 284 | count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num)); |
| 285 | } else { |
| 286 | count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); |
| 287 | count = ((count & SDW_SHIM_PDMSCAP_CPSS) >> |
| 288 | SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS)); |
| 289 | } |
| 290 | |
| 291 | /* zero based values for channel count in register */ |
| 292 | count++; |
| 293 | |
| 294 | return count; |
| 295 | } |
| 296 | |
| 297 | static int intel_pdi_get_ch_update(struct sdw_intel *sdw, |
| 298 | struct sdw_cdns_pdi *pdi, |
| 299 | unsigned int num_pdi, |
| 300 | unsigned int *num_ch, bool pcm) |
| 301 | { |
| 302 | int i, ch_count = 0; |
| 303 | |
| 304 | for (i = 0; i < num_pdi; i++) { |
| 305 | pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm); |
| 306 | ch_count += pdi->ch_count; |
| 307 | pdi++; |
| 308 | } |
| 309 | |
| 310 | *num_ch = ch_count; |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | static int intel_pdi_stream_ch_update(struct sdw_intel *sdw, |
| 315 | struct sdw_cdns_streams *stream, bool pcm) |
| 316 | { |
| 317 | intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd, |
| 318 | &stream->num_ch_bd, pcm); |
| 319 | |
| 320 | intel_pdi_get_ch_update(sdw, stream->in, stream->num_in, |
| 321 | &stream->num_ch_in, pcm); |
| 322 | |
| 323 | intel_pdi_get_ch_update(sdw, stream->out, stream->num_out, |
| 324 | &stream->num_ch_out, pcm); |
| 325 | |
| 326 | return 0; |
| 327 | } |
| 328 | |
| 329 | static int intel_pdi_ch_update(struct sdw_intel *sdw) |
| 330 | { |
| 331 | /* First update PCM streams followed by PDM streams */ |
| 332 | intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true); |
| 333 | intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false); |
| 334 | |
| 335 | return 0; |
| 336 | } |
| 337 | |
| 338 | static void |
| 339 | intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) |
| 340 | { |
| 341 | void __iomem *shim = sdw->res->shim; |
| 342 | unsigned int link_id = sdw->instance; |
| 343 | int pdi_conf = 0; |
| 344 | |
| 345 | pdi->intel_alh_id = (link_id * 16) + pdi->num + 5; |
| 346 | |
| 347 | /* |
| 348 | * Program stream parameters to stream SHIM register |
| 349 | * This is applicable for PCM stream only. |
| 350 | */ |
| 351 | if (pdi->type != SDW_STREAM_PCM) |
| 352 | return; |
| 353 | |
| 354 | if (pdi->dir == SDW_DATA_DIR_RX) |
| 355 | pdi_conf |= SDW_SHIM_PCMSYCM_DIR; |
| 356 | else |
| 357 | pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR); |
| 358 | |
| 359 | pdi_conf |= (pdi->intel_alh_id << |
| 360 | SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM)); |
| 361 | pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN)); |
| 362 | pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN)); |
| 363 | |
| 364 | intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); |
| 365 | } |
| 366 | |
| 367 | static void |
| 368 | intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi) |
| 369 | { |
| 370 | void __iomem *alh = sdw->res->alh; |
| 371 | unsigned int link_id = sdw->instance; |
| 372 | unsigned int conf; |
| 373 | |
| 374 | pdi->intel_alh_id = (link_id * 16) + pdi->num + 5; |
| 375 | |
| 376 | /* Program Stream config ALH register */ |
| 377 | conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id)); |
| 378 | |
| 379 | conf |= (SDW_ALH_STRMZCFG_DMAT_VAL << |
| 380 | SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT)); |
| 381 | |
| 382 | conf |= ((pdi->ch_count - 1) << |
| 383 | SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN)); |
| 384 | |
| 385 | intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf); |
| 386 | } |
| 387 | |
Vinod Koul | c46302e | 2018-04-26 18:39:05 +0530 | [diff] [blame] | 388 | static int intel_config_stream(struct sdw_intel *sdw, |
| 389 | struct snd_pcm_substream *substream, |
| 390 | struct snd_soc_dai *dai, |
| 391 | struct snd_pcm_hw_params *hw_params, int link_id) |
| 392 | { |
| 393 | if (sdw->res->ops && sdw->res->ops->config_stream) |
| 394 | return sdw->res->ops->config_stream(sdw->res->arg, |
| 395 | substream, dai, hw_params, link_id); |
| 396 | |
| 397 | return -EIO; |
| 398 | } |
| 399 | |
| 400 | /* |
Shreyas NC | 30246e2 | 2018-07-27 14:44:17 +0530 | [diff] [blame] | 401 | * bank switch routines |
| 402 | */ |
| 403 | |
| 404 | static int intel_pre_bank_switch(struct sdw_bus *bus) |
| 405 | { |
| 406 | struct sdw_cdns *cdns = bus_to_cdns(bus); |
| 407 | struct sdw_intel *sdw = cdns_to_intel(cdns); |
| 408 | void __iomem *shim = sdw->res->shim; |
| 409 | int sync_reg; |
| 410 | |
| 411 | /* Write to register only for multi-link */ |
| 412 | if (!bus->multi_link) |
| 413 | return 0; |
| 414 | |
| 415 | /* Read SYNC register */ |
| 416 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); |
| 417 | sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance; |
| 418 | intel_writel(shim, SDW_SHIM_SYNC, sync_reg); |
| 419 | |
| 420 | return 0; |
| 421 | } |
| 422 | |
| 423 | static int intel_post_bank_switch(struct sdw_bus *bus) |
| 424 | { |
| 425 | struct sdw_cdns *cdns = bus_to_cdns(bus); |
| 426 | struct sdw_intel *sdw = cdns_to_intel(cdns); |
| 427 | void __iomem *shim = sdw->res->shim; |
| 428 | int sync_reg, ret; |
| 429 | |
| 430 | /* Write to register only for multi-link */ |
| 431 | if (!bus->multi_link) |
| 432 | return 0; |
| 433 | |
| 434 | /* Read SYNC register */ |
| 435 | sync_reg = intel_readl(shim, SDW_SHIM_SYNC); |
| 436 | |
| 437 | /* |
| 438 | * post_bank_switch() ops is called from the bus in loop for |
| 439 | * all the Masters in the steam with the expectation that |
| 440 | * we trigger the bankswitch for the only first Master in the list |
| 441 | * and do nothing for the other Masters |
| 442 | * |
| 443 | * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master. |
| 444 | */ |
| 445 | if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) |
| 446 | return 0; |
| 447 | |
| 448 | /* |
| 449 | * Set SyncGO bit to synchronously trigger a bank switch for |
| 450 | * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all |
| 451 | * the Masters. |
| 452 | */ |
| 453 | sync_reg |= SDW_SHIM_SYNC_SYNCGO; |
| 454 | |
| 455 | ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, |
| 456 | SDW_SHIM_SYNC_SYNCGO); |
| 457 | if (ret < 0) |
| 458 | dev_err(sdw->cdns.dev, "Post bank switch failed: %d", ret); |
| 459 | |
| 460 | return ret; |
| 461 | } |
| 462 | |
| 463 | /* |
Vinod Koul | c46302e | 2018-04-26 18:39:05 +0530 | [diff] [blame] | 464 | * DAI routines |
| 465 | */ |
| 466 | |
| 467 | static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw, |
| 468 | u32 ch, u32 dir, bool pcm) |
| 469 | { |
| 470 | struct sdw_cdns *cdns = &sdw->cdns; |
| 471 | struct sdw_cdns_port *port = NULL; |
| 472 | int i, ret = 0; |
| 473 | |
| 474 | for (i = 0; i < cdns->num_ports; i++) { |
| 475 | if (cdns->ports[i].assigned == true) |
| 476 | continue; |
| 477 | |
| 478 | port = &cdns->ports[i]; |
| 479 | port->assigned = true; |
| 480 | port->direction = dir; |
| 481 | port->ch = ch; |
| 482 | break; |
| 483 | } |
| 484 | |
| 485 | if (!port) { |
| 486 | dev_err(cdns->dev, "Unable to find a free port\n"); |
| 487 | return NULL; |
| 488 | } |
| 489 | |
| 490 | if (pcm) { |
| 491 | ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir); |
| 492 | if (ret) |
| 493 | goto out; |
| 494 | |
| 495 | intel_pdi_shim_configure(sdw, port->pdi); |
| 496 | sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi); |
| 497 | |
| 498 | intel_pdi_alh_configure(sdw, port->pdi); |
| 499 | |
| 500 | } else { |
| 501 | ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir); |
| 502 | } |
| 503 | |
| 504 | out: |
| 505 | if (ret) { |
| 506 | port->assigned = false; |
| 507 | port = NULL; |
| 508 | } |
| 509 | |
| 510 | return port; |
| 511 | } |
| 512 | |
| 513 | static void intel_port_cleanup(struct sdw_cdns_dma_data *dma) |
| 514 | { |
| 515 | int i; |
| 516 | |
| 517 | for (i = 0; i < dma->nr_ports; i++) { |
| 518 | if (dma->port[i]) { |
| 519 | dma->port[i]->pdi->assigned = false; |
| 520 | dma->port[i]->pdi = NULL; |
| 521 | dma->port[i]->assigned = false; |
| 522 | dma->port[i] = NULL; |
| 523 | } |
| 524 | } |
| 525 | } |
| 526 | |
| 527 | static int intel_hw_params(struct snd_pcm_substream *substream, |
| 528 | struct snd_pcm_hw_params *params, |
| 529 | struct snd_soc_dai *dai) |
| 530 | { |
| 531 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); |
| 532 | struct sdw_intel *sdw = cdns_to_intel(cdns); |
| 533 | struct sdw_cdns_dma_data *dma; |
| 534 | struct sdw_stream_config sconfig; |
| 535 | struct sdw_port_config *pconfig; |
| 536 | int ret, i, ch, dir; |
| 537 | bool pcm = true; |
| 538 | |
| 539 | dma = snd_soc_dai_get_dma_data(dai, substream); |
| 540 | if (!dma) |
| 541 | return -EIO; |
| 542 | |
| 543 | ch = params_channels(params); |
| 544 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) |
| 545 | dir = SDW_DATA_DIR_RX; |
| 546 | else |
| 547 | dir = SDW_DATA_DIR_TX; |
| 548 | |
| 549 | if (dma->stream_type == SDW_STREAM_PDM) { |
| 550 | /* TODO: Check whether PDM decimator is already in use */ |
| 551 | dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir); |
| 552 | pcm = false; |
| 553 | } else { |
| 554 | dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir); |
| 555 | } |
| 556 | |
| 557 | if (!dma->nr_ports) { |
| 558 | dev_err(dai->dev, "ports/resources not available"); |
| 559 | return -EINVAL; |
| 560 | } |
| 561 | |
| 562 | dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL); |
| 563 | if (!dma->port) |
| 564 | return -ENOMEM; |
| 565 | |
| 566 | for (i = 0; i < dma->nr_ports; i++) { |
| 567 | dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm); |
| 568 | if (!dma->port[i]) { |
| 569 | ret = -EINVAL; |
| 570 | goto port_error; |
| 571 | } |
| 572 | } |
| 573 | |
| 574 | /* Inform DSP about PDI stream number */ |
| 575 | for (i = 0; i < dma->nr_ports; i++) { |
| 576 | ret = intel_config_stream(sdw, substream, dai, params, |
| 577 | dma->port[i]->pdi->intel_alh_id); |
| 578 | if (ret) |
| 579 | goto port_error; |
| 580 | } |
| 581 | |
| 582 | sconfig.direction = dir; |
| 583 | sconfig.ch_count = ch; |
| 584 | sconfig.frame_rate = params_rate(params); |
| 585 | sconfig.type = dma->stream_type; |
| 586 | |
| 587 | if (dma->stream_type == SDW_STREAM_PDM) { |
| 588 | sconfig.frame_rate *= 50; |
| 589 | sconfig.bps = 1; |
| 590 | } else { |
| 591 | sconfig.bps = snd_pcm_format_width(params_format(params)); |
| 592 | } |
| 593 | |
| 594 | /* Port configuration */ |
| 595 | pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL); |
| 596 | if (!pconfig) { |
| 597 | ret = -ENOMEM; |
| 598 | goto port_error; |
| 599 | } |
| 600 | |
| 601 | for (i = 0; i < dma->nr_ports; i++) { |
| 602 | pconfig[i].num = dma->port[i]->num; |
| 603 | pconfig[i].ch_mask = (1 << ch) - 1; |
| 604 | } |
| 605 | |
| 606 | ret = sdw_stream_add_master(&cdns->bus, &sconfig, |
| 607 | pconfig, dma->nr_ports, dma->stream); |
| 608 | if (ret) { |
| 609 | dev_err(cdns->dev, "add master to stream failed:%d", ret); |
| 610 | goto stream_error; |
| 611 | } |
| 612 | |
| 613 | kfree(pconfig); |
| 614 | return ret; |
| 615 | |
| 616 | stream_error: |
| 617 | kfree(pconfig); |
| 618 | port_error: |
| 619 | intel_port_cleanup(dma); |
| 620 | kfree(dma->port); |
| 621 | return ret; |
| 622 | } |
| 623 | |
| 624 | static int |
| 625 | intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) |
| 626 | { |
| 627 | struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai); |
| 628 | struct sdw_cdns_dma_data *dma; |
| 629 | int ret; |
| 630 | |
| 631 | dma = snd_soc_dai_get_dma_data(dai, substream); |
| 632 | if (!dma) |
| 633 | return -EIO; |
| 634 | |
| 635 | ret = sdw_stream_remove_master(&cdns->bus, dma->stream); |
| 636 | if (ret < 0) |
| 637 | dev_err(dai->dev, "remove master from stream %s failed: %d", |
| 638 | dma->stream->name, ret); |
| 639 | |
| 640 | intel_port_cleanup(dma); |
| 641 | kfree(dma->port); |
| 642 | return ret; |
| 643 | } |
| 644 | |
| 645 | static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai, |
| 646 | void *stream, int direction) |
| 647 | { |
| 648 | return cdns_set_sdw_stream(dai, stream, true, direction); |
| 649 | } |
| 650 | |
| 651 | static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai, |
| 652 | void *stream, int direction) |
| 653 | { |
| 654 | return cdns_set_sdw_stream(dai, stream, false, direction); |
| 655 | } |
| 656 | |
Julia Lawall | b163559 | 2018-10-27 15:34:42 +0200 | [diff] [blame] | 657 | static const struct snd_soc_dai_ops intel_pcm_dai_ops = { |
Vinod Koul | c46302e | 2018-04-26 18:39:05 +0530 | [diff] [blame] | 658 | .hw_params = intel_hw_params, |
| 659 | .hw_free = intel_hw_free, |
| 660 | .shutdown = sdw_cdns_shutdown, |
| 661 | .set_sdw_stream = intel_pcm_set_sdw_stream, |
| 662 | }; |
| 663 | |
Julia Lawall | b163559 | 2018-10-27 15:34:42 +0200 | [diff] [blame] | 664 | static const struct snd_soc_dai_ops intel_pdm_dai_ops = { |
Vinod Koul | c46302e | 2018-04-26 18:39:05 +0530 | [diff] [blame] | 665 | .hw_params = intel_hw_params, |
| 666 | .hw_free = intel_hw_free, |
| 667 | .shutdown = sdw_cdns_shutdown, |
| 668 | .set_sdw_stream = intel_pdm_set_sdw_stream, |
| 669 | }; |
| 670 | |
| 671 | static const struct snd_soc_component_driver dai_component = { |
| 672 | .name = "soundwire", |
| 673 | }; |
| 674 | |
| 675 | static int intel_create_dai(struct sdw_cdns *cdns, |
| 676 | struct snd_soc_dai_driver *dais, |
| 677 | enum intel_pdi_type type, |
| 678 | u32 num, u32 off, u32 max_ch, bool pcm) |
| 679 | { |
| 680 | int i; |
| 681 | |
| 682 | if (num == 0) |
| 683 | return 0; |
| 684 | |
| 685 | /* TODO: Read supported rates/formats from hardware */ |
| 686 | for (i = off; i < (off + num); i++) { |
| 687 | dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d", |
| 688 | cdns->instance, i); |
| 689 | if (!dais[i].name) |
| 690 | return -ENOMEM; |
| 691 | |
| 692 | if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) { |
| 693 | dais[i].playback.stream_name = kasprintf(GFP_KERNEL, |
| 694 | "SDW%d Tx%d", |
| 695 | cdns->instance, i); |
| 696 | if (!dais[i].playback.stream_name) { |
| 697 | kfree(dais[i].name); |
| 698 | return -ENOMEM; |
| 699 | } |
| 700 | |
| 701 | dais[i].playback.channels_min = 1; |
| 702 | dais[i].playback.channels_max = max_ch; |
| 703 | dais[i].playback.rates = SNDRV_PCM_RATE_48000; |
| 704 | dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE; |
| 705 | } |
| 706 | |
| 707 | if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) { |
| 708 | dais[i].capture.stream_name = kasprintf(GFP_KERNEL, |
| 709 | "SDW%d Rx%d", |
| 710 | cdns->instance, i); |
| 711 | if (!dais[i].capture.stream_name) { |
| 712 | kfree(dais[i].name); |
| 713 | kfree(dais[i].playback.stream_name); |
| 714 | return -ENOMEM; |
| 715 | } |
| 716 | |
| 717 | dais[i].playback.channels_min = 1; |
| 718 | dais[i].playback.channels_max = max_ch; |
| 719 | dais[i].capture.rates = SNDRV_PCM_RATE_48000; |
| 720 | dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE; |
| 721 | } |
| 722 | |
| 723 | dais[i].id = SDW_DAI_ID_RANGE_START + i; |
| 724 | |
| 725 | if (pcm) |
| 726 | dais[i].ops = &intel_pcm_dai_ops; |
| 727 | else |
| 728 | dais[i].ops = &intel_pdm_dai_ops; |
| 729 | } |
| 730 | |
| 731 | return 0; |
| 732 | } |
| 733 | |
| 734 | static int intel_register_dai(struct sdw_intel *sdw) |
| 735 | { |
| 736 | struct sdw_cdns *cdns = &sdw->cdns; |
| 737 | struct sdw_cdns_streams *stream; |
| 738 | struct snd_soc_dai_driver *dais; |
| 739 | int num_dai, ret, off = 0; |
| 740 | |
| 741 | /* DAIs are created based on total number of PDIs supported */ |
| 742 | num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi; |
| 743 | |
| 744 | dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL); |
| 745 | if (!dais) |
| 746 | return -ENOMEM; |
| 747 | |
| 748 | /* Create PCM DAIs */ |
| 749 | stream = &cdns->pcm; |
| 750 | |
| 751 | ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, |
| 752 | stream->num_in, off, stream->num_ch_in, true); |
| 753 | if (ret) |
| 754 | return ret; |
| 755 | |
| 756 | off += cdns->pcm.num_in; |
| 757 | ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, |
| 758 | cdns->pcm.num_out, off, stream->num_ch_out, true); |
| 759 | if (ret) |
| 760 | return ret; |
| 761 | |
| 762 | off += cdns->pcm.num_out; |
| 763 | ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, |
| 764 | cdns->pcm.num_bd, off, stream->num_ch_bd, true); |
| 765 | if (ret) |
| 766 | return ret; |
| 767 | |
| 768 | /* Create PDM DAIs */ |
| 769 | stream = &cdns->pdm; |
| 770 | off += cdns->pcm.num_bd; |
| 771 | ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, |
| 772 | cdns->pdm.num_in, off, stream->num_ch_in, false); |
| 773 | if (ret) |
| 774 | return ret; |
| 775 | |
| 776 | off += cdns->pdm.num_in; |
| 777 | ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, |
| 778 | cdns->pdm.num_out, off, stream->num_ch_out, false); |
| 779 | if (ret) |
| 780 | return ret; |
| 781 | |
| 782 | off += cdns->pdm.num_bd; |
| 783 | ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, |
| 784 | cdns->pdm.num_bd, off, stream->num_ch_bd, false); |
| 785 | if (ret) |
| 786 | return ret; |
| 787 | |
| 788 | return snd_soc_register_component(cdns->dev, &dai_component, |
| 789 | dais, num_dai); |
| 790 | } |
| 791 | |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 792 | static int intel_prop_read(struct sdw_bus *bus) |
| 793 | { |
| 794 | /* Initialize with default handler to read all DisCo properties */ |
| 795 | sdw_master_read_prop(bus); |
| 796 | |
| 797 | /* BIOS is not giving some values correctly. So, lets override them */ |
| 798 | bus->prop.num_freq = 1; |
| 799 | bus->prop.freq = devm_kcalloc(bus->dev, sizeof(*bus->prop.freq), |
| 800 | bus->prop.num_freq, GFP_KERNEL); |
| 801 | if (!bus->prop.freq) |
| 802 | return -ENOMEM; |
| 803 | |
| 804 | bus->prop.freq[0] = bus->prop.max_freq; |
| 805 | bus->prop.err_threshold = 5; |
| 806 | |
| 807 | return 0; |
| 808 | } |
| 809 | |
Shreyas NC | c91605f | 2018-04-26 18:38:43 +0530 | [diff] [blame] | 810 | static struct sdw_master_ops sdw_intel_ops = { |
| 811 | .read_prop = sdw_master_read_prop, |
| 812 | .xfer_msg = cdns_xfer_msg, |
| 813 | .xfer_msg_defer = cdns_xfer_msg_defer, |
| 814 | .reset_page_addr = cdns_reset_page_addr, |
Vinod Koul | 07abeff | 2018-04-26 18:38:48 +0530 | [diff] [blame] | 815 | .set_bus_conf = cdns_bus_conf, |
Shreyas NC | 30246e2 | 2018-07-27 14:44:17 +0530 | [diff] [blame] | 816 | .pre_bank_switch = intel_pre_bank_switch, |
| 817 | .post_bank_switch = intel_post_bank_switch, |
Shreyas NC | c91605f | 2018-04-26 18:38:43 +0530 | [diff] [blame] | 818 | }; |
| 819 | |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 820 | /* |
| 821 | * probe and init |
| 822 | */ |
| 823 | static int intel_probe(struct platform_device *pdev) |
| 824 | { |
Vinod Koul | 37a2d22 | 2018-04-26 18:38:58 +0530 | [diff] [blame] | 825 | struct sdw_cdns_stream_config config; |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 826 | struct sdw_intel *sdw; |
| 827 | int ret; |
| 828 | |
| 829 | sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL); |
| 830 | if (!sdw) |
| 831 | return -ENOMEM; |
| 832 | |
| 833 | sdw->instance = pdev->id; |
| 834 | sdw->res = dev_get_platdata(&pdev->dev); |
| 835 | sdw->cdns.dev = &pdev->dev; |
| 836 | sdw->cdns.registers = sdw->res->registers; |
| 837 | sdw->cdns.instance = sdw->instance; |
| 838 | sdw->cdns.msg_count = 0; |
| 839 | sdw->cdns.bus.dev = &pdev->dev; |
| 840 | sdw->cdns.bus.link_id = pdev->id; |
| 841 | |
| 842 | sdw_cdns_probe(&sdw->cdns); |
| 843 | |
| 844 | /* Set property read ops */ |
Shreyas NC | c91605f | 2018-04-26 18:38:43 +0530 | [diff] [blame] | 845 | sdw_intel_ops.read_prop = intel_prop_read; |
| 846 | sdw->cdns.bus.ops = &sdw_intel_ops; |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 847 | |
| 848 | platform_set_drvdata(pdev, sdw); |
| 849 | |
| 850 | ret = sdw_add_bus_master(&sdw->cdns.bus); |
| 851 | if (ret) { |
| 852 | dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret); |
| 853 | goto err_master_reg; |
| 854 | } |
| 855 | |
| 856 | /* Initialize shim and controller */ |
| 857 | intel_link_power_up(sdw); |
| 858 | intel_shim_init(sdw); |
| 859 | |
| 860 | ret = sdw_cdns_init(&sdw->cdns); |
| 861 | if (ret) |
| 862 | goto err_init; |
| 863 | |
Colin Ian King | 7094dc2 | 2018-01-08 22:22:43 +0530 | [diff] [blame] | 864 | ret = sdw_cdns_enable_interrupt(&sdw->cdns); |
Vinod Koul | 37a2d22 | 2018-04-26 18:38:58 +0530 | [diff] [blame] | 865 | |
| 866 | /* Read the PDI config and initialize cadence PDI */ |
| 867 | intel_pdi_init(sdw, &config); |
| 868 | ret = sdw_cdns_pdi_init(&sdw->cdns, config); |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 869 | if (ret) |
| 870 | goto err_init; |
| 871 | |
Vinod Koul | 37a2d22 | 2018-04-26 18:38:58 +0530 | [diff] [blame] | 872 | intel_pdi_ch_update(sdw); |
| 873 | |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 874 | /* Acquire IRQ */ |
| 875 | ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, |
| 876 | sdw_cdns_thread, IRQF_SHARED, KBUILD_MODNAME, |
| 877 | &sdw->cdns); |
| 878 | if (ret < 0) { |
| 879 | dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n", |
| 880 | sdw->res->irq); |
| 881 | goto err_init; |
| 882 | } |
| 883 | |
Vinod Koul | c46302e | 2018-04-26 18:39:05 +0530 | [diff] [blame] | 884 | /* Register DAIs */ |
| 885 | ret = intel_register_dai(sdw); |
| 886 | if (ret) { |
| 887 | dev_err(sdw->cdns.dev, "DAI registration failed: %d", ret); |
| 888 | snd_soc_unregister_component(sdw->cdns.dev); |
| 889 | goto err_dai; |
| 890 | } |
| 891 | |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 892 | return 0; |
| 893 | |
Vinod Koul | c46302e | 2018-04-26 18:39:05 +0530 | [diff] [blame] | 894 | err_dai: |
| 895 | free_irq(sdw->res->irq, sdw); |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 896 | err_init: |
| 897 | sdw_delete_bus_master(&sdw->cdns.bus); |
| 898 | err_master_reg: |
| 899 | return ret; |
| 900 | } |
| 901 | |
| 902 | static int intel_remove(struct platform_device *pdev) |
| 903 | { |
| 904 | struct sdw_intel *sdw; |
| 905 | |
| 906 | sdw = platform_get_drvdata(pdev); |
| 907 | |
| 908 | free_irq(sdw->res->irq, sdw); |
Vinod Koul | c46302e | 2018-04-26 18:39:05 +0530 | [diff] [blame] | 909 | snd_soc_unregister_component(sdw->cdns.dev); |
Vinod Koul | 71bb8a1 | 2017-12-14 11:19:43 +0530 | [diff] [blame] | 910 | sdw_delete_bus_master(&sdw->cdns.bus); |
| 911 | |
| 912 | return 0; |
| 913 | } |
| 914 | |
| 915 | static struct platform_driver sdw_intel_drv = { |
| 916 | .probe = intel_probe, |
| 917 | .remove = intel_remove, |
| 918 | .driver = { |
| 919 | .name = "int-sdw", |
| 920 | |
| 921 | }, |
| 922 | }; |
| 923 | |
| 924 | module_platform_driver(sdw_intel_drv); |
| 925 | |
| 926 | MODULE_LICENSE("Dual BSD/GPL"); |
| 927 | MODULE_ALIAS("platform:int-sdw"); |
| 928 | MODULE_DESCRIPTION("Intel Soundwire Master Driver"); |