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Thomas Gleixnera636cd62019-05-19 15:51:34 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Boris BREZILLON7e682b42013-10-11 10:41:25 +02002/*
3 * This header provides constants for AT91 pmc status.
4 *
5 * The constants defined in this header are being used in dts.
Boris BREZILLON7e682b42013-10-11 10:41:25 +02006 */
7
8#ifndef _DT_BINDINGS_CLK_AT91_H
9#define _DT_BINDINGS_CLK_AT91_H
10
Alexandre Bellonid387ff52018-10-16 16:21:47 +020011#define PMC_TYPE_CORE 0
12#define PMC_TYPE_SYSTEM 1
13#define PMC_TYPE_PERIPHERAL 2
14#define PMC_TYPE_GCK 3
Michał Mirosław99767cd2020-05-05 00:37:56 +020015#define PMC_TYPE_PROGRAMMABLE 4
Alexandre Bellonid387ff52018-10-16 16:21:47 +020016
17#define PMC_SLOW 0
18#define PMC_MCK 1
19#define PMC_UTMI 2
20#define PMC_MAIN 3
21#define PMC_MCK2 4
22#define PMC_I2S0_MUX 5
23#define PMC_I2S1_MUX 6
Michał Mirosław03a1ee12020-05-05 00:37:57 +020024#define PMC_PLLACK 7
25#define PMC_PLLBCK 8
26#define PMC_AUDIOPLLCK 9
Alexandre Bellonid387ff52018-10-16 16:21:47 +020027
Eugen Hristev3d86ee12020-11-19 17:43:08 +020028/* SAMA7G5 */
29#define PMC_CPUPLL (PMC_MAIN + 1)
30#define PMC_SYSPLL (PMC_MAIN + 2)
31#define PMC_DDRPLL (PMC_MAIN + 3)
32#define PMC_IMGPLL (PMC_MAIN + 4)
33#define PMC_BAUDPLL (PMC_MAIN + 5)
34#define PMC_AUDIOPMCPLL (PMC_MAIN + 6)
35#define PMC_AUDIOIOPLL (PMC_MAIN + 7)
36#define PMC_ETHPLL (PMC_MAIN + 8)
Claudiu Beznea91f3bf02020-11-19 17:43:17 +020037#define PMC_CPU (PMC_MAIN + 9)
Eugen Hristev3d86ee12020-11-19 17:43:08 +020038
Alexandre Bellonid387ff52018-10-16 16:21:47 +020039#ifndef AT91_PMC_MOSCS
Boris BREZILLON7e682b42013-10-11 10:41:25 +020040#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
41#define AT91_PMC_LOCKA 1 /* PLLA Lock */
42#define AT91_PMC_LOCKB 2 /* PLLB Lock */
43#define AT91_PMC_MCKRDY 3 /* Master Clock */
44#define AT91_PMC_LOCKU 6 /* UPLL Lock */
45#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
46#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
47#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
48#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
Nicolas Ferrea5752e52015-06-18 14:43:29 +020049#define AT91_PMC_GCKRDY 24 /* Generated Clocks */
Alexandre Bellonid387ff52018-10-16 16:21:47 +020050#endif
Boris BREZILLON7e682b42013-10-11 10:41:25 +020051
52#endif