Konrad Dybcio | 80f5451 | 2022-12-13 16:26:16 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (c) 2022, The Linux Foundation. All rights reserved. |
| 4 | * Copyright (c) 2022, Linaro Limited |
| 5 | */ |
| 6 | |
| 7 | #include <linux/clk-provider.h> |
| 8 | #include <linux/module.h> |
| 9 | #include <linux/platform_device.h> |
| 10 | #include <linux/regmap.h> |
| 11 | |
| 12 | #include <dt-bindings/clock/qcom,sm6350-camcc.h> |
| 13 | |
| 14 | #include "clk-alpha-pll.h" |
| 15 | #include "clk-branch.h" |
| 16 | #include "clk-rcg.h" |
| 17 | #include "common.h" |
| 18 | #include "gdsc.h" |
| 19 | |
| 20 | enum { |
| 21 | DT_BI_TCXO, |
| 22 | }; |
| 23 | |
| 24 | enum { |
| 25 | P_BI_TCXO, |
| 26 | P_CAMCC_PLL0_OUT_EVEN, |
| 27 | P_CAMCC_PLL0_OUT_MAIN, |
| 28 | P_CAMCC_PLL1_OUT_EVEN, |
| 29 | P_CAMCC_PLL1_OUT_MAIN, |
| 30 | P_CAMCC_PLL2_OUT_EARLY, |
| 31 | P_CAMCC_PLL2_OUT_MAIN, |
| 32 | P_CAMCC_PLL3_OUT_MAIN, |
| 33 | }; |
| 34 | |
Christophe JAILLET | fcd9354 | 2024-05-10 18:50:00 +0200 | [diff] [blame] | 35 | static const struct pll_vco fabia_vco[] = { |
Konrad Dybcio | 80f5451 | 2022-12-13 16:26:16 +0100 | [diff] [blame] | 36 | { 249600000, 2000000000, 0 }, |
| 37 | }; |
| 38 | |
| 39 | /* 600MHz configuration */ |
| 40 | static const struct alpha_pll_config camcc_pll0_config = { |
| 41 | .l = 0x1f, |
| 42 | .alpha = 0x4000, |
| 43 | .config_ctl_val = 0x20485699, |
| 44 | .config_ctl_hi_val = 0x00002067, |
| 45 | .test_ctl_val = 0x40000000, |
| 46 | .test_ctl_hi_val = 0x00000002, |
| 47 | .user_ctl_val = 0x00000101, |
| 48 | .user_ctl_hi_val = 0x00004805, |
| 49 | }; |
| 50 | |
| 51 | static struct clk_alpha_pll camcc_pll0 = { |
| 52 | .offset = 0x0, |
| 53 | .vco_table = fabia_vco, |
| 54 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 55 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], |
| 56 | .clkr = { |
| 57 | .hw.init = &(struct clk_init_data){ |
| 58 | .name = "camcc_pll0", |
| 59 | .parent_data = &(const struct clk_parent_data){ |
| 60 | .index = DT_BI_TCXO, |
| 61 | }, |
| 62 | .num_parents = 1, |
| 63 | .ops = &clk_alpha_pll_fabia_ops, |
| 64 | }, |
| 65 | }, |
| 66 | }; |
| 67 | |
| 68 | static const struct clk_div_table post_div_table_camcc_pll0_out_even[] = { |
| 69 | { 0x1, 2 }, |
| 70 | { } |
| 71 | }; |
| 72 | |
| 73 | static struct clk_alpha_pll_postdiv camcc_pll0_out_even = { |
| 74 | .offset = 0x0, |
| 75 | .post_div_shift = 8, |
| 76 | .post_div_table = post_div_table_camcc_pll0_out_even, |
| 77 | .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll0_out_even), |
| 78 | .width = 4, |
| 79 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], |
| 80 | .clkr.hw.init = &(struct clk_init_data){ |
| 81 | .name = "camcc_pll0_out_even", |
| 82 | .parent_hws = (const struct clk_hw*[]){ |
| 83 | &camcc_pll0.clkr.hw, |
| 84 | }, |
| 85 | .num_parents = 1, |
| 86 | .flags = CLK_SET_RATE_PARENT, |
| 87 | .ops = &clk_alpha_pll_postdiv_fabia_ops, |
| 88 | }, |
| 89 | }; |
| 90 | |
| 91 | /* 808MHz configuration */ |
| 92 | static const struct alpha_pll_config camcc_pll1_config = { |
| 93 | .l = 0x2a, |
| 94 | .alpha = 0x1555, |
| 95 | .config_ctl_val = 0x20485699, |
| 96 | .config_ctl_hi_val = 0x00002067, |
| 97 | .test_ctl_val = 0x40000000, |
| 98 | .test_ctl_hi_val = 0x00000000, |
| 99 | .user_ctl_val = 0x00000101, |
| 100 | .user_ctl_hi_val = 0x00004805, |
| 101 | }; |
| 102 | |
| 103 | static struct clk_alpha_pll camcc_pll1 = { |
| 104 | .offset = 0x1000, |
| 105 | .vco_table = fabia_vco, |
| 106 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 107 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], |
| 108 | .clkr = { |
| 109 | .hw.init = &(struct clk_init_data){ |
| 110 | .name = "camcc_pll1", |
| 111 | .parent_data = &(const struct clk_parent_data){ |
| 112 | .index = DT_BI_TCXO, |
| 113 | }, |
| 114 | .num_parents = 1, |
| 115 | .ops = &clk_alpha_pll_fabia_ops, |
| 116 | }, |
| 117 | }, |
| 118 | }; |
| 119 | |
| 120 | static const struct clk_div_table post_div_table_camcc_pll1_out_even[] = { |
| 121 | { 0x1, 2 }, |
| 122 | { } |
| 123 | }; |
| 124 | |
| 125 | static struct clk_alpha_pll_postdiv camcc_pll1_out_even = { |
| 126 | .offset = 0x1000, |
| 127 | .post_div_shift = 8, |
| 128 | .post_div_table = post_div_table_camcc_pll1_out_even, |
| 129 | .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll1_out_even), |
| 130 | .width = 4, |
| 131 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], |
| 132 | .clkr.hw.init = &(struct clk_init_data){ |
| 133 | .name = "camcc_pll1_out_even", |
| 134 | .parent_hws = (const struct clk_hw*[]){ |
| 135 | &camcc_pll1.clkr.hw, |
| 136 | }, |
| 137 | .num_parents = 1, |
| 138 | .flags = CLK_SET_RATE_PARENT, |
| 139 | .ops = &clk_alpha_pll_postdiv_fabia_ops, |
| 140 | }, |
| 141 | }; |
| 142 | |
| 143 | /* 1920MHz configuration */ |
| 144 | static const struct alpha_pll_config camcc_pll2_config = { |
| 145 | .l = 0x64, |
| 146 | .alpha = 0x0, |
| 147 | .post_div_val = 0x3 << 8, |
| 148 | .post_div_mask = 0x3 << 8, |
| 149 | .aux_output_mask = BIT(1), |
| 150 | .main_output_mask = BIT(0), |
| 151 | .early_output_mask = BIT(3), |
| 152 | .config_ctl_val = 0x20000800, |
| 153 | .config_ctl_hi_val = 0x400003d2, |
| 154 | .test_ctl_val = 0x04000400, |
| 155 | .test_ctl_hi_val = 0x00004000, |
| 156 | }; |
| 157 | |
| 158 | static struct clk_alpha_pll camcc_pll2 = { |
| 159 | .offset = 0x2000, |
| 160 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], |
| 161 | .clkr = { |
| 162 | .hw.init = &(struct clk_init_data){ |
| 163 | .name = "camcc_pll2", |
| 164 | .parent_data = &(const struct clk_parent_data){ |
| 165 | .index = DT_BI_TCXO, |
| 166 | }, |
| 167 | .num_parents = 1, |
| 168 | .ops = &clk_alpha_pll_agera_ops, |
| 169 | }, |
| 170 | }, |
| 171 | }; |
| 172 | |
| 173 | static struct clk_fixed_factor camcc_pll2_out_early = { |
| 174 | .mult = 1, |
| 175 | .div = 2, |
| 176 | .hw.init = &(struct clk_init_data){ |
| 177 | .name = "camcc_pll2_out_early", |
| 178 | .parent_hws = (const struct clk_hw*[]){ |
| 179 | &camcc_pll2.clkr.hw, |
| 180 | }, |
| 181 | .num_parents = 1, |
| 182 | .ops = &clk_fixed_factor_ops, |
| 183 | }, |
| 184 | }; |
| 185 | |
| 186 | static const struct clk_div_table post_div_table_camcc_pll2_out_main[] = { |
| 187 | { 0x1, 2 }, |
| 188 | { } |
| 189 | }; |
| 190 | |
| 191 | static struct clk_alpha_pll_postdiv camcc_pll2_out_main = { |
| 192 | .offset = 0x2000, |
| 193 | .post_div_shift = 8, |
| 194 | .post_div_table = post_div_table_camcc_pll2_out_main, |
| 195 | .num_post_div = ARRAY_SIZE(post_div_table_camcc_pll2_out_main), |
| 196 | .width = 2, |
| 197 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA], |
| 198 | .clkr.hw.init = &(struct clk_init_data){ |
| 199 | .name = "camcc_pll2_out_main", |
| 200 | .parent_hws = (const struct clk_hw*[]){ |
| 201 | &camcc_pll2.clkr.hw, |
| 202 | }, |
| 203 | .num_parents = 1, |
| 204 | .flags = CLK_SET_RATE_PARENT, |
| 205 | .ops = &clk_alpha_pll_postdiv_ops, |
| 206 | }, |
| 207 | }; |
| 208 | |
| 209 | /* 384MHz configuration */ |
| 210 | static const struct alpha_pll_config camcc_pll3_config = { |
| 211 | .l = 0x14, |
| 212 | .alpha = 0x0, |
| 213 | .config_ctl_val = 0x20485699, |
| 214 | .config_ctl_hi_val = 0x00002067, |
| 215 | .test_ctl_val = 0x40000000, |
| 216 | .test_ctl_hi_val = 0x00000002, |
| 217 | .user_ctl_val = 0x00000001, |
| 218 | .user_ctl_hi_val = 0x00014805, |
| 219 | }; |
| 220 | |
| 221 | static struct clk_alpha_pll camcc_pll3 = { |
| 222 | .offset = 0x3000, |
| 223 | .vco_table = fabia_vco, |
| 224 | .num_vco = ARRAY_SIZE(fabia_vco), |
| 225 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], |
| 226 | .clkr = { |
| 227 | .hw.init = &(struct clk_init_data){ |
| 228 | .name = "camcc_pll3", |
| 229 | .parent_data = &(const struct clk_parent_data){ |
| 230 | .index = DT_BI_TCXO, |
| 231 | }, |
| 232 | .num_parents = 1, |
| 233 | .ops = &clk_alpha_pll_fabia_ops, |
| 234 | }, |
| 235 | }, |
| 236 | }; |
| 237 | |
| 238 | static const struct parent_map camcc_parent_map_0[] = { |
| 239 | { P_BI_TCXO, 0 }, |
| 240 | { P_CAMCC_PLL0_OUT_EVEN, 6 }, |
| 241 | }; |
| 242 | |
| 243 | static const struct clk_parent_data camcc_parent_data_0[] = { |
| 244 | { .fw_name = "bi_tcxo" }, |
| 245 | { .hw = &camcc_pll0_out_even.clkr.hw }, |
| 246 | }; |
| 247 | |
| 248 | static const struct parent_map camcc_parent_map_1[] = { |
| 249 | { P_BI_TCXO, 0 }, |
| 250 | { P_CAMCC_PLL0_OUT_MAIN, 1 }, |
| 251 | { P_CAMCC_PLL1_OUT_EVEN, 3 }, |
| 252 | { P_CAMCC_PLL2_OUT_MAIN, 4 }, |
| 253 | }; |
| 254 | |
| 255 | static const struct clk_parent_data camcc_parent_data_1[] = { |
| 256 | { .fw_name = "bi_tcxo" }, |
| 257 | { .hw = &camcc_pll0.clkr.hw }, |
| 258 | { .hw = &camcc_pll1_out_even.clkr.hw }, |
| 259 | { .hw = &camcc_pll2_out_main.clkr.hw }, |
| 260 | }; |
| 261 | |
| 262 | static const struct parent_map camcc_parent_map_2[] = { |
| 263 | { P_BI_TCXO, 0 }, |
| 264 | { P_CAMCC_PLL0_OUT_MAIN, 1 }, |
| 265 | { P_CAMCC_PLL3_OUT_MAIN, 5 }, |
| 266 | }; |
| 267 | |
| 268 | static const struct clk_parent_data camcc_parent_data_2[] = { |
| 269 | { .fw_name = "bi_tcxo" }, |
| 270 | { .hw = &camcc_pll0.clkr.hw }, |
| 271 | { .hw = &camcc_pll3.clkr.hw }, |
| 272 | }; |
| 273 | |
| 274 | static const struct parent_map camcc_parent_map_3[] = { |
| 275 | { P_BI_TCXO, 0 }, |
| 276 | { P_CAMCC_PLL2_OUT_EARLY, 3 }, |
| 277 | }; |
| 278 | |
| 279 | static const struct clk_parent_data camcc_parent_data_3[] = { |
| 280 | { .fw_name = "bi_tcxo" }, |
| 281 | { .hw = &camcc_pll2_out_early.hw }, |
| 282 | }; |
| 283 | |
| 284 | static const struct parent_map camcc_parent_map_4[] = { |
| 285 | { P_BI_TCXO, 0 }, |
| 286 | { P_CAMCC_PLL0_OUT_MAIN, 1 }, |
| 287 | { P_CAMCC_PLL1_OUT_EVEN, 3 }, |
| 288 | }; |
| 289 | |
| 290 | static const struct clk_parent_data camcc_parent_data_4[] = { |
| 291 | { .fw_name = "bi_tcxo" }, |
| 292 | { .hw = &camcc_pll0.clkr.hw }, |
| 293 | { .hw = &camcc_pll1_out_even.clkr.hw }, |
| 294 | }; |
| 295 | |
| 296 | static const struct parent_map camcc_parent_map_5[] = { |
| 297 | { P_BI_TCXO, 0 }, |
| 298 | { P_CAMCC_PLL0_OUT_MAIN, 1 }, |
| 299 | { P_CAMCC_PLL1_OUT_EVEN, 3 }, |
| 300 | { P_CAMCC_PLL3_OUT_MAIN, 5 }, |
| 301 | }; |
| 302 | |
| 303 | static const struct clk_parent_data camcc_parent_data_5[] = { |
| 304 | { .fw_name = "bi_tcxo" }, |
| 305 | { .hw = &camcc_pll0.clkr.hw }, |
| 306 | { .hw = &camcc_pll1_out_even.clkr.hw }, |
| 307 | { .hw = &camcc_pll3.clkr.hw }, |
| 308 | }; |
| 309 | |
| 310 | static const struct parent_map camcc_parent_map_6[] = { |
| 311 | { P_BI_TCXO, 0 }, |
| 312 | { P_CAMCC_PLL0_OUT_MAIN, 1 }, |
| 313 | { P_CAMCC_PLL2_OUT_MAIN, 4 }, |
| 314 | }; |
| 315 | |
| 316 | static const struct clk_parent_data camcc_parent_data_6[] = { |
| 317 | { .fw_name = "bi_tcxo" }, |
| 318 | { .hw = &camcc_pll0.clkr.hw }, |
| 319 | { .hw = &camcc_pll2_out_main.clkr.hw }, |
| 320 | }; |
| 321 | |
| 322 | static const struct parent_map camcc_parent_map_7[] = { |
| 323 | { P_BI_TCXO, 0 }, |
| 324 | { P_CAMCC_PLL0_OUT_MAIN, 1 }, |
| 325 | { P_CAMCC_PLL1_OUT_MAIN, 2 }, |
| 326 | { P_CAMCC_PLL2_OUT_MAIN, 4 }, |
| 327 | }; |
| 328 | |
| 329 | static const struct clk_parent_data camcc_parent_data_7[] = { |
| 330 | { .fw_name = "bi_tcxo" }, |
| 331 | { .hw = &camcc_pll0.clkr.hw }, |
| 332 | { .hw = &camcc_pll1.clkr.hw }, |
| 333 | { .hw = &camcc_pll2_out_main.clkr.hw }, |
| 334 | }; |
| 335 | |
| 336 | static const struct parent_map camcc_parent_map_8[] = { |
| 337 | { P_BI_TCXO, 0 }, |
| 338 | { P_CAMCC_PLL0_OUT_MAIN, 1 }, |
| 339 | { P_CAMCC_PLL1_OUT_MAIN, 2 }, |
| 340 | }; |
| 341 | |
| 342 | static const struct clk_parent_data camcc_parent_data_8[] = { |
| 343 | { .fw_name = "bi_tcxo" }, |
| 344 | { .hw = &camcc_pll0.clkr.hw }, |
| 345 | { .hw = &camcc_pll1.clkr.hw }, |
| 346 | }; |
| 347 | |
| 348 | static const struct parent_map camcc_parent_map_9[] = { |
| 349 | { P_BI_TCXO, 0 }, |
| 350 | { P_CAMCC_PLL2_OUT_MAIN, 4 }, |
| 351 | }; |
| 352 | |
| 353 | static const struct clk_parent_data camcc_parent_data_9[] = { |
| 354 | { .fw_name = "bi_tcxo" }, |
| 355 | { .hw = &camcc_pll2_out_main.clkr.hw }, |
| 356 | }; |
| 357 | |
| 358 | static const struct freq_tbl ftbl_camcc_bps_clk_src[] = { |
| 359 | F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), |
| 360 | F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), |
| 361 | F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), |
| 362 | F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), |
| 363 | F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), |
| 364 | { } |
| 365 | }; |
| 366 | |
| 367 | static struct clk_rcg2 camcc_bps_clk_src = { |
| 368 | .cmd_rcgr = 0x6010, |
| 369 | .mnd_width = 0, |
| 370 | .hid_width = 5, |
| 371 | .parent_map = camcc_parent_map_1, |
| 372 | .freq_tbl = ftbl_camcc_bps_clk_src, |
| 373 | .clkr.hw.init = &(struct clk_init_data){ |
| 374 | .name = "camcc_bps_clk_src", |
| 375 | .parent_data = camcc_parent_data_1, |
| 376 | .num_parents = ARRAY_SIZE(camcc_parent_data_1), |
| 377 | .ops = &clk_rcg2_ops, |
| 378 | }, |
| 379 | }; |
| 380 | |
| 381 | static const struct freq_tbl ftbl_camcc_cci_0_clk_src[] = { |
| 382 | F(37500000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0), |
| 383 | F(50000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0), |
| 384 | F(100000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0), |
| 385 | { } |
| 386 | }; |
| 387 | |
| 388 | static struct clk_rcg2 camcc_cci_0_clk_src = { |
| 389 | .cmd_rcgr = 0xf004, |
| 390 | .mnd_width = 8, |
| 391 | .hid_width = 5, |
| 392 | .parent_map = camcc_parent_map_0, |
| 393 | .freq_tbl = ftbl_camcc_cci_0_clk_src, |
| 394 | .clkr.hw.init = &(struct clk_init_data){ |
| 395 | .name = "camcc_cci_0_clk_src", |
| 396 | .parent_data = camcc_parent_data_0, |
| 397 | .num_parents = ARRAY_SIZE(camcc_parent_data_0), |
| 398 | .ops = &clk_rcg2_ops, |
| 399 | }, |
| 400 | }; |
| 401 | |
| 402 | static struct clk_rcg2 camcc_cci_1_clk_src = { |
| 403 | .cmd_rcgr = 0x10004, |
| 404 | .mnd_width = 8, |
| 405 | .hid_width = 5, |
| 406 | .parent_map = camcc_parent_map_0, |
| 407 | .freq_tbl = ftbl_camcc_cci_0_clk_src, |
| 408 | .clkr.hw.init = &(struct clk_init_data){ |
| 409 | .name = "camcc_cci_1_clk_src", |
| 410 | .parent_data = camcc_parent_data_0, |
| 411 | .num_parents = ARRAY_SIZE(camcc_parent_data_0), |
| 412 | .ops = &clk_rcg2_ops, |
| 413 | }, |
| 414 | }; |
| 415 | |
| 416 | static const struct freq_tbl ftbl_camcc_cphy_rx_clk_src[] = { |
| 417 | F(150000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0), |
| 418 | F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), |
| 419 | F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0), |
| 420 | F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0), |
| 421 | { } |
| 422 | }; |
| 423 | |
| 424 | static struct clk_rcg2 camcc_cphy_rx_clk_src = { |
| 425 | .cmd_rcgr = 0x9064, |
| 426 | .mnd_width = 0, |
| 427 | .hid_width = 5, |
| 428 | .parent_map = camcc_parent_map_2, |
| 429 | .freq_tbl = ftbl_camcc_cphy_rx_clk_src, |
| 430 | .clkr.hw.init = &(struct clk_init_data){ |
| 431 | .name = "camcc_cphy_rx_clk_src", |
| 432 | .parent_data = camcc_parent_data_2, |
| 433 | .num_parents = ARRAY_SIZE(camcc_parent_data_2), |
| 434 | .ops = &clk_rcg2_ops, |
| 435 | }, |
| 436 | }; |
| 437 | |
| 438 | static const struct freq_tbl ftbl_camcc_csi0phytimer_clk_src[] = { |
| 439 | F(300000000, P_CAMCC_PLL0_OUT_EVEN, 1, 0, 0), |
| 440 | { } |
| 441 | }; |
| 442 | |
| 443 | static struct clk_rcg2 camcc_csi0phytimer_clk_src = { |
| 444 | .cmd_rcgr = 0x5004, |
| 445 | .mnd_width = 0, |
| 446 | .hid_width = 5, |
| 447 | .parent_map = camcc_parent_map_0, |
| 448 | .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, |
| 449 | .clkr.hw.init = &(struct clk_init_data){ |
| 450 | .name = "camcc_csi0phytimer_clk_src", |
| 451 | .parent_data = camcc_parent_data_0, |
| 452 | .num_parents = ARRAY_SIZE(camcc_parent_data_0), |
| 453 | .ops = &clk_rcg2_ops, |
| 454 | }, |
| 455 | }; |
| 456 | |
| 457 | static struct clk_rcg2 camcc_csi1phytimer_clk_src = { |
| 458 | .cmd_rcgr = 0x5028, |
| 459 | .mnd_width = 0, |
| 460 | .hid_width = 5, |
| 461 | .parent_map = camcc_parent_map_0, |
| 462 | .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, |
| 463 | .clkr.hw.init = &(struct clk_init_data){ |
| 464 | .name = "camcc_csi1phytimer_clk_src", |
| 465 | .parent_data = camcc_parent_data_0, |
| 466 | .num_parents = ARRAY_SIZE(camcc_parent_data_0), |
| 467 | .ops = &clk_rcg2_ops, |
| 468 | }, |
| 469 | }; |
| 470 | |
| 471 | static struct clk_rcg2 camcc_csi2phytimer_clk_src = { |
| 472 | .cmd_rcgr = 0x504c, |
| 473 | .mnd_width = 0, |
| 474 | .hid_width = 5, |
| 475 | .parent_map = camcc_parent_map_0, |
| 476 | .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, |
| 477 | .clkr.hw.init = &(struct clk_init_data){ |
| 478 | .name = "camcc_csi2phytimer_clk_src", |
| 479 | .parent_data = camcc_parent_data_0, |
| 480 | .num_parents = ARRAY_SIZE(camcc_parent_data_0), |
| 481 | .ops = &clk_rcg2_ops, |
| 482 | }, |
| 483 | }; |
| 484 | |
| 485 | static struct clk_rcg2 camcc_csi3phytimer_clk_src = { |
| 486 | .cmd_rcgr = 0x5070, |
| 487 | .mnd_width = 0, |
| 488 | .hid_width = 5, |
| 489 | .parent_map = camcc_parent_map_0, |
| 490 | .freq_tbl = ftbl_camcc_csi0phytimer_clk_src, |
| 491 | .clkr.hw.init = &(struct clk_init_data){ |
| 492 | .name = "camcc_csi3phytimer_clk_src", |
| 493 | .parent_data = camcc_parent_data_0, |
| 494 | .num_parents = ARRAY_SIZE(camcc_parent_data_0), |
| 495 | .ops = &clk_rcg2_ops, |
| 496 | }, |
| 497 | }; |
| 498 | |
| 499 | static const struct freq_tbl ftbl_camcc_fast_ahb_clk_src[] = { |
| 500 | F(100000000, P_CAMCC_PLL0_OUT_MAIN, 6, 0, 0), |
| 501 | F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), |
| 502 | F(300000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0), |
| 503 | F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), |
| 504 | { } |
| 505 | }; |
| 506 | |
| 507 | static struct clk_rcg2 camcc_fast_ahb_clk_src = { |
| 508 | .cmd_rcgr = 0x603c, |
| 509 | .mnd_width = 0, |
| 510 | .hid_width = 5, |
| 511 | .parent_map = camcc_parent_map_4, |
| 512 | .freq_tbl = ftbl_camcc_fast_ahb_clk_src, |
| 513 | .clkr.hw.init = &(struct clk_init_data){ |
| 514 | .name = "camcc_fast_ahb_clk_src", |
| 515 | .parent_data = camcc_parent_data_4, |
| 516 | .num_parents = ARRAY_SIZE(camcc_parent_data_4), |
| 517 | .ops = &clk_rcg2_ops, |
| 518 | }, |
| 519 | }; |
| 520 | |
| 521 | static const struct freq_tbl ftbl_camcc_icp_clk_src[] = { |
| 522 | F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0), |
| 523 | F(384000000, P_CAMCC_PLL3_OUT_MAIN, 1, 0, 0), |
| 524 | F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), |
| 525 | F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), |
| 526 | { } |
| 527 | }; |
| 528 | |
| 529 | static struct clk_rcg2 camcc_icp_clk_src = { |
| 530 | .cmd_rcgr = 0xe014, |
| 531 | .mnd_width = 0, |
| 532 | .hid_width = 5, |
| 533 | .parent_map = camcc_parent_map_5, |
| 534 | .freq_tbl = ftbl_camcc_icp_clk_src, |
| 535 | .clkr.hw.init = &(struct clk_init_data){ |
| 536 | .name = "camcc_icp_clk_src", |
| 537 | .parent_data = camcc_parent_data_5, |
| 538 | .num_parents = ARRAY_SIZE(camcc_parent_data_5), |
| 539 | .ops = &clk_rcg2_ops, |
| 540 | }, |
| 541 | }; |
| 542 | |
| 543 | static const struct freq_tbl ftbl_camcc_ife_0_clk_src[] = { |
| 544 | F(240000000, P_CAMCC_PLL0_OUT_MAIN, 2.5, 0, 0), |
| 545 | F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), |
| 546 | F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), |
| 547 | F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), |
| 548 | F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), |
| 549 | { } |
| 550 | }; |
| 551 | |
| 552 | static struct clk_rcg2 camcc_ife_0_clk_src = { |
| 553 | .cmd_rcgr = 0x9010, |
| 554 | .mnd_width = 0, |
| 555 | .hid_width = 5, |
| 556 | .parent_map = camcc_parent_map_1, |
| 557 | .freq_tbl = ftbl_camcc_ife_0_clk_src, |
| 558 | .clkr.hw.init = &(struct clk_init_data){ |
| 559 | .name = "camcc_ife_0_clk_src", |
| 560 | .parent_data = camcc_parent_data_1, |
| 561 | .num_parents = ARRAY_SIZE(camcc_parent_data_1), |
| 562 | .flags = CLK_SET_RATE_PARENT, |
| 563 | .ops = &clk_rcg2_ops, |
| 564 | }, |
| 565 | }; |
| 566 | |
| 567 | static struct clk_rcg2 camcc_ife_0_csid_clk_src = { |
| 568 | .cmd_rcgr = 0x903c, |
| 569 | .mnd_width = 0, |
| 570 | .hid_width = 5, |
| 571 | .parent_map = camcc_parent_map_2, |
| 572 | .freq_tbl = ftbl_camcc_cphy_rx_clk_src, |
| 573 | .clkr.hw.init = &(struct clk_init_data){ |
| 574 | .name = "camcc_ife_0_csid_clk_src", |
| 575 | .parent_data = camcc_parent_data_2, |
| 576 | .num_parents = ARRAY_SIZE(camcc_parent_data_2), |
| 577 | .ops = &clk_rcg2_ops, |
| 578 | }, |
| 579 | }; |
| 580 | |
| 581 | static struct clk_rcg2 camcc_ife_1_clk_src = { |
| 582 | .cmd_rcgr = 0xa010, |
| 583 | .mnd_width = 0, |
| 584 | .hid_width = 5, |
| 585 | .parent_map = camcc_parent_map_1, |
| 586 | .freq_tbl = ftbl_camcc_ife_0_clk_src, |
| 587 | .clkr.hw.init = &(struct clk_init_data){ |
| 588 | .name = "camcc_ife_1_clk_src", |
| 589 | .parent_data = camcc_parent_data_1, |
| 590 | .num_parents = ARRAY_SIZE(camcc_parent_data_1), |
| 591 | .flags = CLK_SET_RATE_PARENT, |
| 592 | .ops = &clk_rcg2_ops, |
| 593 | }, |
| 594 | }; |
| 595 | |
| 596 | static struct clk_rcg2 camcc_ife_1_csid_clk_src = { |
| 597 | .cmd_rcgr = 0xa034, |
| 598 | .mnd_width = 0, |
| 599 | .hid_width = 5, |
| 600 | .parent_map = camcc_parent_map_2, |
| 601 | .freq_tbl = ftbl_camcc_cphy_rx_clk_src, |
| 602 | .clkr.hw.init = &(struct clk_init_data){ |
| 603 | .name = "camcc_ife_1_csid_clk_src", |
| 604 | .parent_data = camcc_parent_data_2, |
| 605 | .num_parents = ARRAY_SIZE(camcc_parent_data_2), |
| 606 | .ops = &clk_rcg2_ops, |
| 607 | }, |
| 608 | }; |
| 609 | |
| 610 | static struct clk_rcg2 camcc_ife_2_clk_src = { |
| 611 | .cmd_rcgr = 0xb00c, |
| 612 | .mnd_width = 0, |
| 613 | .hid_width = 5, |
| 614 | .parent_map = camcc_parent_map_1, |
| 615 | .freq_tbl = ftbl_camcc_ife_0_clk_src, |
| 616 | .clkr.hw.init = &(struct clk_init_data){ |
| 617 | .name = "camcc_ife_2_clk_src", |
| 618 | .parent_data = camcc_parent_data_1, |
| 619 | .num_parents = ARRAY_SIZE(camcc_parent_data_1), |
| 620 | .ops = &clk_rcg2_ops, |
| 621 | }, |
| 622 | }; |
| 623 | |
| 624 | static struct clk_rcg2 camcc_ife_2_csid_clk_src = { |
| 625 | .cmd_rcgr = 0xb030, |
| 626 | .mnd_width = 0, |
| 627 | .hid_width = 5, |
| 628 | .parent_map = camcc_parent_map_2, |
| 629 | .freq_tbl = ftbl_camcc_cphy_rx_clk_src, |
| 630 | .clkr.hw.init = &(struct clk_init_data){ |
| 631 | .name = "camcc_ife_2_csid_clk_src", |
| 632 | .parent_data = camcc_parent_data_2, |
| 633 | .num_parents = ARRAY_SIZE(camcc_parent_data_2), |
| 634 | .ops = &clk_rcg2_ops, |
| 635 | }, |
| 636 | }; |
| 637 | |
| 638 | static const struct freq_tbl ftbl_camcc_ife_lite_clk_src[] = { |
| 639 | F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), |
| 640 | F(400000000, P_CAMCC_PLL0_OUT_MAIN, 1.5, 0, 0), |
| 641 | F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), |
| 642 | F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), |
| 643 | { } |
| 644 | }; |
| 645 | |
| 646 | static struct clk_rcg2 camcc_ife_lite_clk_src = { |
| 647 | .cmd_rcgr = 0xc004, |
| 648 | .mnd_width = 0, |
| 649 | .hid_width = 5, |
| 650 | .parent_map = camcc_parent_map_6, |
| 651 | .freq_tbl = ftbl_camcc_ife_lite_clk_src, |
| 652 | .clkr.hw.init = &(struct clk_init_data){ |
| 653 | .name = "camcc_ife_lite_clk_src", |
| 654 | .parent_data = camcc_parent_data_6, |
| 655 | .num_parents = ARRAY_SIZE(camcc_parent_data_6), |
| 656 | .ops = &clk_rcg2_ops, |
| 657 | }, |
| 658 | }; |
| 659 | |
| 660 | static struct clk_rcg2 camcc_ife_lite_csid_clk_src = { |
| 661 | .cmd_rcgr = 0xc024, |
| 662 | .mnd_width = 0, |
| 663 | .hid_width = 5, |
| 664 | .parent_map = camcc_parent_map_2, |
| 665 | .freq_tbl = ftbl_camcc_cphy_rx_clk_src, |
| 666 | .clkr.hw.init = &(struct clk_init_data){ |
| 667 | .name = "camcc_ife_lite_csid_clk_src", |
| 668 | .parent_data = camcc_parent_data_2, |
| 669 | .num_parents = ARRAY_SIZE(camcc_parent_data_2), |
| 670 | .ops = &clk_rcg2_ops, |
| 671 | }, |
| 672 | }; |
| 673 | |
| 674 | static const struct freq_tbl ftbl_camcc_ipe_0_clk_src[] = { |
| 675 | F(240000000, P_CAMCC_PLL2_OUT_MAIN, 2, 0, 0), |
| 676 | F(320000000, P_CAMCC_PLL2_OUT_MAIN, 1.5, 0, 0), |
| 677 | F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0), |
| 678 | F(538666667, P_CAMCC_PLL1_OUT_MAIN, 1.5, 0, 0), |
| 679 | F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), |
| 680 | { } |
| 681 | }; |
| 682 | |
| 683 | static struct clk_rcg2 camcc_ipe_0_clk_src = { |
| 684 | .cmd_rcgr = 0x7010, |
| 685 | .mnd_width = 0, |
| 686 | .hid_width = 5, |
| 687 | .parent_map = camcc_parent_map_7, |
| 688 | .freq_tbl = ftbl_camcc_ipe_0_clk_src, |
| 689 | .clkr.hw.init = &(struct clk_init_data){ |
| 690 | .name = "camcc_ipe_0_clk_src", |
| 691 | .parent_data = camcc_parent_data_7, |
| 692 | .num_parents = ARRAY_SIZE(camcc_parent_data_7), |
| 693 | .flags = CLK_SET_RATE_PARENT, |
| 694 | .ops = &clk_rcg2_ops, |
| 695 | }, |
| 696 | }; |
| 697 | |
| 698 | static const struct freq_tbl ftbl_camcc_jpeg_clk_src[] = { |
| 699 | F(66666667, P_CAMCC_PLL0_OUT_MAIN, 9, 0, 0), |
| 700 | F(133333333, P_CAMCC_PLL0_OUT_MAIN, 4.5, 0, 0), |
| 701 | F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), |
| 702 | F(404000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0), |
| 703 | F(480000000, P_CAMCC_PLL2_OUT_MAIN, 1, 0, 0), |
| 704 | F(600000000, P_CAMCC_PLL0_OUT_MAIN, 1, 0, 0), |
| 705 | { } |
| 706 | }; |
| 707 | |
| 708 | static struct clk_rcg2 camcc_jpeg_clk_src = { |
| 709 | .cmd_rcgr = 0xd004, |
| 710 | .mnd_width = 0, |
| 711 | .hid_width = 5, |
| 712 | .parent_map = camcc_parent_map_1, |
| 713 | .freq_tbl = ftbl_camcc_jpeg_clk_src, |
| 714 | .clkr.hw.init = &(struct clk_init_data){ |
| 715 | .name = "camcc_jpeg_clk_src", |
| 716 | .parent_data = camcc_parent_data_1, |
| 717 | .num_parents = ARRAY_SIZE(camcc_parent_data_1), |
| 718 | .ops = &clk_rcg2_ops, |
| 719 | }, |
| 720 | }; |
| 721 | |
| 722 | static const struct freq_tbl ftbl_camcc_lrme_clk_src[] = { |
| 723 | F(200000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0), |
| 724 | F(269333333, P_CAMCC_PLL1_OUT_MAIN, 3, 0, 0), |
| 725 | F(323200000, P_CAMCC_PLL1_OUT_MAIN, 2.5, 0, 0), |
| 726 | F(404000000, P_CAMCC_PLL1_OUT_MAIN, 2, 0, 0), |
| 727 | { } |
| 728 | }; |
| 729 | |
| 730 | static struct clk_rcg2 camcc_lrme_clk_src = { |
| 731 | .cmd_rcgr = 0x11004, |
| 732 | .mnd_width = 0, |
| 733 | .hid_width = 5, |
| 734 | .parent_map = camcc_parent_map_8, |
| 735 | .freq_tbl = ftbl_camcc_lrme_clk_src, |
| 736 | .clkr.hw.init = &(struct clk_init_data){ |
| 737 | .name = "camcc_lrme_clk_src", |
| 738 | .parent_data = camcc_parent_data_8, |
| 739 | .num_parents = ARRAY_SIZE(camcc_parent_data_8), |
| 740 | .ops = &clk_rcg2_ops, |
| 741 | }, |
| 742 | }; |
| 743 | |
| 744 | static const struct freq_tbl ftbl_camcc_mclk0_clk_src[] = { |
| 745 | F(19200000, P_CAMCC_PLL2_OUT_EARLY, 1, 1, 50), |
| 746 | F(24000000, P_CAMCC_PLL2_OUT_EARLY, 10, 1, 4), |
| 747 | F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0), |
| 748 | { } |
| 749 | }; |
| 750 | |
| 751 | static struct clk_rcg2 camcc_mclk0_clk_src = { |
| 752 | .cmd_rcgr = 0x4004, |
| 753 | .mnd_width = 8, |
| 754 | .hid_width = 5, |
| 755 | .parent_map = camcc_parent_map_3, |
| 756 | .freq_tbl = ftbl_camcc_mclk0_clk_src, |
| 757 | .clkr.hw.init = &(struct clk_init_data){ |
| 758 | .name = "camcc_mclk0_clk_src", |
| 759 | .parent_data = camcc_parent_data_3, |
| 760 | .num_parents = ARRAY_SIZE(camcc_parent_data_3), |
| 761 | .ops = &clk_rcg2_ops, |
| 762 | }, |
| 763 | }; |
| 764 | |
| 765 | static struct clk_rcg2 camcc_mclk1_clk_src = { |
| 766 | .cmd_rcgr = 0x4024, |
| 767 | .mnd_width = 8, |
| 768 | .hid_width = 5, |
| 769 | .parent_map = camcc_parent_map_3, |
| 770 | .freq_tbl = ftbl_camcc_mclk0_clk_src, |
| 771 | .clkr.hw.init = &(struct clk_init_data){ |
| 772 | .name = "camcc_mclk1_clk_src", |
| 773 | .parent_data = camcc_parent_data_3, |
| 774 | .num_parents = ARRAY_SIZE(camcc_parent_data_3), |
| 775 | .ops = &clk_rcg2_ops, |
| 776 | }, |
| 777 | }; |
| 778 | |
| 779 | static struct clk_rcg2 camcc_mclk2_clk_src = { |
| 780 | .cmd_rcgr = 0x4044, |
| 781 | .mnd_width = 8, |
| 782 | .hid_width = 5, |
| 783 | .parent_map = camcc_parent_map_3, |
| 784 | .freq_tbl = ftbl_camcc_mclk0_clk_src, |
| 785 | .clkr.hw.init = &(struct clk_init_data){ |
| 786 | .name = "camcc_mclk2_clk_src", |
| 787 | .parent_data = camcc_parent_data_3, |
| 788 | .num_parents = ARRAY_SIZE(camcc_parent_data_3), |
| 789 | .ops = &clk_rcg2_ops, |
| 790 | }, |
| 791 | }; |
| 792 | |
| 793 | static struct clk_rcg2 camcc_mclk3_clk_src = { |
| 794 | .cmd_rcgr = 0x4064, |
| 795 | .mnd_width = 8, |
| 796 | .hid_width = 5, |
| 797 | .parent_map = camcc_parent_map_3, |
| 798 | .freq_tbl = ftbl_camcc_mclk0_clk_src, |
| 799 | .clkr.hw.init = &(struct clk_init_data){ |
| 800 | .name = "camcc_mclk3_clk_src", |
| 801 | .parent_data = camcc_parent_data_3, |
| 802 | .num_parents = ARRAY_SIZE(camcc_parent_data_3), |
| 803 | .ops = &clk_rcg2_ops, |
| 804 | }, |
| 805 | }; |
| 806 | |
| 807 | static struct clk_rcg2 camcc_mclk4_clk_src = { |
| 808 | .cmd_rcgr = 0x4084, |
| 809 | .mnd_width = 8, |
| 810 | .hid_width = 5, |
| 811 | .parent_map = camcc_parent_map_3, |
| 812 | .freq_tbl = ftbl_camcc_mclk0_clk_src, |
| 813 | .clkr.hw.init = &(struct clk_init_data){ |
| 814 | .name = "camcc_mclk4_clk_src", |
| 815 | .parent_data = camcc_parent_data_3, |
| 816 | .num_parents = ARRAY_SIZE(camcc_parent_data_3), |
| 817 | .ops = &clk_rcg2_ops, |
| 818 | }, |
| 819 | }; |
| 820 | |
| 821 | static const struct freq_tbl ftbl_camcc_slow_ahb_clk_src[] = { |
| 822 | F(80000000, P_CAMCC_PLL2_OUT_MAIN, 6, 0, 0), |
| 823 | { } |
| 824 | }; |
| 825 | |
| 826 | static struct clk_rcg2 camcc_slow_ahb_clk_src = { |
| 827 | .cmd_rcgr = 0x6058, |
| 828 | .mnd_width = 0, |
| 829 | .hid_width = 5, |
| 830 | .parent_map = camcc_parent_map_9, |
| 831 | .freq_tbl = ftbl_camcc_slow_ahb_clk_src, |
| 832 | .clkr.hw.init = &(struct clk_init_data){ |
| 833 | .name = "camcc_slow_ahb_clk_src", |
| 834 | .parent_data = camcc_parent_data_9, |
| 835 | .num_parents = ARRAY_SIZE(camcc_parent_data_9), |
| 836 | .ops = &clk_rcg2_ops, |
| 837 | }, |
| 838 | }; |
| 839 | |
| 840 | static struct clk_branch camcc_bps_ahb_clk = { |
| 841 | .halt_reg = 0x6070, |
| 842 | .halt_check = BRANCH_HALT, |
| 843 | .clkr = { |
| 844 | .enable_reg = 0x6070, |
| 845 | .enable_mask = BIT(0), |
| 846 | .hw.init = &(struct clk_init_data){ |
| 847 | .name = "camcc_bps_ahb_clk", |
| 848 | .parent_hws = (const struct clk_hw*[]){ |
| 849 | &camcc_slow_ahb_clk_src.clkr.hw |
| 850 | }, |
| 851 | .num_parents = 1, |
| 852 | .flags = CLK_SET_RATE_PARENT, |
| 853 | .ops = &clk_branch2_ops, |
| 854 | }, |
| 855 | }, |
| 856 | }; |
| 857 | |
| 858 | static struct clk_branch camcc_bps_areg_clk = { |
| 859 | .halt_reg = 0x6054, |
| 860 | .halt_check = BRANCH_HALT, |
| 861 | .clkr = { |
| 862 | .enable_reg = 0x6054, |
| 863 | .enable_mask = BIT(0), |
| 864 | .hw.init = &(struct clk_init_data){ |
| 865 | .name = "camcc_bps_areg_clk", |
| 866 | .parent_hws = (const struct clk_hw*[]){ |
| 867 | &camcc_fast_ahb_clk_src.clkr.hw |
| 868 | }, |
| 869 | .num_parents = 1, |
| 870 | .flags = CLK_SET_RATE_PARENT, |
| 871 | .ops = &clk_branch2_ops, |
| 872 | }, |
| 873 | }, |
| 874 | }; |
| 875 | |
| 876 | static struct clk_branch camcc_bps_axi_clk = { |
| 877 | .halt_reg = 0x6038, |
| 878 | .halt_check = BRANCH_HALT, |
| 879 | .clkr = { |
| 880 | .enable_reg = 0x6038, |
| 881 | .enable_mask = BIT(0), |
| 882 | .hw.init = &(struct clk_init_data){ |
| 883 | .name = "camcc_bps_axi_clk", |
| 884 | .ops = &clk_branch2_ops, |
| 885 | }, |
| 886 | }, |
| 887 | }; |
| 888 | |
| 889 | static struct clk_branch camcc_bps_clk = { |
| 890 | .halt_reg = 0x6028, |
| 891 | .halt_check = BRANCH_HALT, |
| 892 | .clkr = { |
| 893 | .enable_reg = 0x6028, |
| 894 | .enable_mask = BIT(0), |
| 895 | .hw.init = &(struct clk_init_data){ |
| 896 | .name = "camcc_bps_clk", |
| 897 | .parent_hws = (const struct clk_hw*[]){ |
| 898 | &camcc_bps_clk_src.clkr.hw |
| 899 | }, |
| 900 | .num_parents = 1, |
| 901 | .flags = CLK_SET_RATE_PARENT, |
| 902 | .ops = &clk_branch2_ops, |
| 903 | }, |
| 904 | }, |
| 905 | }; |
| 906 | |
| 907 | static struct clk_branch camcc_camnoc_axi_clk = { |
| 908 | .halt_reg = 0x13004, |
| 909 | .halt_check = BRANCH_HALT, |
| 910 | .clkr = { |
| 911 | .enable_reg = 0x13004, |
| 912 | .enable_mask = BIT(0), |
| 913 | .hw.init = &(struct clk_init_data){ |
| 914 | .name = "camcc_camnoc_axi_clk", |
| 915 | .ops = &clk_branch2_ops, |
| 916 | }, |
| 917 | }, |
| 918 | }; |
| 919 | |
| 920 | static struct clk_branch camcc_cci_0_clk = { |
| 921 | .halt_reg = 0xf01c, |
| 922 | .halt_check = BRANCH_HALT, |
| 923 | .clkr = { |
| 924 | .enable_reg = 0xf01c, |
| 925 | .enable_mask = BIT(0), |
| 926 | .hw.init = &(struct clk_init_data){ |
| 927 | .name = "camcc_cci_0_clk", |
| 928 | .parent_hws = (const struct clk_hw*[]){ |
| 929 | &camcc_cci_0_clk_src.clkr.hw |
| 930 | }, |
| 931 | .num_parents = 1, |
| 932 | .flags = CLK_SET_RATE_PARENT, |
| 933 | .ops = &clk_branch2_ops, |
| 934 | }, |
| 935 | }, |
| 936 | }; |
| 937 | |
| 938 | static struct clk_branch camcc_cci_1_clk = { |
| 939 | .halt_reg = 0x1001c, |
| 940 | .halt_check = BRANCH_HALT, |
| 941 | .clkr = { |
| 942 | .enable_reg = 0x1001c, |
| 943 | .enable_mask = BIT(0), |
| 944 | .hw.init = &(struct clk_init_data){ |
| 945 | .name = "camcc_cci_1_clk", |
| 946 | .parent_hws = (const struct clk_hw*[]){ |
| 947 | &camcc_cci_1_clk_src.clkr.hw |
| 948 | }, |
| 949 | .num_parents = 1, |
| 950 | .flags = CLK_SET_RATE_PARENT, |
| 951 | .ops = &clk_branch2_ops, |
| 952 | }, |
| 953 | }, |
| 954 | }; |
| 955 | |
| 956 | static struct clk_branch camcc_core_ahb_clk = { |
| 957 | .halt_reg = 0x14010, |
| 958 | .halt_check = BRANCH_HALT_VOTED, |
| 959 | .clkr = { |
| 960 | .enable_reg = 0x14010, |
| 961 | .enable_mask = BIT(0), |
| 962 | .hw.init = &(struct clk_init_data){ |
| 963 | .name = "camcc_core_ahb_clk", |
| 964 | .parent_hws = (const struct clk_hw*[]){ |
| 965 | &camcc_slow_ahb_clk_src.clkr.hw |
| 966 | }, |
| 967 | .num_parents = 1, |
| 968 | .flags = CLK_SET_RATE_PARENT, |
| 969 | .ops = &clk_branch2_ops, |
| 970 | }, |
| 971 | }, |
| 972 | }; |
| 973 | |
| 974 | static struct clk_branch camcc_cpas_ahb_clk = { |
| 975 | .halt_reg = 0x12004, |
| 976 | .halt_check = BRANCH_HALT, |
| 977 | .clkr = { |
| 978 | .enable_reg = 0x12004, |
| 979 | .enable_mask = BIT(0), |
| 980 | .hw.init = &(struct clk_init_data){ |
| 981 | .name = "camcc_cpas_ahb_clk", |
| 982 | .parent_hws = (const struct clk_hw*[]){ |
| 983 | &camcc_slow_ahb_clk_src.clkr.hw |
| 984 | }, |
| 985 | .num_parents = 1, |
| 986 | .flags = CLK_SET_RATE_PARENT, |
| 987 | .ops = &clk_branch2_ops, |
| 988 | }, |
| 989 | }, |
| 990 | }; |
| 991 | |
| 992 | static struct clk_branch camcc_csi0phytimer_clk = { |
| 993 | .halt_reg = 0x501c, |
| 994 | .halt_check = BRANCH_HALT, |
| 995 | .clkr = { |
| 996 | .enable_reg = 0x501c, |
| 997 | .enable_mask = BIT(0), |
| 998 | .hw.init = &(struct clk_init_data){ |
| 999 | .name = "camcc_csi0phytimer_clk", |
| 1000 | .parent_hws = (const struct clk_hw*[]){ |
| 1001 | &camcc_csi0phytimer_clk_src.clkr.hw |
| 1002 | }, |
| 1003 | .num_parents = 1, |
| 1004 | .flags = CLK_SET_RATE_PARENT, |
| 1005 | .ops = &clk_branch2_ops, |
| 1006 | }, |
| 1007 | }, |
| 1008 | }; |
| 1009 | |
| 1010 | static struct clk_branch camcc_csi1phytimer_clk = { |
| 1011 | .halt_reg = 0x5040, |
| 1012 | .halt_check = BRANCH_HALT, |
| 1013 | .clkr = { |
| 1014 | .enable_reg = 0x5040, |
| 1015 | .enable_mask = BIT(0), |
| 1016 | .hw.init = &(struct clk_init_data){ |
| 1017 | .name = "camcc_csi1phytimer_clk", |
| 1018 | .parent_hws = (const struct clk_hw*[]){ |
| 1019 | &camcc_csi1phytimer_clk_src.clkr.hw |
| 1020 | }, |
| 1021 | .num_parents = 1, |
| 1022 | .flags = CLK_SET_RATE_PARENT, |
| 1023 | .ops = &clk_branch2_ops, |
| 1024 | }, |
| 1025 | }, |
| 1026 | }; |
| 1027 | |
| 1028 | static struct clk_branch camcc_csi2phytimer_clk = { |
| 1029 | .halt_reg = 0x5064, |
| 1030 | .halt_check = BRANCH_HALT, |
| 1031 | .clkr = { |
| 1032 | .enable_reg = 0x5064, |
| 1033 | .enable_mask = BIT(0), |
| 1034 | .hw.init = &(struct clk_init_data){ |
| 1035 | .name = "camcc_csi2phytimer_clk", |
| 1036 | .parent_hws = (const struct clk_hw*[]){ |
| 1037 | &camcc_csi2phytimer_clk_src.clkr.hw |
| 1038 | }, |
| 1039 | .num_parents = 1, |
| 1040 | .flags = CLK_SET_RATE_PARENT, |
| 1041 | .ops = &clk_branch2_ops, |
| 1042 | }, |
| 1043 | }, |
| 1044 | }; |
| 1045 | |
| 1046 | static struct clk_branch camcc_csi3phytimer_clk = { |
| 1047 | .halt_reg = 0x5088, |
| 1048 | .halt_check = BRANCH_HALT, |
| 1049 | .clkr = { |
| 1050 | .enable_reg = 0x5088, |
| 1051 | .enable_mask = BIT(0), |
| 1052 | .hw.init = &(struct clk_init_data){ |
| 1053 | .name = "camcc_csi3phytimer_clk", |
| 1054 | .parent_hws = (const struct clk_hw*[]){ |
| 1055 | &camcc_csi3phytimer_clk_src.clkr.hw |
| 1056 | }, |
| 1057 | .num_parents = 1, |
| 1058 | .flags = CLK_SET_RATE_PARENT, |
| 1059 | .ops = &clk_branch2_ops, |
| 1060 | }, |
| 1061 | }, |
| 1062 | }; |
| 1063 | |
| 1064 | static struct clk_branch camcc_csiphy0_clk = { |
| 1065 | .halt_reg = 0x5020, |
| 1066 | .halt_check = BRANCH_HALT, |
| 1067 | .clkr = { |
| 1068 | .enable_reg = 0x5020, |
| 1069 | .enable_mask = BIT(0), |
| 1070 | .hw.init = &(struct clk_init_data){ |
| 1071 | .name = "camcc_csiphy0_clk", |
| 1072 | .parent_hws = (const struct clk_hw*[]){ |
| 1073 | &camcc_cphy_rx_clk_src.clkr.hw |
| 1074 | }, |
| 1075 | .num_parents = 1, |
| 1076 | .flags = CLK_SET_RATE_PARENT, |
| 1077 | .ops = &clk_branch2_ops, |
| 1078 | }, |
| 1079 | }, |
| 1080 | }; |
| 1081 | |
| 1082 | static struct clk_branch camcc_csiphy1_clk = { |
| 1083 | .halt_reg = 0x5044, |
| 1084 | .halt_check = BRANCH_HALT, |
| 1085 | .clkr = { |
| 1086 | .enable_reg = 0x5044, |
| 1087 | .enable_mask = BIT(0), |
| 1088 | .hw.init = &(struct clk_init_data){ |
| 1089 | .name = "camcc_csiphy1_clk", |
| 1090 | .parent_hws = (const struct clk_hw*[]){ |
| 1091 | &camcc_cphy_rx_clk_src.clkr.hw |
| 1092 | }, |
| 1093 | .num_parents = 1, |
| 1094 | .flags = CLK_SET_RATE_PARENT, |
| 1095 | .ops = &clk_branch2_ops, |
| 1096 | }, |
| 1097 | }, |
| 1098 | }; |
| 1099 | |
| 1100 | static struct clk_branch camcc_csiphy2_clk = { |
| 1101 | .halt_reg = 0x5068, |
| 1102 | .halt_check = BRANCH_HALT, |
| 1103 | .clkr = { |
| 1104 | .enable_reg = 0x5068, |
| 1105 | .enable_mask = BIT(0), |
| 1106 | .hw.init = &(struct clk_init_data){ |
| 1107 | .name = "camcc_csiphy2_clk", |
| 1108 | .parent_hws = (const struct clk_hw*[]){ |
| 1109 | &camcc_cphy_rx_clk_src.clkr.hw |
| 1110 | }, |
| 1111 | .num_parents = 1, |
| 1112 | .flags = CLK_SET_RATE_PARENT, |
| 1113 | .ops = &clk_branch2_ops, |
| 1114 | }, |
| 1115 | }, |
| 1116 | }; |
| 1117 | |
| 1118 | static struct clk_branch camcc_csiphy3_clk = { |
| 1119 | .halt_reg = 0x508c, |
| 1120 | .halt_check = BRANCH_HALT, |
| 1121 | .clkr = { |
| 1122 | .enable_reg = 0x508c, |
| 1123 | .enable_mask = BIT(0), |
| 1124 | .hw.init = &(struct clk_init_data){ |
| 1125 | .name = "camcc_csiphy3_clk", |
| 1126 | .parent_hws = (const struct clk_hw*[]){ |
| 1127 | &camcc_cphy_rx_clk_src.clkr.hw |
| 1128 | }, |
| 1129 | .num_parents = 1, |
| 1130 | .flags = CLK_SET_RATE_PARENT, |
| 1131 | .ops = &clk_branch2_ops, |
| 1132 | }, |
| 1133 | }, |
| 1134 | }; |
| 1135 | |
| 1136 | static struct clk_branch camcc_icp_clk = { |
| 1137 | .halt_reg = 0xe02c, |
| 1138 | .halt_check = BRANCH_HALT, |
| 1139 | .clkr = { |
| 1140 | .enable_reg = 0xe02c, |
| 1141 | .enable_mask = BIT(0), |
| 1142 | .hw.init = &(struct clk_init_data){ |
| 1143 | .name = "camcc_icp_clk", |
| 1144 | .parent_hws = (const struct clk_hw*[]){ |
| 1145 | &camcc_icp_clk_src.clkr.hw |
| 1146 | }, |
| 1147 | .num_parents = 1, |
| 1148 | .flags = CLK_SET_RATE_PARENT, |
| 1149 | .ops = &clk_branch2_ops, |
| 1150 | }, |
| 1151 | }, |
| 1152 | }; |
| 1153 | |
| 1154 | static struct clk_branch camcc_icp_ts_clk = { |
| 1155 | .halt_reg = 0xe00c, |
| 1156 | .halt_check = BRANCH_HALT, |
| 1157 | .clkr = { |
| 1158 | .enable_reg = 0xe00c, |
| 1159 | .enable_mask = BIT(0), |
| 1160 | .hw.init = &(struct clk_init_data){ |
| 1161 | .name = "camcc_icp_ts_clk", |
| 1162 | .ops = &clk_branch2_ops, |
| 1163 | }, |
| 1164 | }, |
| 1165 | }; |
| 1166 | |
| 1167 | static struct clk_branch camcc_ife_0_axi_clk = { |
| 1168 | .halt_reg = 0x9080, |
| 1169 | .halt_check = BRANCH_HALT, |
| 1170 | .clkr = { |
| 1171 | .enable_reg = 0x9080, |
| 1172 | .enable_mask = BIT(0), |
| 1173 | .hw.init = &(struct clk_init_data){ |
| 1174 | .name = "camcc_ife_0_axi_clk", |
| 1175 | .ops = &clk_branch2_ops, |
| 1176 | }, |
| 1177 | }, |
| 1178 | }; |
| 1179 | |
| 1180 | static struct clk_branch camcc_ife_0_clk = { |
| 1181 | .halt_reg = 0x9028, |
| 1182 | .halt_check = BRANCH_HALT, |
| 1183 | .clkr = { |
| 1184 | .enable_reg = 0x9028, |
| 1185 | .enable_mask = BIT(0), |
| 1186 | .hw.init = &(struct clk_init_data){ |
| 1187 | .name = "camcc_ife_0_clk", |
| 1188 | .parent_hws = (const struct clk_hw*[]){ |
| 1189 | &camcc_ife_0_clk_src.clkr.hw |
| 1190 | }, |
| 1191 | .num_parents = 1, |
| 1192 | .flags = CLK_SET_RATE_PARENT, |
| 1193 | .ops = &clk_branch2_ops, |
| 1194 | }, |
| 1195 | }, |
| 1196 | }; |
| 1197 | |
| 1198 | static struct clk_branch camcc_ife_0_cphy_rx_clk = { |
| 1199 | .halt_reg = 0x907c, |
| 1200 | .halt_check = BRANCH_HALT, |
| 1201 | .clkr = { |
| 1202 | .enable_reg = 0x907c, |
| 1203 | .enable_mask = BIT(0), |
| 1204 | .hw.init = &(struct clk_init_data){ |
| 1205 | .name = "camcc_ife_0_cphy_rx_clk", |
| 1206 | .parent_hws = (const struct clk_hw*[]){ |
| 1207 | &camcc_cphy_rx_clk_src.clkr.hw |
| 1208 | }, |
| 1209 | .num_parents = 1, |
| 1210 | .flags = CLK_SET_RATE_PARENT, |
| 1211 | .ops = &clk_branch2_ops, |
| 1212 | }, |
| 1213 | }, |
| 1214 | }; |
| 1215 | |
| 1216 | static struct clk_branch camcc_ife_0_csid_clk = { |
| 1217 | .halt_reg = 0x9054, |
| 1218 | .halt_check = BRANCH_HALT, |
| 1219 | .clkr = { |
| 1220 | .enable_reg = 0x9054, |
| 1221 | .enable_mask = BIT(0), |
| 1222 | .hw.init = &(struct clk_init_data){ |
| 1223 | .name = "camcc_ife_0_csid_clk", |
| 1224 | .parent_hws = (const struct clk_hw*[]){ |
| 1225 | &camcc_ife_0_csid_clk_src.clkr.hw |
| 1226 | }, |
| 1227 | .num_parents = 1, |
| 1228 | .flags = CLK_SET_RATE_PARENT, |
| 1229 | .ops = &clk_branch2_ops, |
| 1230 | }, |
| 1231 | }, |
| 1232 | }; |
| 1233 | |
| 1234 | static struct clk_branch camcc_ife_0_dsp_clk = { |
| 1235 | .halt_reg = 0x9038, |
| 1236 | .halt_check = BRANCH_HALT, |
| 1237 | .clkr = { |
| 1238 | .enable_reg = 0x9038, |
| 1239 | .enable_mask = BIT(0), |
| 1240 | .hw.init = &(struct clk_init_data){ |
| 1241 | .name = "camcc_ife_0_dsp_clk", |
| 1242 | .parent_hws = (const struct clk_hw*[]){ |
| 1243 | &camcc_ife_0_clk_src.clkr.hw |
| 1244 | }, |
| 1245 | .num_parents = 1, |
| 1246 | .flags = CLK_SET_RATE_PARENT, |
| 1247 | .ops = &clk_branch2_ops, |
| 1248 | }, |
| 1249 | }, |
| 1250 | }; |
| 1251 | |
| 1252 | static struct clk_branch camcc_ife_1_axi_clk = { |
| 1253 | .halt_reg = 0xa058, |
| 1254 | .halt_check = BRANCH_HALT, |
| 1255 | .clkr = { |
| 1256 | .enable_reg = 0xa058, |
| 1257 | .enable_mask = BIT(0), |
| 1258 | .hw.init = &(struct clk_init_data){ |
| 1259 | .name = "camcc_ife_1_axi_clk", |
| 1260 | .ops = &clk_branch2_ops, |
| 1261 | }, |
| 1262 | }, |
| 1263 | }; |
| 1264 | |
| 1265 | static struct clk_branch camcc_ife_1_clk = { |
| 1266 | .halt_reg = 0xa028, |
| 1267 | .halt_check = BRANCH_HALT, |
| 1268 | .clkr = { |
| 1269 | .enable_reg = 0xa028, |
| 1270 | .enable_mask = BIT(0), |
| 1271 | .hw.init = &(struct clk_init_data){ |
| 1272 | .name = "camcc_ife_1_clk", |
| 1273 | .parent_hws = (const struct clk_hw*[]){ |
| 1274 | &camcc_ife_1_clk_src.clkr.hw |
| 1275 | }, |
| 1276 | .num_parents = 1, |
| 1277 | .flags = CLK_SET_RATE_PARENT, |
| 1278 | .ops = &clk_branch2_ops, |
| 1279 | }, |
| 1280 | }, |
| 1281 | }; |
| 1282 | |
| 1283 | static struct clk_branch camcc_ife_1_cphy_rx_clk = { |
| 1284 | .halt_reg = 0xa054, |
| 1285 | .halt_check = BRANCH_HALT, |
| 1286 | .clkr = { |
| 1287 | .enable_reg = 0xa054, |
| 1288 | .enable_mask = BIT(0), |
| 1289 | .hw.init = &(struct clk_init_data){ |
| 1290 | .name = "camcc_ife_1_cphy_rx_clk", |
| 1291 | .parent_hws = (const struct clk_hw*[]){ |
| 1292 | &camcc_cphy_rx_clk_src.clkr.hw |
| 1293 | }, |
| 1294 | .num_parents = 1, |
| 1295 | .flags = CLK_SET_RATE_PARENT, |
| 1296 | .ops = &clk_branch2_ops, |
| 1297 | }, |
| 1298 | }, |
| 1299 | }; |
| 1300 | |
| 1301 | static struct clk_branch camcc_ife_1_csid_clk = { |
| 1302 | .halt_reg = 0xa04c, |
| 1303 | .halt_check = BRANCH_HALT, |
| 1304 | .clkr = { |
| 1305 | .enable_reg = 0xa04c, |
| 1306 | .enable_mask = BIT(0), |
| 1307 | .hw.init = &(struct clk_init_data){ |
| 1308 | .name = "camcc_ife_1_csid_clk", |
| 1309 | .parent_hws = (const struct clk_hw*[]){ |
| 1310 | &camcc_ife_1_csid_clk_src.clkr.hw |
| 1311 | }, |
| 1312 | .num_parents = 1, |
| 1313 | .flags = CLK_SET_RATE_PARENT, |
| 1314 | .ops = &clk_branch2_ops, |
| 1315 | }, |
| 1316 | }, |
| 1317 | }; |
| 1318 | |
| 1319 | static struct clk_branch camcc_ife_1_dsp_clk = { |
| 1320 | .halt_reg = 0xa030, |
| 1321 | .halt_check = BRANCH_HALT, |
| 1322 | .clkr = { |
| 1323 | .enable_reg = 0xa030, |
| 1324 | .enable_mask = BIT(0), |
| 1325 | .hw.init = &(struct clk_init_data){ |
| 1326 | .name = "camcc_ife_1_dsp_clk", |
| 1327 | .parent_hws = (const struct clk_hw*[]){ |
| 1328 | &camcc_ife_1_clk_src.clkr.hw |
| 1329 | }, |
| 1330 | .num_parents = 1, |
| 1331 | .flags = CLK_SET_RATE_PARENT, |
| 1332 | .ops = &clk_branch2_ops, |
| 1333 | }, |
| 1334 | }, |
| 1335 | }; |
| 1336 | |
| 1337 | static struct clk_branch camcc_ife_2_axi_clk = { |
| 1338 | .halt_reg = 0xb054, |
| 1339 | .halt_check = BRANCH_HALT, |
| 1340 | .clkr = { |
| 1341 | .enable_reg = 0xb054, |
| 1342 | .enable_mask = BIT(0), |
| 1343 | .hw.init = &(struct clk_init_data){ |
| 1344 | .name = "camcc_ife_2_axi_clk", |
| 1345 | .ops = &clk_branch2_ops, |
| 1346 | }, |
| 1347 | }, |
| 1348 | }; |
| 1349 | |
| 1350 | static struct clk_branch camcc_ife_2_clk = { |
| 1351 | .halt_reg = 0xb024, |
| 1352 | .halt_check = BRANCH_HALT, |
| 1353 | .clkr = { |
| 1354 | .enable_reg = 0xb024, |
| 1355 | .enable_mask = BIT(0), |
| 1356 | .hw.init = &(struct clk_init_data){ |
| 1357 | .name = "camcc_ife_2_clk", |
| 1358 | .parent_hws = (const struct clk_hw*[]){ |
| 1359 | &camcc_ife_2_clk_src.clkr.hw |
| 1360 | }, |
| 1361 | .num_parents = 1, |
| 1362 | .flags = CLK_SET_RATE_PARENT, |
| 1363 | .ops = &clk_branch2_ops, |
| 1364 | }, |
| 1365 | }, |
| 1366 | }; |
| 1367 | |
| 1368 | static struct clk_branch camcc_ife_2_cphy_rx_clk = { |
| 1369 | .halt_reg = 0xb050, |
| 1370 | .halt_check = BRANCH_HALT, |
| 1371 | .clkr = { |
| 1372 | .enable_reg = 0xb050, |
| 1373 | .enable_mask = BIT(0), |
| 1374 | .hw.init = &(struct clk_init_data){ |
| 1375 | .name = "camcc_ife_2_cphy_rx_clk", |
| 1376 | .parent_hws = (const struct clk_hw*[]){ |
| 1377 | &camcc_cphy_rx_clk_src.clkr.hw |
| 1378 | }, |
| 1379 | .num_parents = 1, |
| 1380 | .flags = CLK_SET_RATE_PARENT, |
| 1381 | .ops = &clk_branch2_ops, |
| 1382 | }, |
| 1383 | }, |
| 1384 | }; |
| 1385 | |
| 1386 | static struct clk_branch camcc_ife_2_csid_clk = { |
| 1387 | .halt_reg = 0xb048, |
| 1388 | .halt_check = BRANCH_HALT, |
| 1389 | .clkr = { |
| 1390 | .enable_reg = 0xb048, |
| 1391 | .enable_mask = BIT(0), |
| 1392 | .hw.init = &(struct clk_init_data){ |
| 1393 | .name = "camcc_ife_2_csid_clk", |
| 1394 | .parent_hws = (const struct clk_hw*[]){ |
| 1395 | &camcc_ife_2_csid_clk_src.clkr.hw |
| 1396 | }, |
| 1397 | .num_parents = 1, |
| 1398 | .flags = CLK_SET_RATE_PARENT, |
| 1399 | .ops = &clk_branch2_ops, |
| 1400 | }, |
| 1401 | }, |
| 1402 | }; |
| 1403 | |
| 1404 | static struct clk_branch camcc_ife_2_dsp_clk = { |
| 1405 | .halt_reg = 0xb02c, |
| 1406 | .halt_check = BRANCH_HALT, |
| 1407 | .clkr = { |
| 1408 | .enable_reg = 0xb02c, |
| 1409 | .enable_mask = BIT(0), |
| 1410 | .hw.init = &(struct clk_init_data){ |
| 1411 | .name = "camcc_ife_2_dsp_clk", |
| 1412 | .parent_hws = (const struct clk_hw*[]){ |
| 1413 | &camcc_ife_2_clk_src.clkr.hw |
| 1414 | }, |
| 1415 | .num_parents = 1, |
| 1416 | .flags = CLK_SET_RATE_PARENT, |
| 1417 | .ops = &clk_branch2_ops, |
| 1418 | }, |
| 1419 | }, |
| 1420 | }; |
| 1421 | |
| 1422 | static struct clk_branch camcc_ife_lite_clk = { |
| 1423 | .halt_reg = 0xc01c, |
| 1424 | .halt_check = BRANCH_HALT, |
| 1425 | .clkr = { |
| 1426 | .enable_reg = 0xc01c, |
| 1427 | .enable_mask = BIT(0), |
| 1428 | .hw.init = &(struct clk_init_data){ |
| 1429 | .name = "camcc_ife_lite_clk", |
| 1430 | .parent_hws = (const struct clk_hw*[]){ |
| 1431 | &camcc_ife_lite_clk_src.clkr.hw |
| 1432 | }, |
| 1433 | .num_parents = 1, |
| 1434 | .flags = CLK_SET_RATE_PARENT, |
| 1435 | .ops = &clk_branch2_ops, |
| 1436 | }, |
| 1437 | }, |
| 1438 | }; |
| 1439 | |
| 1440 | static struct clk_branch camcc_ife_lite_cphy_rx_clk = { |
| 1441 | .halt_reg = 0xc044, |
| 1442 | .halt_check = BRANCH_HALT, |
| 1443 | .clkr = { |
| 1444 | .enable_reg = 0xc044, |
| 1445 | .enable_mask = BIT(0), |
| 1446 | .hw.init = &(struct clk_init_data){ |
| 1447 | .name = "camcc_ife_lite_cphy_rx_clk", |
| 1448 | .parent_hws = (const struct clk_hw*[]){ |
| 1449 | &camcc_cphy_rx_clk_src.clkr.hw |
| 1450 | }, |
| 1451 | .num_parents = 1, |
| 1452 | .flags = CLK_SET_RATE_PARENT, |
| 1453 | .ops = &clk_branch2_ops, |
| 1454 | }, |
| 1455 | }, |
| 1456 | }; |
| 1457 | |
| 1458 | static struct clk_branch camcc_ife_lite_csid_clk = { |
| 1459 | .halt_reg = 0xc03c, |
| 1460 | .halt_check = BRANCH_HALT, |
| 1461 | .clkr = { |
| 1462 | .enable_reg = 0xc03c, |
| 1463 | .enable_mask = BIT(0), |
| 1464 | .hw.init = &(struct clk_init_data){ |
| 1465 | .name = "camcc_ife_lite_csid_clk", |
| 1466 | .parent_hws = (const struct clk_hw*[]){ |
| 1467 | &camcc_ife_lite_csid_clk_src.clkr.hw |
| 1468 | }, |
| 1469 | .num_parents = 1, |
| 1470 | .flags = CLK_SET_RATE_PARENT, |
| 1471 | .ops = &clk_branch2_ops, |
| 1472 | }, |
| 1473 | }, |
| 1474 | }; |
| 1475 | |
| 1476 | static struct clk_branch camcc_ipe_0_ahb_clk = { |
| 1477 | .halt_reg = 0x7040, |
| 1478 | .halt_check = BRANCH_HALT, |
| 1479 | .clkr = { |
| 1480 | .enable_reg = 0x7040, |
| 1481 | .enable_mask = BIT(0), |
| 1482 | .hw.init = &(struct clk_init_data){ |
| 1483 | .name = "camcc_ipe_0_ahb_clk", |
| 1484 | .parent_hws = (const struct clk_hw*[]){ |
| 1485 | &camcc_slow_ahb_clk_src.clkr.hw |
| 1486 | }, |
| 1487 | .num_parents = 1, |
| 1488 | .flags = CLK_SET_RATE_PARENT, |
| 1489 | .ops = &clk_branch2_ops, |
| 1490 | }, |
| 1491 | }, |
| 1492 | }; |
| 1493 | |
| 1494 | static struct clk_branch camcc_ipe_0_areg_clk = { |
| 1495 | .halt_reg = 0x703c, |
| 1496 | .halt_check = BRANCH_HALT, |
| 1497 | .clkr = { |
| 1498 | .enable_reg = 0x703c, |
| 1499 | .enable_mask = BIT(0), |
| 1500 | .hw.init = &(struct clk_init_data){ |
| 1501 | .name = "camcc_ipe_0_areg_clk", |
| 1502 | .parent_hws = (const struct clk_hw*[]){ |
| 1503 | &camcc_fast_ahb_clk_src.clkr.hw |
| 1504 | }, |
| 1505 | .num_parents = 1, |
| 1506 | .flags = CLK_SET_RATE_PARENT, |
| 1507 | .ops = &clk_branch2_ops, |
| 1508 | }, |
| 1509 | }, |
| 1510 | }; |
| 1511 | |
| 1512 | static struct clk_branch camcc_ipe_0_axi_clk = { |
| 1513 | .halt_reg = 0x7038, |
| 1514 | .halt_check = BRANCH_HALT, |
| 1515 | .clkr = { |
| 1516 | .enable_reg = 0x7038, |
| 1517 | .enable_mask = BIT(0), |
| 1518 | .hw.init = &(struct clk_init_data){ |
| 1519 | .name = "camcc_ipe_0_axi_clk", |
| 1520 | .ops = &clk_branch2_ops, |
| 1521 | }, |
| 1522 | }, |
| 1523 | }; |
| 1524 | |
| 1525 | static struct clk_branch camcc_ipe_0_clk = { |
| 1526 | .halt_reg = 0x7028, |
| 1527 | .halt_check = BRANCH_HALT, |
| 1528 | .clkr = { |
| 1529 | .enable_reg = 0x7028, |
| 1530 | .enable_mask = BIT(0), |
| 1531 | .hw.init = &(struct clk_init_data){ |
| 1532 | .name = "camcc_ipe_0_clk", |
| 1533 | .parent_hws = (const struct clk_hw*[]){ |
| 1534 | &camcc_ipe_0_clk_src.clkr.hw |
| 1535 | }, |
| 1536 | .num_parents = 1, |
| 1537 | .flags = CLK_SET_RATE_PARENT, |
| 1538 | .ops = &clk_branch2_ops, |
| 1539 | }, |
| 1540 | }, |
| 1541 | }; |
| 1542 | |
| 1543 | static struct clk_branch camcc_jpeg_clk = { |
| 1544 | .halt_reg = 0xd01c, |
| 1545 | .halt_check = BRANCH_HALT, |
| 1546 | .clkr = { |
| 1547 | .enable_reg = 0xd01c, |
| 1548 | .enable_mask = BIT(0), |
| 1549 | .hw.init = &(struct clk_init_data){ |
| 1550 | .name = "camcc_jpeg_clk", |
| 1551 | .parent_hws = (const struct clk_hw*[]){ |
| 1552 | &camcc_jpeg_clk_src.clkr.hw |
| 1553 | }, |
| 1554 | .num_parents = 1, |
| 1555 | .flags = CLK_SET_RATE_PARENT, |
| 1556 | .ops = &clk_branch2_ops, |
| 1557 | }, |
| 1558 | }, |
| 1559 | }; |
| 1560 | |
| 1561 | static struct clk_branch camcc_lrme_clk = { |
| 1562 | .halt_reg = 0x1101c, |
| 1563 | .halt_check = BRANCH_HALT, |
| 1564 | .clkr = { |
| 1565 | .enable_reg = 0x1101c, |
| 1566 | .enable_mask = BIT(0), |
| 1567 | .hw.init = &(struct clk_init_data){ |
| 1568 | .name = "camcc_lrme_clk", |
| 1569 | .parent_hws = (const struct clk_hw*[]){ |
| 1570 | &camcc_lrme_clk_src.clkr.hw |
| 1571 | }, |
| 1572 | .num_parents = 1, |
| 1573 | .flags = CLK_SET_RATE_PARENT, |
| 1574 | .ops = &clk_branch2_ops, |
| 1575 | }, |
| 1576 | }, |
| 1577 | }; |
| 1578 | |
| 1579 | static struct clk_branch camcc_mclk0_clk = { |
| 1580 | .halt_reg = 0x401c, |
| 1581 | .halt_check = BRANCH_HALT, |
| 1582 | .clkr = { |
| 1583 | .enable_reg = 0x401c, |
| 1584 | .enable_mask = BIT(0), |
| 1585 | .hw.init = &(struct clk_init_data){ |
| 1586 | .name = "camcc_mclk0_clk", |
| 1587 | .parent_hws = (const struct clk_hw*[]){ |
| 1588 | &camcc_mclk0_clk_src.clkr.hw |
| 1589 | }, |
| 1590 | .num_parents = 1, |
| 1591 | .flags = CLK_SET_RATE_PARENT, |
| 1592 | .ops = &clk_branch2_ops, |
| 1593 | }, |
| 1594 | }, |
| 1595 | }; |
| 1596 | |
| 1597 | static struct clk_branch camcc_mclk1_clk = { |
| 1598 | .halt_reg = 0x403c, |
| 1599 | .halt_check = BRANCH_HALT, |
| 1600 | .clkr = { |
| 1601 | .enable_reg = 0x403c, |
| 1602 | .enable_mask = BIT(0), |
| 1603 | .hw.init = &(struct clk_init_data){ |
| 1604 | .name = "camcc_mclk1_clk", |
| 1605 | .parent_hws = (const struct clk_hw*[]){ |
| 1606 | &camcc_mclk1_clk_src.clkr.hw |
| 1607 | }, |
| 1608 | .num_parents = 1, |
| 1609 | .flags = CLK_SET_RATE_PARENT, |
| 1610 | .ops = &clk_branch2_ops, |
| 1611 | }, |
| 1612 | }, |
| 1613 | }; |
| 1614 | |
| 1615 | static struct clk_branch camcc_mclk2_clk = { |
| 1616 | .halt_reg = 0x405c, |
| 1617 | .halt_check = BRANCH_HALT, |
| 1618 | .clkr = { |
| 1619 | .enable_reg = 0x405c, |
| 1620 | .enable_mask = BIT(0), |
| 1621 | .hw.init = &(struct clk_init_data){ |
| 1622 | .name = "camcc_mclk2_clk", |
| 1623 | .parent_hws = (const struct clk_hw*[]){ |
| 1624 | &camcc_mclk2_clk_src.clkr.hw |
| 1625 | }, |
| 1626 | .num_parents = 1, |
| 1627 | .flags = CLK_SET_RATE_PARENT, |
| 1628 | .ops = &clk_branch2_ops, |
| 1629 | }, |
| 1630 | }, |
| 1631 | }; |
| 1632 | |
| 1633 | static struct clk_branch camcc_mclk3_clk = { |
| 1634 | .halt_reg = 0x407c, |
| 1635 | .halt_check = BRANCH_HALT, |
| 1636 | .clkr = { |
| 1637 | .enable_reg = 0x407c, |
| 1638 | .enable_mask = BIT(0), |
| 1639 | .hw.init = &(struct clk_init_data){ |
| 1640 | .name = "camcc_mclk3_clk", |
| 1641 | .parent_hws = (const struct clk_hw*[]){ |
| 1642 | &camcc_mclk3_clk_src.clkr.hw |
| 1643 | }, |
| 1644 | .num_parents = 1, |
| 1645 | .flags = CLK_SET_RATE_PARENT, |
| 1646 | .ops = &clk_branch2_ops, |
| 1647 | }, |
| 1648 | }, |
| 1649 | }; |
| 1650 | |
| 1651 | static struct clk_branch camcc_mclk4_clk = { |
| 1652 | .halt_reg = 0x409c, |
| 1653 | .halt_check = BRANCH_HALT, |
| 1654 | .clkr = { |
| 1655 | .enable_reg = 0x409c, |
| 1656 | .enable_mask = BIT(0), |
| 1657 | .hw.init = &(struct clk_init_data){ |
| 1658 | .name = "camcc_mclk4_clk", |
| 1659 | .parent_hws = (const struct clk_hw*[]){ |
| 1660 | &camcc_mclk4_clk_src.clkr.hw |
| 1661 | }, |
| 1662 | .num_parents = 1, |
| 1663 | .flags = CLK_SET_RATE_PARENT, |
| 1664 | .ops = &clk_branch2_ops, |
| 1665 | }, |
| 1666 | }, |
| 1667 | }; |
| 1668 | |
| 1669 | static struct clk_branch camcc_soc_ahb_clk = { |
| 1670 | .halt_reg = 0x1400c, |
| 1671 | .halt_check = BRANCH_HALT, |
| 1672 | .clkr = { |
| 1673 | .enable_reg = 0x1400c, |
| 1674 | .enable_mask = BIT(0), |
| 1675 | .hw.init = &(struct clk_init_data){ |
| 1676 | .name = "camcc_soc_ahb_clk", |
| 1677 | .ops = &clk_branch2_ops, |
| 1678 | }, |
| 1679 | }, |
| 1680 | }; |
| 1681 | |
| 1682 | static struct clk_branch camcc_sys_tmr_clk = { |
| 1683 | .halt_reg = 0xe034, |
| 1684 | .halt_check = BRANCH_HALT, |
| 1685 | .clkr = { |
| 1686 | .enable_reg = 0xe034, |
| 1687 | .enable_mask = BIT(0), |
| 1688 | .hw.init = &(struct clk_init_data){ |
| 1689 | .name = "camcc_sys_tmr_clk", |
| 1690 | .ops = &clk_branch2_ops, |
| 1691 | }, |
| 1692 | }, |
| 1693 | }; |
| 1694 | |
| 1695 | static struct gdsc bps_gdsc = { |
| 1696 | .gdscr = 0x6004, |
| 1697 | .pd = { |
| 1698 | .name = "bps_gdsc", |
| 1699 | }, |
| 1700 | .pwrsts = PWRSTS_OFF_ON, |
| 1701 | .flags = VOTABLE, |
| 1702 | }; |
| 1703 | |
| 1704 | static struct gdsc ipe_0_gdsc = { |
| 1705 | .gdscr = 0x7004, |
| 1706 | .pd = { |
| 1707 | .name = "ipe_0_gdsc", |
| 1708 | }, |
| 1709 | .pwrsts = PWRSTS_OFF_ON, |
| 1710 | .flags = VOTABLE, |
| 1711 | }; |
| 1712 | |
| 1713 | static struct gdsc ife_0_gdsc = { |
| 1714 | .gdscr = 0x9004, |
| 1715 | .pd = { |
| 1716 | .name = "ife_0_gdsc", |
| 1717 | }, |
| 1718 | .pwrsts = PWRSTS_OFF_ON, |
| 1719 | }; |
| 1720 | |
| 1721 | static struct gdsc ife_1_gdsc = { |
| 1722 | .gdscr = 0xa004, |
| 1723 | .pd = { |
| 1724 | .name = "ife_1_gdsc", |
| 1725 | }, |
| 1726 | .pwrsts = PWRSTS_OFF_ON, |
| 1727 | }; |
| 1728 | |
| 1729 | static struct gdsc ife_2_gdsc = { |
| 1730 | .gdscr = 0xb004, |
| 1731 | .pd = { |
| 1732 | .name = "ife_2_gdsc", |
| 1733 | }, |
| 1734 | .pwrsts = PWRSTS_OFF_ON, |
| 1735 | }; |
| 1736 | |
| 1737 | static struct gdsc titan_top_gdsc = { |
| 1738 | .gdscr = 0x14004, |
| 1739 | .pd = { |
| 1740 | .name = "titan_top_gdsc", |
| 1741 | }, |
| 1742 | .pwrsts = PWRSTS_OFF_ON, |
| 1743 | }; |
| 1744 | |
Konrad Dybcio | bfc7486 | 2023-01-07 13:04:34 +0100 | [diff] [blame] | 1745 | static struct clk_hw *camcc_sm6350_hws[] = { |
Konrad Dybcio | 80f5451 | 2022-12-13 16:26:16 +0100 | [diff] [blame] | 1746 | [CAMCC_PLL2_OUT_EARLY] = &camcc_pll2_out_early.hw, |
| 1747 | }; |
| 1748 | |
| 1749 | static struct clk_regmap *camcc_sm6350_clocks[] = { |
| 1750 | [CAMCC_BPS_AHB_CLK] = &camcc_bps_ahb_clk.clkr, |
| 1751 | [CAMCC_BPS_AREG_CLK] = &camcc_bps_areg_clk.clkr, |
| 1752 | [CAMCC_BPS_AXI_CLK] = &camcc_bps_axi_clk.clkr, |
| 1753 | [CAMCC_BPS_CLK] = &camcc_bps_clk.clkr, |
| 1754 | [CAMCC_BPS_CLK_SRC] = &camcc_bps_clk_src.clkr, |
| 1755 | [CAMCC_CAMNOC_AXI_CLK] = &camcc_camnoc_axi_clk.clkr, |
| 1756 | [CAMCC_CCI_0_CLK] = &camcc_cci_0_clk.clkr, |
| 1757 | [CAMCC_CCI_0_CLK_SRC] = &camcc_cci_0_clk_src.clkr, |
| 1758 | [CAMCC_CCI_1_CLK] = &camcc_cci_1_clk.clkr, |
| 1759 | [CAMCC_CCI_1_CLK_SRC] = &camcc_cci_1_clk_src.clkr, |
| 1760 | [CAMCC_CORE_AHB_CLK] = &camcc_core_ahb_clk.clkr, |
| 1761 | [CAMCC_CPAS_AHB_CLK] = &camcc_cpas_ahb_clk.clkr, |
| 1762 | [CAMCC_CPHY_RX_CLK_SRC] = &camcc_cphy_rx_clk_src.clkr, |
| 1763 | [CAMCC_CSI0PHYTIMER_CLK] = &camcc_csi0phytimer_clk.clkr, |
| 1764 | [CAMCC_CSI0PHYTIMER_CLK_SRC] = &camcc_csi0phytimer_clk_src.clkr, |
| 1765 | [CAMCC_CSI1PHYTIMER_CLK] = &camcc_csi1phytimer_clk.clkr, |
| 1766 | [CAMCC_CSI1PHYTIMER_CLK_SRC] = &camcc_csi1phytimer_clk_src.clkr, |
| 1767 | [CAMCC_CSI2PHYTIMER_CLK] = &camcc_csi2phytimer_clk.clkr, |
| 1768 | [CAMCC_CSI2PHYTIMER_CLK_SRC] = &camcc_csi2phytimer_clk_src.clkr, |
| 1769 | [CAMCC_CSI3PHYTIMER_CLK] = &camcc_csi3phytimer_clk.clkr, |
| 1770 | [CAMCC_CSI3PHYTIMER_CLK_SRC] = &camcc_csi3phytimer_clk_src.clkr, |
| 1771 | [CAMCC_CSIPHY0_CLK] = &camcc_csiphy0_clk.clkr, |
| 1772 | [CAMCC_CSIPHY1_CLK] = &camcc_csiphy1_clk.clkr, |
| 1773 | [CAMCC_CSIPHY2_CLK] = &camcc_csiphy2_clk.clkr, |
| 1774 | [CAMCC_CSIPHY3_CLK] = &camcc_csiphy3_clk.clkr, |
| 1775 | [CAMCC_FAST_AHB_CLK_SRC] = &camcc_fast_ahb_clk_src.clkr, |
| 1776 | [CAMCC_ICP_CLK] = &camcc_icp_clk.clkr, |
| 1777 | [CAMCC_ICP_CLK_SRC] = &camcc_icp_clk_src.clkr, |
| 1778 | [CAMCC_ICP_TS_CLK] = &camcc_icp_ts_clk.clkr, |
| 1779 | [CAMCC_IFE_0_AXI_CLK] = &camcc_ife_0_axi_clk.clkr, |
| 1780 | [CAMCC_IFE_0_CLK] = &camcc_ife_0_clk.clkr, |
| 1781 | [CAMCC_IFE_0_CLK_SRC] = &camcc_ife_0_clk_src.clkr, |
| 1782 | [CAMCC_IFE_0_CPHY_RX_CLK] = &camcc_ife_0_cphy_rx_clk.clkr, |
| 1783 | [CAMCC_IFE_0_CSID_CLK] = &camcc_ife_0_csid_clk.clkr, |
| 1784 | [CAMCC_IFE_0_CSID_CLK_SRC] = &camcc_ife_0_csid_clk_src.clkr, |
| 1785 | [CAMCC_IFE_0_DSP_CLK] = &camcc_ife_0_dsp_clk.clkr, |
| 1786 | [CAMCC_IFE_1_AXI_CLK] = &camcc_ife_1_axi_clk.clkr, |
| 1787 | [CAMCC_IFE_1_CLK] = &camcc_ife_1_clk.clkr, |
| 1788 | [CAMCC_IFE_1_CLK_SRC] = &camcc_ife_1_clk_src.clkr, |
| 1789 | [CAMCC_IFE_1_CPHY_RX_CLK] = &camcc_ife_1_cphy_rx_clk.clkr, |
| 1790 | [CAMCC_IFE_1_CSID_CLK] = &camcc_ife_1_csid_clk.clkr, |
| 1791 | [CAMCC_IFE_1_CSID_CLK_SRC] = &camcc_ife_1_csid_clk_src.clkr, |
| 1792 | [CAMCC_IFE_1_DSP_CLK] = &camcc_ife_1_dsp_clk.clkr, |
| 1793 | [CAMCC_IFE_2_AXI_CLK] = &camcc_ife_2_axi_clk.clkr, |
| 1794 | [CAMCC_IFE_2_CLK] = &camcc_ife_2_clk.clkr, |
| 1795 | [CAMCC_IFE_2_CLK_SRC] = &camcc_ife_2_clk_src.clkr, |
| 1796 | [CAMCC_IFE_2_CPHY_RX_CLK] = &camcc_ife_2_cphy_rx_clk.clkr, |
| 1797 | [CAMCC_IFE_2_CSID_CLK] = &camcc_ife_2_csid_clk.clkr, |
| 1798 | [CAMCC_IFE_2_CSID_CLK_SRC] = &camcc_ife_2_csid_clk_src.clkr, |
| 1799 | [CAMCC_IFE_2_DSP_CLK] = &camcc_ife_2_dsp_clk.clkr, |
| 1800 | [CAMCC_IFE_LITE_CLK] = &camcc_ife_lite_clk.clkr, |
| 1801 | [CAMCC_IFE_LITE_CLK_SRC] = &camcc_ife_lite_clk_src.clkr, |
| 1802 | [CAMCC_IFE_LITE_CPHY_RX_CLK] = &camcc_ife_lite_cphy_rx_clk.clkr, |
| 1803 | [CAMCC_IFE_LITE_CSID_CLK] = &camcc_ife_lite_csid_clk.clkr, |
| 1804 | [CAMCC_IFE_LITE_CSID_CLK_SRC] = &camcc_ife_lite_csid_clk_src.clkr, |
| 1805 | [CAMCC_IPE_0_AHB_CLK] = &camcc_ipe_0_ahb_clk.clkr, |
| 1806 | [CAMCC_IPE_0_AREG_CLK] = &camcc_ipe_0_areg_clk.clkr, |
| 1807 | [CAMCC_IPE_0_AXI_CLK] = &camcc_ipe_0_axi_clk.clkr, |
| 1808 | [CAMCC_IPE_0_CLK] = &camcc_ipe_0_clk.clkr, |
| 1809 | [CAMCC_IPE_0_CLK_SRC] = &camcc_ipe_0_clk_src.clkr, |
| 1810 | [CAMCC_JPEG_CLK] = &camcc_jpeg_clk.clkr, |
| 1811 | [CAMCC_JPEG_CLK_SRC] = &camcc_jpeg_clk_src.clkr, |
| 1812 | [CAMCC_LRME_CLK] = &camcc_lrme_clk.clkr, |
| 1813 | [CAMCC_LRME_CLK_SRC] = &camcc_lrme_clk_src.clkr, |
| 1814 | [CAMCC_MCLK0_CLK] = &camcc_mclk0_clk.clkr, |
| 1815 | [CAMCC_MCLK0_CLK_SRC] = &camcc_mclk0_clk_src.clkr, |
| 1816 | [CAMCC_MCLK1_CLK] = &camcc_mclk1_clk.clkr, |
| 1817 | [CAMCC_MCLK1_CLK_SRC] = &camcc_mclk1_clk_src.clkr, |
| 1818 | [CAMCC_MCLK2_CLK] = &camcc_mclk2_clk.clkr, |
| 1819 | [CAMCC_MCLK2_CLK_SRC] = &camcc_mclk2_clk_src.clkr, |
| 1820 | [CAMCC_MCLK3_CLK] = &camcc_mclk3_clk.clkr, |
| 1821 | [CAMCC_MCLK3_CLK_SRC] = &camcc_mclk3_clk_src.clkr, |
| 1822 | [CAMCC_MCLK4_CLK] = &camcc_mclk4_clk.clkr, |
| 1823 | [CAMCC_MCLK4_CLK_SRC] = &camcc_mclk4_clk_src.clkr, |
| 1824 | [CAMCC_PLL0] = &camcc_pll0.clkr, |
| 1825 | [CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.clkr, |
| 1826 | [CAMCC_PLL1] = &camcc_pll1.clkr, |
| 1827 | [CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.clkr, |
| 1828 | [CAMCC_PLL2] = &camcc_pll2.clkr, |
| 1829 | [CAMCC_PLL2_OUT_MAIN] = &camcc_pll2_out_main.clkr, |
| 1830 | [CAMCC_PLL3] = &camcc_pll3.clkr, |
| 1831 | [CAMCC_SLOW_AHB_CLK_SRC] = &camcc_slow_ahb_clk_src.clkr, |
| 1832 | [CAMCC_SOC_AHB_CLK] = &camcc_soc_ahb_clk.clkr, |
| 1833 | [CAMCC_SYS_TMR_CLK] = &camcc_sys_tmr_clk.clkr, |
| 1834 | }; |
| 1835 | |
| 1836 | static struct gdsc *camcc_sm6350_gdscs[] = { |
| 1837 | [BPS_GDSC] = &bps_gdsc, |
| 1838 | [IPE_0_GDSC] = &ipe_0_gdsc, |
| 1839 | [IFE_0_GDSC] = &ife_0_gdsc, |
| 1840 | [IFE_1_GDSC] = &ife_1_gdsc, |
| 1841 | [IFE_2_GDSC] = &ife_2_gdsc, |
| 1842 | [TITAN_TOP_GDSC] = &titan_top_gdsc, |
| 1843 | }; |
| 1844 | |
| 1845 | static const struct regmap_config camcc_sm6350_regmap_config = { |
| 1846 | .reg_bits = 32, |
| 1847 | .reg_stride = 4, |
| 1848 | .val_bits = 32, |
| 1849 | .max_register = 0x16000, |
| 1850 | .fast_io = true, |
| 1851 | }; |
| 1852 | |
| 1853 | static const struct qcom_cc_desc camcc_sm6350_desc = { |
| 1854 | .config = &camcc_sm6350_regmap_config, |
| 1855 | .clk_hws = camcc_sm6350_hws, |
| 1856 | .num_clk_hws = ARRAY_SIZE(camcc_sm6350_hws), |
| 1857 | .clks = camcc_sm6350_clocks, |
| 1858 | .num_clks = ARRAY_SIZE(camcc_sm6350_clocks), |
| 1859 | .gdscs = camcc_sm6350_gdscs, |
| 1860 | .num_gdscs = ARRAY_SIZE(camcc_sm6350_gdscs), |
| 1861 | }; |
| 1862 | |
| 1863 | static const struct of_device_id camcc_sm6350_match_table[] = { |
| 1864 | { .compatible = "qcom,sm6350-camcc" }, |
| 1865 | { } |
| 1866 | }; |
| 1867 | MODULE_DEVICE_TABLE(of, camcc_sm6350_match_table); |
| 1868 | |
| 1869 | static int camcc_sm6350_probe(struct platform_device *pdev) |
| 1870 | { |
| 1871 | struct regmap *regmap; |
| 1872 | |
| 1873 | regmap = qcom_cc_map(pdev, &camcc_sm6350_desc); |
| 1874 | if (IS_ERR(regmap)) |
| 1875 | return PTR_ERR(regmap); |
| 1876 | |
| 1877 | clk_fabia_pll_configure(&camcc_pll0, regmap, &camcc_pll0_config); |
| 1878 | clk_fabia_pll_configure(&camcc_pll1, regmap, &camcc_pll1_config); |
| 1879 | clk_agera_pll_configure(&camcc_pll2, regmap, &camcc_pll2_config); |
| 1880 | clk_fabia_pll_configure(&camcc_pll3, regmap, &camcc_pll3_config); |
| 1881 | |
Luo Jie | 9f93a0a | 2024-06-05 20:45:40 +0800 | [diff] [blame] | 1882 | return qcom_cc_really_probe(&pdev->dev, &camcc_sm6350_desc, regmap); |
Konrad Dybcio | 80f5451 | 2022-12-13 16:26:16 +0100 | [diff] [blame] | 1883 | } |
| 1884 | |
| 1885 | static struct platform_driver camcc_sm6350_driver = { |
| 1886 | .probe = camcc_sm6350_probe, |
| 1887 | .driver = { |
| 1888 | .name = "sm6350-camcc", |
| 1889 | .of_match_table = camcc_sm6350_match_table, |
| 1890 | }, |
| 1891 | }; |
| 1892 | |
Dmitry Baryshkov | 8f4bfd9 | 2024-02-06 17:25:12 +0200 | [diff] [blame] | 1893 | module_platform_driver(camcc_sm6350_driver); |
Konrad Dybcio | 80f5451 | 2022-12-13 16:26:16 +0100 | [diff] [blame] | 1894 | |
| 1895 | MODULE_DESCRIPTION("QTI CAMCC SM6350 Driver"); |
| 1896 | MODULE_LICENSE("GPL"); |