Thomas Gleixner | 7160d9c | 2022-05-10 19:24:41 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Marvell Armada 370/XP SoC timer handling. |
| 4 | * |
| 5 | * Copyright (C) 2012 Marvell |
| 6 | * |
| 7 | * Lior Amsalem <alior@marvell.com> |
| 8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| 9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 10 | * |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 11 | * Timer 0 is used as free-running clocksource, while timer 1 is |
| 12 | * used as clock_event_device. |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 13 | * |
| 14 | * --- |
| 15 | * Clocksource driver for Armada 370 and Armada XP SoC. |
| 16 | * This driver implements one compatible string for each SoC, given |
| 17 | * each has its own characteristics: |
| 18 | * |
| 19 | * * Armada 370 has no 25 MHz fixed timer. |
| 20 | * |
| 21 | * * Armada XP cannot work properly without such 25 MHz fixed timer as |
| 22 | * doing otherwise leads to using a clocksource whose frequency varies |
| 23 | * when doing cpufreq frequency changes. |
| 24 | * |
| 25 | * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 26 | */ |
| 27 | |
| 28 | #include <linux/init.h> |
| 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/kernel.h> |
Gregory CLEMENT | 307c2bf | 2012-11-17 15:22:25 +0100 | [diff] [blame] | 31 | #include <linux/clk.h> |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 32 | #include <linux/cpu.h> |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 33 | #include <linux/timer.h> |
| 34 | #include <linux/clockchips.h> |
| 35 | #include <linux/interrupt.h> |
| 36 | #include <linux/of.h> |
| 37 | #include <linux/of_irq.h> |
| 38 | #include <linux/of_address.h> |
| 39 | #include <linux/irq.h> |
| 40 | #include <linux/module.h> |
Stephen Boyd | 38ff87f | 2013-06-01 23:39:40 -0700 | [diff] [blame] | 41 | #include <linux/sched_clock.h> |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 42 | #include <linux/percpu.h> |
Thomas Petazzoni | f9a49ab | 2014-11-21 17:00:01 +0100 | [diff] [blame] | 43 | #include <linux/syscore_ops.h> |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 44 | |
Russell King | cb0f253 | 2015-10-19 16:19:20 +0100 | [diff] [blame] | 45 | #include <asm/delay.h> |
| 46 | |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 47 | /* |
| 48 | * Timer block registers. |
| 49 | */ |
| 50 | #define TIMER_CTRL_OFF 0x0000 |
Ezequiel Garcia | ad48bd6 | 2013-08-13 11:43:10 -0300 | [diff] [blame] | 51 | #define TIMER0_EN BIT(0) |
| 52 | #define TIMER0_RELOAD_EN BIT(1) |
| 53 | #define TIMER0_25MHZ BIT(11) |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 54 | #define TIMER0_DIV(div) ((div) << 19) |
Ezequiel Garcia | ad48bd6 | 2013-08-13 11:43:10 -0300 | [diff] [blame] | 55 | #define TIMER1_EN BIT(2) |
| 56 | #define TIMER1_RELOAD_EN BIT(3) |
| 57 | #define TIMER1_25MHZ BIT(12) |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 58 | #define TIMER1_DIV(div) ((div) << 22) |
| 59 | #define TIMER_EVENTS_STATUS 0x0004 |
| 60 | #define TIMER0_CLR_MASK (~0x1) |
| 61 | #define TIMER1_CLR_MASK (~0x100) |
| 62 | #define TIMER0_RELOAD_OFF 0x0010 |
| 63 | #define TIMER0_VAL_OFF 0x0014 |
| 64 | #define TIMER1_RELOAD_OFF 0x0018 |
| 65 | #define TIMER1_VAL_OFF 0x001c |
| 66 | |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 67 | #define LCL_TIMER_EVENTS_STATUS 0x0028 |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 68 | /* Global timers are connected to the coherency fabric clock, and the |
| 69 | below divider reduces their incrementing frequency. */ |
| 70 | #define TIMER_DIVIDER_SHIFT 5 |
| 71 | #define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT) |
| 72 | |
| 73 | /* |
| 74 | * SoC-specific data. |
| 75 | */ |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 76 | static void __iomem *timer_base, *local_base; |
| 77 | static unsigned int timer_clk; |
| 78 | static bool timer25Mhz = true; |
Ezequiel Garcia | 08cb8e46 | 2013-12-02 11:39:56 +0100 | [diff] [blame] | 79 | static u32 enable_mask; |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 80 | |
| 81 | /* |
| 82 | * Number of timer ticks per jiffy. |
| 83 | */ |
| 84 | static u32 ticks_per_jiffy; |
| 85 | |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 86 | static struct clock_event_device __percpu *armada_370_xp_evt; |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 87 | |
Ezequiel Garcia | 3579698 | 2013-08-13 11:43:11 -0300 | [diff] [blame] | 88 | static void local_timer_ctrl_clrset(u32 clr, u32 set) |
| 89 | { |
| 90 | writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, |
| 91 | local_base + TIMER_CTRL_OFF); |
| 92 | } |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 93 | |
Stephen Boyd | d9dbcbe | 2013-07-18 16:21:27 -0700 | [diff] [blame] | 94 | static u64 notrace armada_370_xp_read_sched_clock(void) |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 95 | { |
| 96 | return ~readl(timer_base + TIMER0_VAL_OFF); |
| 97 | } |
| 98 | |
| 99 | /* |
| 100 | * Clockevent handling. |
| 101 | */ |
| 102 | static int |
| 103 | armada_370_xp_clkevt_next_event(unsigned long delta, |
| 104 | struct clock_event_device *dev) |
| 105 | { |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 106 | /* |
| 107 | * Clear clockevent timer interrupt. |
| 108 | */ |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 109 | writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 110 | |
| 111 | /* |
| 112 | * Setup new clockevent timer value. |
| 113 | */ |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 114 | writel(delta, local_base + TIMER0_VAL_OFF); |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * Enable the timer. |
| 118 | */ |
Ezequiel Garcia | 08cb8e46 | 2013-12-02 11:39:56 +0100 | [diff] [blame] | 119 | local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask); |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 120 | return 0; |
| 121 | } |
| 122 | |
Viresh Kumar | d96f441 | 2015-06-18 16:24:40 +0530 | [diff] [blame] | 123 | static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt) |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 124 | { |
Viresh Kumar | d96f441 | 2015-06-18 16:24:40 +0530 | [diff] [blame] | 125 | /* |
| 126 | * Disable timer. |
| 127 | */ |
| 128 | local_timer_ctrl_clrset(TIMER0_EN, 0); |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 129 | |
Viresh Kumar | d96f441 | 2015-06-18 16:24:40 +0530 | [diff] [blame] | 130 | /* |
| 131 | * ACK pending timer interrupt. |
| 132 | */ |
| 133 | writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); |
| 134 | return 0; |
| 135 | } |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 136 | |
Viresh Kumar | d96f441 | 2015-06-18 16:24:40 +0530 | [diff] [blame] | 137 | static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt) |
| 138 | { |
| 139 | /* |
| 140 | * Setup timer to fire at 1/HZ intervals. |
| 141 | */ |
| 142 | writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF); |
| 143 | writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF); |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 144 | |
Viresh Kumar | d96f441 | 2015-06-18 16:24:40 +0530 | [diff] [blame] | 145 | /* |
| 146 | * Enable timer. |
| 147 | */ |
| 148 | local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask); |
| 149 | return 0; |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 150 | } |
| 151 | |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 152 | static int armada_370_xp_clkevt_irq; |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 153 | |
| 154 | static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id) |
| 155 | { |
| 156 | /* |
| 157 | * ACK timer interrupt and call event handler. |
| 158 | */ |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 159 | struct clock_event_device *evt = dev_id; |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 160 | |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 161 | writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); |
| 162 | evt->event_handler(evt); |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 163 | |
| 164 | return IRQ_HANDLED; |
| 165 | } |
| 166 | |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 167 | /* |
| 168 | * Setup the local clock events for a CPU. |
| 169 | */ |
Richard Cochran | 2c48fef | 2016-07-13 17:17:06 +0000 | [diff] [blame] | 170 | static int armada_370_xp_timer_starting_cpu(unsigned int cpu) |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 171 | { |
Richard Cochran | 2c48fef | 2016-07-13 17:17:06 +0000 | [diff] [blame] | 172 | struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu); |
Ezequiel Garcia | 3579698 | 2013-08-13 11:43:11 -0300 | [diff] [blame] | 173 | u32 clr = 0, set = 0; |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 174 | |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 175 | if (timer25Mhz) |
Ezequiel Garcia | 3579698 | 2013-08-13 11:43:11 -0300 | [diff] [blame] | 176 | set = TIMER0_25MHZ; |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 177 | else |
Ezequiel Garcia | 3579698 | 2013-08-13 11:43:11 -0300 | [diff] [blame] | 178 | clr = TIMER0_25MHZ; |
| 179 | local_timer_ctrl_clrset(clr, set); |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 180 | |
Julia Lawall | 1b80043 | 2020-09-27 21:12:26 +0200 | [diff] [blame] | 181 | evt->name = "armada_370_xp_per_cpu_tick"; |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 182 | evt->features = CLOCK_EVT_FEAT_ONESHOT | |
| 183 | CLOCK_EVT_FEAT_PERIODIC; |
Julia Lawall | 1b80043 | 2020-09-27 21:12:26 +0200 | [diff] [blame] | 184 | evt->shift = 32; |
| 185 | evt->rating = 300; |
| 186 | evt->set_next_event = armada_370_xp_clkevt_next_event; |
Viresh Kumar | d96f441 | 2015-06-18 16:24:40 +0530 | [diff] [blame] | 187 | evt->set_state_shutdown = armada_370_xp_clkevt_shutdown; |
| 188 | evt->set_state_periodic = armada_370_xp_clkevt_set_periodic; |
| 189 | evt->set_state_oneshot = armada_370_xp_clkevt_shutdown; |
| 190 | evt->tick_resume = armada_370_xp_clkevt_shutdown; |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 191 | evt->irq = armada_370_xp_clkevt_irq; |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 192 | evt->cpumask = cpumask_of(cpu); |
| 193 | |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 194 | clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe); |
| 195 | enable_percpu_irq(evt->irq, 0); |
| 196 | |
| 197 | return 0; |
| 198 | } |
| 199 | |
Richard Cochran | 2c48fef | 2016-07-13 17:17:06 +0000 | [diff] [blame] | 200 | static int armada_370_xp_timer_dying_cpu(unsigned int cpu) |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 201 | { |
Richard Cochran | 2c48fef | 2016-07-13 17:17:06 +0000 | [diff] [blame] | 202 | struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu); |
| 203 | |
Viresh Kumar | d96f441 | 2015-06-18 16:24:40 +0530 | [diff] [blame] | 204 | evt->set_state_shutdown(evt); |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 205 | disable_percpu_irq(evt->irq); |
Richard Cochran | 2c48fef | 2016-07-13 17:17:06 +0000 | [diff] [blame] | 206 | return 0; |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 207 | } |
| 208 | |
Thomas Petazzoni | f9a49ab | 2014-11-21 17:00:01 +0100 | [diff] [blame] | 209 | static u32 timer0_ctrl_reg, timer0_local_ctrl_reg; |
| 210 | |
| 211 | static int armada_370_xp_timer_suspend(void) |
| 212 | { |
| 213 | timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF); |
| 214 | timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF); |
| 215 | return 0; |
| 216 | } |
| 217 | |
| 218 | static void armada_370_xp_timer_resume(void) |
| 219 | { |
| 220 | writel(0xffffffff, timer_base + TIMER0_VAL_OFF); |
| 221 | writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); |
| 222 | writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF); |
| 223 | writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF); |
| 224 | } |
| 225 | |
Ben Dooks | 2c436e4 | 2016-06-16 15:47:49 +0200 | [diff] [blame] | 226 | static struct syscore_ops armada_370_xp_timer_syscore_ops = { |
Thomas Petazzoni | f9a49ab | 2014-11-21 17:00:01 +0100 | [diff] [blame] | 227 | .suspend = armada_370_xp_timer_suspend, |
| 228 | .resume = armada_370_xp_timer_resume, |
| 229 | }; |
| 230 | |
Russell King | cb0f253 | 2015-10-19 16:19:20 +0100 | [diff] [blame] | 231 | static unsigned long armada_370_delay_timer_read(void) |
| 232 | { |
| 233 | return ~readl(timer_base + TIMER0_VAL_OFF); |
| 234 | } |
| 235 | |
| 236 | static struct delay_timer armada_370_delay_timer = { |
| 237 | .read_current_timer = armada_370_delay_timer_read, |
| 238 | }; |
| 239 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 240 | static int __init armada_370_xp_timer_common_init(struct device_node *np) |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 241 | { |
Ezequiel Garcia | 3579698 | 2013-08-13 11:43:11 -0300 | [diff] [blame] | 242 | u32 clr = 0, set = 0; |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 243 | int res; |
| 244 | |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 245 | timer_base = of_iomap(np, 0); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 246 | if (!timer_base) { |
Rafał Miłecki | ac9ce6d | 2017-03-09 10:47:10 +0100 | [diff] [blame] | 247 | pr_err("Failed to iomap\n"); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 248 | return -ENXIO; |
| 249 | } |
| 250 | |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 251 | local_base = of_iomap(np, 1); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 252 | if (!local_base) { |
Rafał Miłecki | ac9ce6d | 2017-03-09 10:47:10 +0100 | [diff] [blame] | 253 | pr_err("Failed to iomap\n"); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 254 | return -ENXIO; |
| 255 | } |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 256 | |
Ezequiel Garcia | 08cb8e46 | 2013-12-02 11:39:56 +0100 | [diff] [blame] | 257 | if (timer25Mhz) { |
Linus Torvalds | a4ae54f | 2013-09-16 16:10:26 -0400 | [diff] [blame] | 258 | set = TIMER0_25MHZ; |
Ezequiel Garcia | 08cb8e46 | 2013-12-02 11:39:56 +0100 | [diff] [blame] | 259 | enable_mask = TIMER0_EN; |
| 260 | } else { |
Ezequiel Garcia | 3579698 | 2013-08-13 11:43:11 -0300 | [diff] [blame] | 261 | clr = TIMER0_25MHZ; |
Ezequiel Garcia | 08cb8e46 | 2013-12-02 11:39:56 +0100 | [diff] [blame] | 262 | enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT); |
| 263 | } |
Ezequiel Garcia | c8af34b | 2014-02-19 17:05:26 -0300 | [diff] [blame] | 264 | atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); |
Ezequiel Garcia | 3579698 | 2013-08-13 11:43:11 -0300 | [diff] [blame] | 265 | local_timer_ctrl_clrset(clr, set); |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 266 | |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 267 | /* |
| 268 | * We use timer 0 as clocksource, and private(local) timer 0 |
| 269 | * for clockevents |
| 270 | */ |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 271 | armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4); |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 272 | |
| 273 | ticks_per_jiffy = (timer_clk + HZ / 2) / HZ; |
| 274 | |
| 275 | /* |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 276 | * Setup free-running clocksource timer (interrupts |
| 277 | * disabled). |
| 278 | */ |
| 279 | writel(0xffffffff, timer_base + TIMER0_VAL_OFF); |
| 280 | writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); |
| 281 | |
Ezequiel Garcia | c8af34b | 2014-02-19 17:05:26 -0300 | [diff] [blame] | 282 | atomic_io_modify(timer_base + TIMER_CTRL_OFF, |
| 283 | TIMER0_RELOAD_EN | enable_mask, |
| 284 | TIMER0_RELOAD_EN | enable_mask); |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 285 | |
Russell King | cb0f253 | 2015-10-19 16:19:20 +0100 | [diff] [blame] | 286 | armada_370_delay_timer.freq = timer_clk; |
| 287 | register_current_timer_delay(&armada_370_delay_timer); |
| 288 | |
Ezequiel Garcia | c813eff | 2013-11-26 18:20:14 -0300 | [diff] [blame] | 289 | /* |
| 290 | * Set scale and timer for sched_clock. |
| 291 | */ |
| 292 | sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk); |
| 293 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 294 | res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, |
| 295 | "armada_370_xp_clocksource", |
| 296 | timer_clk, 300, 32, clocksource_mmio_readl_down); |
| 297 | if (res) { |
Rafał Miłecki | ac9ce6d | 2017-03-09 10:47:10 +0100 | [diff] [blame] | 298 | pr_err("Failed to initialize clocksource mmio\n"); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 299 | return res; |
| 300 | } |
Gregory CLEMENT | 6fe9cbd | 2012-06-13 18:58:09 +0200 | [diff] [blame] | 301 | |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 302 | armada_370_xp_evt = alloc_percpu(struct clock_event_device); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 303 | if (!armada_370_xp_evt) |
| 304 | return -ENOMEM; |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 305 | |
| 306 | /* |
| 307 | * Setup clockevent timer (interrupt-driven). |
| 308 | */ |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 309 | res = request_percpu_irq(armada_370_xp_clkevt_irq, |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 310 | armada_370_xp_timer_interrupt, |
Stephen Boyd | 5ddb6d2 | 2013-02-15 17:02:16 -0800 | [diff] [blame] | 311 | "armada_370_xp_per_cpu_tick", |
| 312 | armada_370_xp_evt); |
| 313 | /* Immediately configure the timer on the boot CPU */ |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 314 | if (res) { |
Rafał Miłecki | ac9ce6d | 2017-03-09 10:47:10 +0100 | [diff] [blame] | 315 | pr_err("Failed to request percpu irq\n"); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 316 | return res; |
| 317 | } |
| 318 | |
Richard Cochran | 2c48fef | 2016-07-13 17:17:06 +0000 | [diff] [blame] | 319 | res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING, |
Thomas Gleixner | 73c1b41 | 2016-12-21 20:19:54 +0100 | [diff] [blame] | 320 | "clockevents/armada:starting", |
Richard Cochran | 2c48fef | 2016-07-13 17:17:06 +0000 | [diff] [blame] | 321 | armada_370_xp_timer_starting_cpu, |
| 322 | armada_370_xp_timer_dying_cpu); |
Anna-Maria Gleixner | 1d661bf | 2016-07-12 16:40:09 +0200 | [diff] [blame] | 323 | if (res) { |
Rafał Miłecki | ac9ce6d | 2017-03-09 10:47:10 +0100 | [diff] [blame] | 324 | pr_err("Failed to setup hotplug state and timer\n"); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 325 | return res; |
| 326 | } |
Thomas Petazzoni | f9a49ab | 2014-11-21 17:00:01 +0100 | [diff] [blame] | 327 | |
| 328 | register_syscore_ops(&armada_370_xp_timer_syscore_ops); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 329 | |
| 330 | return 0; |
Gregory CLEMENT | ddd3f69 | 2013-01-25 18:32:42 +0100 | [diff] [blame] | 331 | } |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 332 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 333 | static int __init armada_xp_timer_init(struct device_node *np) |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 334 | { |
Ezequiel Garcia | 5e9fe6c | 2013-08-20 12:45:53 -0300 | [diff] [blame] | 335 | struct clk *clk = of_clk_get_by_name(np, "fixed"); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 336 | int ret; |
Ezequiel Garcia | 5e9fe6c | 2013-08-20 12:45:53 -0300 | [diff] [blame] | 337 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 338 | if (IS_ERR(clk)) { |
Rafał Miłecki | ac9ce6d | 2017-03-09 10:47:10 +0100 | [diff] [blame] | 339 | pr_err("Failed to get clock\n"); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 340 | return PTR_ERR(clk); |
| 341 | } |
| 342 | |
| 343 | ret = clk_prepare_enable(clk); |
| 344 | if (ret) |
| 345 | return ret; |
| 346 | |
Ezequiel Garcia | 5e9fe6c | 2013-08-20 12:45:53 -0300 | [diff] [blame] | 347 | timer_clk = clk_get_rate(clk); |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 348 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 349 | return armada_370_xp_timer_common_init(np); |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 350 | } |
Daniel Lezcano | 1727339 | 2017-05-26 16:56:11 +0200 | [diff] [blame] | 351 | TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer", |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 352 | armada_xp_timer_init); |
| 353 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 354 | static int __init armada_375_timer_init(struct device_node *np) |
Ezequiel Garcia | 4a22d9c | 2014-11-04 10:21:33 -0300 | [diff] [blame] | 355 | { |
| 356 | struct clk *clk; |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 357 | int ret; |
Ezequiel Garcia | 4a22d9c | 2014-11-04 10:21:33 -0300 | [diff] [blame] | 358 | |
| 359 | clk = of_clk_get_by_name(np, "fixed"); |
| 360 | if (!IS_ERR(clk)) { |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 361 | ret = clk_prepare_enable(clk); |
| 362 | if (ret) |
| 363 | return ret; |
Ezequiel Garcia | 4a22d9c | 2014-11-04 10:21:33 -0300 | [diff] [blame] | 364 | timer_clk = clk_get_rate(clk); |
| 365 | } else { |
| 366 | |
| 367 | /* |
| 368 | * This fallback is required in order to retain proper |
| 369 | * devicetree backwards compatibility. |
| 370 | */ |
| 371 | clk = of_clk_get(np, 0); |
| 372 | |
| 373 | /* Must have at least a clock */ |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 374 | if (IS_ERR(clk)) { |
Rafał Miłecki | ac9ce6d | 2017-03-09 10:47:10 +0100 | [diff] [blame] | 375 | pr_err("Failed to get clock\n"); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 376 | return PTR_ERR(clk); |
| 377 | } |
| 378 | |
| 379 | ret = clk_prepare_enable(clk); |
| 380 | if (ret) |
| 381 | return ret; |
| 382 | |
Ezequiel Garcia | 4a22d9c | 2014-11-04 10:21:33 -0300 | [diff] [blame] | 383 | timer_clk = clk_get_rate(clk) / TIMER_DIVIDER; |
| 384 | timer25Mhz = false; |
| 385 | } |
| 386 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 387 | return armada_370_xp_timer_common_init(np); |
Ezequiel Garcia | 4a22d9c | 2014-11-04 10:21:33 -0300 | [diff] [blame] | 388 | } |
Daniel Lezcano | 1727339 | 2017-05-26 16:56:11 +0200 | [diff] [blame] | 389 | TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer", |
Ezequiel Garcia | 4a22d9c | 2014-11-04 10:21:33 -0300 | [diff] [blame] | 390 | armada_375_timer_init); |
| 391 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 392 | static int __init armada_370_timer_init(struct device_node *np) |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 393 | { |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 394 | struct clk *clk; |
| 395 | int ret; |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 396 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 397 | clk = of_clk_get(np, 0); |
| 398 | if (IS_ERR(clk)) { |
Rafał Miłecki | ac9ce6d | 2017-03-09 10:47:10 +0100 | [diff] [blame] | 399 | pr_err("Failed to get clock\n"); |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 400 | return PTR_ERR(clk); |
| 401 | } |
| 402 | |
| 403 | ret = clk_prepare_enable(clk); |
| 404 | if (ret) |
| 405 | return ret; |
| 406 | |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 407 | timer_clk = clk_get_rate(clk) / TIMER_DIVIDER; |
| 408 | timer25Mhz = false; |
| 409 | |
Daniel Lezcano | 12549e2 | 2016-06-06 18:00:01 +0200 | [diff] [blame] | 410 | return armada_370_xp_timer_common_init(np); |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 411 | } |
Daniel Lezcano | 1727339 | 2017-05-26 16:56:11 +0200 | [diff] [blame] | 412 | TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer", |
Ezequiel Garcia | 7cd6392 | 2013-08-13 11:43:13 -0300 | [diff] [blame] | 413 | armada_370_timer_init); |