blob: 6ec565d6939ad4369594396f9f78eab26c3d475e [file] [log] [blame]
Thomas Gleixner7160d9c2022-05-10 19:24:41 +02001// SPDX-License-Identifier: GPL-2.0
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +02002/*
3 * Marvell Armada 370/XP SoC timer handling.
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 *
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020011 * Timer 0 is used as free-running clocksource, while timer 1 is
12 * used as clock_event_device.
Ezequiel Garcia7cd63922013-08-13 11:43:13 -030013 *
14 * ---
15 * Clocksource driver for Armada 370 and Armada XP SoC.
16 * This driver implements one compatible string for each SoC, given
17 * each has its own characteristics:
18 *
19 * * Armada 370 has no 25 MHz fixed timer.
20 *
21 * * Armada XP cannot work properly without such 25 MHz fixed timer as
22 * doing otherwise leads to using a clocksource whose frequency varies
23 * when doing cpufreq frequency changes.
24 *
25 * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020026 */
27
28#include <linux/init.h>
29#include <linux/platform_device.h>
30#include <linux/kernel.h>
Gregory CLEMENT307c2bf2012-11-17 15:22:25 +010031#include <linux/clk.h>
Stephen Boyd5ddb6d22013-02-15 17:02:16 -080032#include <linux/cpu.h>
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020033#include <linux/timer.h>
34#include <linux/clockchips.h>
35#include <linux/interrupt.h>
36#include <linux/of.h>
37#include <linux/of_irq.h>
38#include <linux/of_address.h>
39#include <linux/irq.h>
40#include <linux/module.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070041#include <linux/sched_clock.h>
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010042#include <linux/percpu.h>
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +010043#include <linux/syscore_ops.h>
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020044
Russell Kingcb0f2532015-10-19 16:19:20 +010045#include <asm/delay.h>
46
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020047/*
48 * Timer block registers.
49 */
50#define TIMER_CTRL_OFF 0x0000
Ezequiel Garciaad48bd62013-08-13 11:43:10 -030051#define TIMER0_EN BIT(0)
52#define TIMER0_RELOAD_EN BIT(1)
53#define TIMER0_25MHZ BIT(11)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020054#define TIMER0_DIV(div) ((div) << 19)
Ezequiel Garciaad48bd62013-08-13 11:43:10 -030055#define TIMER1_EN BIT(2)
56#define TIMER1_RELOAD_EN BIT(3)
57#define TIMER1_25MHZ BIT(12)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020058#define TIMER1_DIV(div) ((div) << 22)
59#define TIMER_EVENTS_STATUS 0x0004
60#define TIMER0_CLR_MASK (~0x1)
61#define TIMER1_CLR_MASK (~0x100)
62#define TIMER0_RELOAD_OFF 0x0010
63#define TIMER0_VAL_OFF 0x0014
64#define TIMER1_RELOAD_OFF 0x0018
65#define TIMER1_VAL_OFF 0x001c
66
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010067#define LCL_TIMER_EVENTS_STATUS 0x0028
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020068/* Global timers are connected to the coherency fabric clock, and the
69 below divider reduces their incrementing frequency. */
70#define TIMER_DIVIDER_SHIFT 5
71#define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT)
72
73/*
74 * SoC-specific data.
75 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010076static void __iomem *timer_base, *local_base;
77static unsigned int timer_clk;
78static bool timer25Mhz = true;
Ezequiel Garcia08cb8e462013-12-02 11:39:56 +010079static u32 enable_mask;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020080
81/*
82 * Number of timer ticks per jiffy.
83 */
84static u32 ticks_per_jiffy;
85
Stephen Boyd5ddb6d22013-02-15 17:02:16 -080086static struct clock_event_device __percpu *armada_370_xp_evt;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +010087
Ezequiel Garcia35796982013-08-13 11:43:11 -030088static void local_timer_ctrl_clrset(u32 clr, u32 set)
89{
90 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
91 local_base + TIMER_CTRL_OFF);
92}
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020093
Stephen Boydd9dbcbe2013-07-18 16:21:27 -070094static u64 notrace armada_370_xp_read_sched_clock(void)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +020095{
96 return ~readl(timer_base + TIMER0_VAL_OFF);
97}
98
99/*
100 * Clockevent handling.
101 */
102static int
103armada_370_xp_clkevt_next_event(unsigned long delta,
104 struct clock_event_device *dev)
105{
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200106 /*
107 * Clear clockevent timer interrupt.
108 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100109 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200110
111 /*
112 * Setup new clockevent timer value.
113 */
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100114 writel(delta, local_base + TIMER0_VAL_OFF);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200115
116 /*
117 * Enable the timer.
118 */
Ezequiel Garcia08cb8e462013-12-02 11:39:56 +0100119 local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200120 return 0;
121}
122
Viresh Kumard96f4412015-06-18 16:24:40 +0530123static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200124{
Viresh Kumard96f4412015-06-18 16:24:40 +0530125 /*
126 * Disable timer.
127 */
128 local_timer_ctrl_clrset(TIMER0_EN, 0);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100129
Viresh Kumard96f4412015-06-18 16:24:40 +0530130 /*
131 * ACK pending timer interrupt.
132 */
133 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
134 return 0;
135}
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200136
Viresh Kumard96f4412015-06-18 16:24:40 +0530137static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
138{
139 /*
140 * Setup timer to fire at 1/HZ intervals.
141 */
142 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
143 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200144
Viresh Kumard96f4412015-06-18 16:24:40 +0530145 /*
146 * Enable timer.
147 */
148 local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
149 return 0;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200150}
151
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800152static int armada_370_xp_clkevt_irq;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200153
154static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
155{
156 /*
157 * ACK timer interrupt and call event handler.
158 */
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800159 struct clock_event_device *evt = dev_id;
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200160
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100161 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
162 evt->event_handler(evt);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200163
164 return IRQ_HANDLED;
165}
166
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100167/*
168 * Setup the local clock events for a CPU.
169 */
Richard Cochran2c48fef2016-07-13 17:17:06 +0000170static int armada_370_xp_timer_starting_cpu(unsigned int cpu)
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100171{
Richard Cochran2c48fef2016-07-13 17:17:06 +0000172 struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
Ezequiel Garcia35796982013-08-13 11:43:11 -0300173 u32 clr = 0, set = 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100174
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100175 if (timer25Mhz)
Ezequiel Garcia35796982013-08-13 11:43:11 -0300176 set = TIMER0_25MHZ;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100177 else
Ezequiel Garcia35796982013-08-13 11:43:11 -0300178 clr = TIMER0_25MHZ;
179 local_timer_ctrl_clrset(clr, set);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100180
Julia Lawall1b800432020-09-27 21:12:26 +0200181 evt->name = "armada_370_xp_per_cpu_tick";
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800182 evt->features = CLOCK_EVT_FEAT_ONESHOT |
183 CLOCK_EVT_FEAT_PERIODIC;
Julia Lawall1b800432020-09-27 21:12:26 +0200184 evt->shift = 32;
185 evt->rating = 300;
186 evt->set_next_event = armada_370_xp_clkevt_next_event;
Viresh Kumard96f4412015-06-18 16:24:40 +0530187 evt->set_state_shutdown = armada_370_xp_clkevt_shutdown;
188 evt->set_state_periodic = armada_370_xp_clkevt_set_periodic;
189 evt->set_state_oneshot = armada_370_xp_clkevt_shutdown;
190 evt->tick_resume = armada_370_xp_clkevt_shutdown;
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800191 evt->irq = armada_370_xp_clkevt_irq;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100192 evt->cpumask = cpumask_of(cpu);
193
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100194 clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
195 enable_percpu_irq(evt->irq, 0);
196
197 return 0;
198}
199
Richard Cochran2c48fef2016-07-13 17:17:06 +0000200static int armada_370_xp_timer_dying_cpu(unsigned int cpu)
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100201{
Richard Cochran2c48fef2016-07-13 17:17:06 +0000202 struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
203
Viresh Kumard96f4412015-06-18 16:24:40 +0530204 evt->set_state_shutdown(evt);
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100205 disable_percpu_irq(evt->irq);
Richard Cochran2c48fef2016-07-13 17:17:06 +0000206 return 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100207}
208
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +0100209static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
210
211static int armada_370_xp_timer_suspend(void)
212{
213 timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
214 timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
215 return 0;
216}
217
218static void armada_370_xp_timer_resume(void)
219{
220 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
221 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
222 writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
223 writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
224}
225
Ben Dooks2c436e42016-06-16 15:47:49 +0200226static struct syscore_ops armada_370_xp_timer_syscore_ops = {
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +0100227 .suspend = armada_370_xp_timer_suspend,
228 .resume = armada_370_xp_timer_resume,
229};
230
Russell Kingcb0f2532015-10-19 16:19:20 +0100231static unsigned long armada_370_delay_timer_read(void)
232{
233 return ~readl(timer_base + TIMER0_VAL_OFF);
234}
235
236static struct delay_timer armada_370_delay_timer = {
237 .read_current_timer = armada_370_delay_timer_read,
238};
239
Daniel Lezcano12549e22016-06-06 18:00:01 +0200240static int __init armada_370_xp_timer_common_init(struct device_node *np)
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200241{
Ezequiel Garcia35796982013-08-13 11:43:11 -0300242 u32 clr = 0, set = 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100243 int res;
244
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200245 timer_base = of_iomap(np, 0);
Daniel Lezcano12549e22016-06-06 18:00:01 +0200246 if (!timer_base) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100247 pr_err("Failed to iomap\n");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200248 return -ENXIO;
249 }
250
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100251 local_base = of_iomap(np, 1);
Daniel Lezcano12549e22016-06-06 18:00:01 +0200252 if (!local_base) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100253 pr_err("Failed to iomap\n");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200254 return -ENXIO;
255 }
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200256
Ezequiel Garcia08cb8e462013-12-02 11:39:56 +0100257 if (timer25Mhz) {
Linus Torvaldsa4ae54f2013-09-16 16:10:26 -0400258 set = TIMER0_25MHZ;
Ezequiel Garcia08cb8e462013-12-02 11:39:56 +0100259 enable_mask = TIMER0_EN;
260 } else {
Ezequiel Garcia35796982013-08-13 11:43:11 -0300261 clr = TIMER0_25MHZ;
Ezequiel Garcia08cb8e462013-12-02 11:39:56 +0100262 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
263 }
Ezequiel Garciac8af34b2014-02-19 17:05:26 -0300264 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
Ezequiel Garcia35796982013-08-13 11:43:11 -0300265 local_timer_ctrl_clrset(clr, set);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200266
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100267 /*
268 * We use timer 0 as clocksource, and private(local) timer 0
269 * for clockevents
270 */
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800271 armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200272
273 ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
274
275 /*
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200276 * Setup free-running clocksource timer (interrupts
277 * disabled).
278 */
279 writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
280 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
281
Ezequiel Garciac8af34b2014-02-19 17:05:26 -0300282 atomic_io_modify(timer_base + TIMER_CTRL_OFF,
283 TIMER0_RELOAD_EN | enable_mask,
284 TIMER0_RELOAD_EN | enable_mask);
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200285
Russell Kingcb0f2532015-10-19 16:19:20 +0100286 armada_370_delay_timer.freq = timer_clk;
287 register_current_timer_delay(&armada_370_delay_timer);
288
Ezequiel Garciac813eff2013-11-26 18:20:14 -0300289 /*
290 * Set scale and timer for sched_clock.
291 */
292 sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
293
Daniel Lezcano12549e22016-06-06 18:00:01 +0200294 res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
295 "armada_370_xp_clocksource",
296 timer_clk, 300, 32, clocksource_mmio_readl_down);
297 if (res) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100298 pr_err("Failed to initialize clocksource mmio\n");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200299 return res;
300 }
Gregory CLEMENT6fe9cbd2012-06-13 18:58:09 +0200301
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800302 armada_370_xp_evt = alloc_percpu(struct clock_event_device);
Daniel Lezcano12549e22016-06-06 18:00:01 +0200303 if (!armada_370_xp_evt)
304 return -ENOMEM;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100305
306 /*
307 * Setup clockevent timer (interrupt-driven).
308 */
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800309 res = request_percpu_irq(armada_370_xp_clkevt_irq,
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100310 armada_370_xp_timer_interrupt,
Stephen Boyd5ddb6d22013-02-15 17:02:16 -0800311 "armada_370_xp_per_cpu_tick",
312 armada_370_xp_evt);
313 /* Immediately configure the timer on the boot CPU */
Daniel Lezcano12549e22016-06-06 18:00:01 +0200314 if (res) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100315 pr_err("Failed to request percpu irq\n");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200316 return res;
317 }
318
Richard Cochran2c48fef2016-07-13 17:17:06 +0000319 res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING,
Thomas Gleixner73c1b412016-12-21 20:19:54 +0100320 "clockevents/armada:starting",
Richard Cochran2c48fef2016-07-13 17:17:06 +0000321 armada_370_xp_timer_starting_cpu,
322 armada_370_xp_timer_dying_cpu);
Anna-Maria Gleixner1d661bf2016-07-12 16:40:09 +0200323 if (res) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100324 pr_err("Failed to setup hotplug state and timer\n");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200325 return res;
326 }
Thomas Petazzonif9a49ab2014-11-21 17:00:01 +0100327
328 register_syscore_ops(&armada_370_xp_timer_syscore_ops);
Daniel Lezcano12549e22016-06-06 18:00:01 +0200329
330 return 0;
Gregory CLEMENTddd3f692013-01-25 18:32:42 +0100331}
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300332
Daniel Lezcano12549e22016-06-06 18:00:01 +0200333static int __init armada_xp_timer_init(struct device_node *np)
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300334{
Ezequiel Garcia5e9fe6c2013-08-20 12:45:53 -0300335 struct clk *clk = of_clk_get_by_name(np, "fixed");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200336 int ret;
Ezequiel Garcia5e9fe6c2013-08-20 12:45:53 -0300337
Daniel Lezcano12549e22016-06-06 18:00:01 +0200338 if (IS_ERR(clk)) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100339 pr_err("Failed to get clock\n");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200340 return PTR_ERR(clk);
341 }
342
343 ret = clk_prepare_enable(clk);
344 if (ret)
345 return ret;
346
Ezequiel Garcia5e9fe6c2013-08-20 12:45:53 -0300347 timer_clk = clk_get_rate(clk);
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300348
Daniel Lezcano12549e22016-06-06 18:00:01 +0200349 return armada_370_xp_timer_common_init(np);
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300350}
Daniel Lezcano17273392017-05-26 16:56:11 +0200351TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300352 armada_xp_timer_init);
353
Daniel Lezcano12549e22016-06-06 18:00:01 +0200354static int __init armada_375_timer_init(struct device_node *np)
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300355{
356 struct clk *clk;
Daniel Lezcano12549e22016-06-06 18:00:01 +0200357 int ret;
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300358
359 clk = of_clk_get_by_name(np, "fixed");
360 if (!IS_ERR(clk)) {
Daniel Lezcano12549e22016-06-06 18:00:01 +0200361 ret = clk_prepare_enable(clk);
362 if (ret)
363 return ret;
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300364 timer_clk = clk_get_rate(clk);
365 } else {
366
367 /*
368 * This fallback is required in order to retain proper
369 * devicetree backwards compatibility.
370 */
371 clk = of_clk_get(np, 0);
372
373 /* Must have at least a clock */
Daniel Lezcano12549e22016-06-06 18:00:01 +0200374 if (IS_ERR(clk)) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100375 pr_err("Failed to get clock\n");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200376 return PTR_ERR(clk);
377 }
378
379 ret = clk_prepare_enable(clk);
380 if (ret)
381 return ret;
382
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300383 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
384 timer25Mhz = false;
385 }
386
Daniel Lezcano12549e22016-06-06 18:00:01 +0200387 return armada_370_xp_timer_common_init(np);
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300388}
Daniel Lezcano17273392017-05-26 16:56:11 +0200389TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer",
Ezequiel Garcia4a22d9c2014-11-04 10:21:33 -0300390 armada_375_timer_init);
391
Daniel Lezcano12549e22016-06-06 18:00:01 +0200392static int __init armada_370_timer_init(struct device_node *np)
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300393{
Daniel Lezcano12549e22016-06-06 18:00:01 +0200394 struct clk *clk;
395 int ret;
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300396
Daniel Lezcano12549e22016-06-06 18:00:01 +0200397 clk = of_clk_get(np, 0);
398 if (IS_ERR(clk)) {
Rafał Miłeckiac9ce6d2017-03-09 10:47:10 +0100399 pr_err("Failed to get clock\n");
Daniel Lezcano12549e22016-06-06 18:00:01 +0200400 return PTR_ERR(clk);
401 }
402
403 ret = clk_prepare_enable(clk);
404 if (ret)
405 return ret;
406
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300407 timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
408 timer25Mhz = false;
409
Daniel Lezcano12549e22016-06-06 18:00:01 +0200410 return armada_370_xp_timer_common_init(np);
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300411}
Daniel Lezcano17273392017-05-26 16:56:11 +0200412TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer",
Ezequiel Garcia7cd63922013-08-13 11:43:13 -0300413 armada_370_timer_init);