Thomas Gleixner | 09c434b | 2019-05-19 13:08:20 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 2 | /* |
| 3 | * pata_sis.c - SiS ATA driver |
| 4 | * |
Alan Cox | ab77163 | 2008-10-27 15:09:10 +0000 | [diff] [blame] | 5 | * (C) 2005 Red Hat |
Bartlomiej Zolnierkiewicz | 750c713 | 2009-12-03 20:32:13 +0100 | [diff] [blame] | 6 | * (C) 2007,2009 Bartlomiej Zolnierkiewicz |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 7 | * |
| 8 | * Based upon linux/drivers/ide/pci/sis5513.c |
| 9 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> |
| 10 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer |
| 11 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> |
| 12 | * SiS Taiwan : for direct support and hardware. |
| 13 | * Daniela Engert : for initial ATA100 advices and numerous others. |
| 14 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : |
| 15 | * for checking code correctness, providing patches. |
| 16 | * Original tests and design on the SiS620 chipset. |
| 17 | * ATA100 tests and design on the SiS735 chipset. |
| 18 | * ATA16/33 support from specs |
| 19 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> |
| 20 | * |
| 21 | * |
| 22 | * TODO |
| 23 | * Check MWDMA on drives that don't support MWDMA speed pio cycles ? |
| 24 | * More Testing |
| 25 | */ |
| 26 | |
| 27 | #include <linux/kernel.h> |
| 28 | #include <linux/module.h> |
| 29 | #include <linux/pci.h> |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 30 | #include <linux/blkdev.h> |
| 31 | #include <linux/delay.h> |
| 32 | #include <linux/device.h> |
| 33 | #include <scsi/scsi_host.h> |
| 34 | #include <linux/libata.h> |
| 35 | #include <linux/ata.h> |
Alan | 4bb64fb | 2007-02-16 01:40:04 -0800 | [diff] [blame] | 36 | #include "sis.h" |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 37 | |
| 38 | #define DRV_NAME "pata_sis" |
Bartlomiej Zolnierkiewicz | 4761c06 | 2007-07-31 22:02:41 +0200 | [diff] [blame] | 39 | #define DRV_VERSION "0.5.2" |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 40 | |
| 41 | struct sis_chipset { |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 42 | u16 device; /* PCI host ID */ |
| 43 | const struct ata_port_info *info; /* Info block */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 44 | /* Probably add family, cable detect type etc here to clean |
| 45 | up code later */ |
| 46 | }; |
| 47 | |
Jakub W. Jozwicki J | 7dcbc1f | 2007-01-09 09:01:19 +0900 | [diff] [blame] | 48 | struct sis_laptop { |
| 49 | u16 device; |
| 50 | u16 subvendor; |
| 51 | u16 subdevice; |
| 52 | }; |
| 53 | |
| 54 | static const struct sis_laptop sis_laptop[] = { |
| 55 | /* devid, subvendor, subdev */ |
| 56 | { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ |
Alan Cox | 4f2d47c | 2007-08-22 22:56:43 +0100 | [diff] [blame] | 57 | { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 58 | { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ |
Jakub W. Jozwicki J | 7dcbc1f | 2007-01-09 09:01:19 +0900 | [diff] [blame] | 59 | /* end marker */ |
| 60 | { 0, } |
| 61 | }; |
| 62 | |
| 63 | static int sis_short_ata40(struct pci_dev *dev) |
| 64 | { |
| 65 | const struct sis_laptop *lap = &sis_laptop[0]; |
| 66 | |
| 67 | while (lap->device) { |
| 68 | if (lap->device == dev->device && |
| 69 | lap->subvendor == dev->subsystem_vendor && |
| 70 | lap->subdevice == dev->subsystem_device) |
| 71 | return 1; |
| 72 | lap++; |
| 73 | } |
| 74 | |
| 75 | return 0; |
| 76 | } |
| 77 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 78 | /** |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 79 | * sis_old_port_base - return PCI configuration base for dev |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 80 | * @adev: device |
| 81 | * |
| 82 | * Returns the base of the PCI configuration registers for this port |
| 83 | * number. |
| 84 | */ |
| 85 | |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 86 | static int sis_old_port_base(struct ata_device *adev) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 87 | { |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 88 | return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | /** |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 92 | * sis_port_base - return PCI configuration base for dev |
Dan McGee | 023a017 | 2011-09-07 11:23:18 -0500 | [diff] [blame] | 93 | * @adev: device |
| 94 | * |
| 95 | * Returns the base of the PCI configuration registers for this port |
| 96 | * number. |
| 97 | */ |
| 98 | |
| 99 | static int sis_port_base(struct ata_device *adev) |
| 100 | { |
| 101 | struct ata_port *ap = adev->link->ap; |
| 102 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 103 | int port = 0x40; |
| 104 | u32 reg54; |
| 105 | |
| 106 | /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */ |
| 107 | pci_read_config_dword(pdev, 0x54, ®54); |
| 108 | if (reg54 & 0x40000000) |
| 109 | port = 0x70; |
| 110 | |
| 111 | return port + (8 * ap->port_no) + (4 * adev->devno); |
| 112 | } |
| 113 | |
| 114 | /** |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 115 | * sis_133_cable_detect - check for 40/80 pin |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 116 | * @ap: Port |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 117 | * @deadline: deadline jiffies for the operation |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 118 | * |
| 119 | * Perform cable detection for the later UDMA133 capable |
| 120 | * SiS chipset. |
| 121 | */ |
| 122 | |
Alan Cox | 2e413f5 | 2007-03-07 16:54:24 +0000 | [diff] [blame] | 123 | static int sis_133_cable_detect(struct ata_port *ap) |
| 124 | { |
| 125 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 126 | u16 tmp; |
| 127 | |
| 128 | /* The top bit of this register is the cable detect bit */ |
| 129 | pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); |
| 130 | if ((tmp & 0x8000) && !sis_short_ata40(pdev)) |
| 131 | return ATA_CBL_PATA40; |
| 132 | return ATA_CBL_PATA80; |
| 133 | } |
| 134 | |
| 135 | /** |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 136 | * sis_66_cable_detect - check for 40/80 pin |
Alan Cox | 2e413f5 | 2007-03-07 16:54:24 +0000 | [diff] [blame] | 137 | * @ap: Port |
| 138 | * |
| 139 | * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 |
| 140 | * SiS IDE controllers. |
| 141 | */ |
| 142 | |
| 143 | static int sis_66_cable_detect(struct ata_port *ap) |
| 144 | { |
| 145 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 146 | u8 tmp; |
| 147 | |
| 148 | /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ |
| 149 | pci_read_config_byte(pdev, 0x48, &tmp); |
| 150 | tmp >>= ap->port_no; |
| 151 | if ((tmp & 0x10) && !sis_short_ata40(pdev)) |
| 152 | return ATA_CBL_PATA40; |
| 153 | return ATA_CBL_PATA80; |
| 154 | } |
| 155 | |
| 156 | |
| 157 | /** |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 158 | * sis_pre_reset - probe begin |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 159 | * @link: ATA link |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 160 | * @deadline: deadline jiffies for the operation |
Alan Cox | 2e413f5 | 2007-03-07 16:54:24 +0000 | [diff] [blame] | 161 | * |
| 162 | * Set up cable type and use generic probe init |
| 163 | */ |
| 164 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 165 | static int sis_pre_reset(struct ata_link *link, unsigned long deadline) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 166 | { |
| 167 | static const struct pci_bits sis_enable_bits[] = { |
| 168 | { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ |
| 169 | { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ |
| 170 | }; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 171 | |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 172 | struct ata_port *ap = link->ap; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 173 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 174 | |
Alan Cox | c961922 | 2006-09-26 17:53:38 +0100 | [diff] [blame] | 175 | if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) |
| 176 | return -ENOENT; |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 177 | |
Alan Cox | 15ce094 | 2007-05-25 20:50:24 +0100 | [diff] [blame] | 178 | /* Clear the FIFO settings. We can't enable the FIFO until |
| 179 | we know we are poking at a disk */ |
| 180 | pci_write_config_byte(pdev, 0x4B, 0); |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 181 | return ata_sff_prereset(link, deadline); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 182 | } |
| 183 | |
Alan Cox | 2e413f5 | 2007-03-07 16:54:24 +0000 | [diff] [blame] | 184 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 185 | /** |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 186 | * sis_set_fifo - Set RWP fifo bits for this device |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 187 | * @ap: Port |
| 188 | * @adev: Device |
| 189 | * |
| 190 | * SIS chipsets implement prefetch/postwrite bits for each device |
| 191 | * on both channels. This functionality is not ATAPI compatible and |
| 192 | * must be configured according to the class of device present |
| 193 | */ |
| 194 | |
| 195 | static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) |
| 196 | { |
| 197 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 198 | u8 fifoctrl; |
| 199 | u8 mask = 0x11; |
| 200 | |
| 201 | mask <<= (2 * ap->port_no); |
| 202 | mask <<= adev->devno; |
| 203 | |
| 204 | /* This holds various bits including the FIFO control */ |
| 205 | pci_read_config_byte(pdev, 0x4B, &fifoctrl); |
| 206 | fifoctrl &= ~mask; |
| 207 | |
| 208 | /* Enable for ATA (disk) only */ |
| 209 | if (adev->class == ATA_DEV_ATA) |
| 210 | fifoctrl |= mask; |
| 211 | pci_write_config_byte(pdev, 0x4B, fifoctrl); |
| 212 | } |
| 213 | |
| 214 | /** |
| 215 | * sis_old_set_piomode - Initialize host controller PATA PIO timings |
| 216 | * @ap: Port whose timings we are configuring |
| 217 | * @adev: Device we are configuring for. |
| 218 | * |
| 219 | * Set PIO mode for device, in host controller PCI config space. This |
| 220 | * function handles PIO set up for all chips that are pre ATA100 and |
| 221 | * also early ATA100 devices. |
| 222 | * |
| 223 | * LOCKING: |
| 224 | * None (inherited from caller). |
| 225 | */ |
| 226 | |
| 227 | static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) |
| 228 | { |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 229 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 230 | int port = sis_old_port_base(adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 231 | u8 t1, t2; |
| 232 | int speed = adev->pio_mode - XFER_PIO_0; |
| 233 | |
Dan McGee | c03a476 | 2011-09-07 11:23:21 -0500 | [diff] [blame] | 234 | static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; |
| 235 | static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 236 | |
| 237 | sis_set_fifo(ap, adev); |
| 238 | |
| 239 | pci_read_config_byte(pdev, port, &t1); |
| 240 | pci_read_config_byte(pdev, port + 1, &t2); |
| 241 | |
| 242 | t1 &= ~0x0F; /* Clear active/recovery timings */ |
| 243 | t2 &= ~0x07; |
| 244 | |
| 245 | t1 |= active[speed]; |
| 246 | t2 |= recovery[speed]; |
| 247 | |
| 248 | pci_write_config_byte(pdev, port, t1); |
| 249 | pci_write_config_byte(pdev, port + 1, t2); |
| 250 | } |
| 251 | |
| 252 | /** |
Bartlomiej Zolnierkiewicz | 4761c06 | 2007-07-31 22:02:41 +0200 | [diff] [blame] | 253 | * sis_100_set_piomode - Initialize host controller PATA PIO timings |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 254 | * @ap: Port whose timings we are configuring |
| 255 | * @adev: Device we are configuring for. |
| 256 | * |
| 257 | * Set PIO mode for device, in host controller PCI config space. This |
| 258 | * function handles PIO set up for ATA100 devices and early ATA133. |
| 259 | * |
| 260 | * LOCKING: |
| 261 | * None (inherited from caller). |
| 262 | */ |
| 263 | |
| 264 | static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) |
| 265 | { |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 266 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 267 | int port = sis_old_port_base(adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 268 | int speed = adev->pio_mode - XFER_PIO_0; |
| 269 | |
Dan McGee | c03a476 | 2011-09-07 11:23:21 -0500 | [diff] [blame] | 270 | static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 271 | |
| 272 | sis_set_fifo(ap, adev); |
| 273 | |
| 274 | pci_write_config_byte(pdev, port, actrec[speed]); |
| 275 | } |
| 276 | |
| 277 | /** |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 278 | * sis_133_set_piomode - Initialize host controller PATA PIO timings |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 279 | * @ap: Port whose timings we are configuring |
| 280 | * @adev: Device we are configuring for. |
| 281 | * |
| 282 | * Set PIO mode for device, in host controller PCI config space. This |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 283 | * function handles PIO set up for the later ATA133 devices. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 284 | * |
| 285 | * LOCKING: |
| 286 | * None (inherited from caller). |
| 287 | */ |
| 288 | |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 289 | static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 290 | { |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 291 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Dan McGee | 023a017 | 2011-09-07 11:23:18 -0500 | [diff] [blame] | 292 | int port; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 293 | u32 t1; |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 294 | int speed = adev->pio_mode - XFER_PIO_0; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 295 | |
Dan McGee | c03a476 | 2011-09-07 11:23:21 -0500 | [diff] [blame] | 296 | static const u32 timing133[] = { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 297 | 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ |
| 298 | 0x0C266000, |
| 299 | 0x04263000, |
| 300 | 0x0C0A3000, |
| 301 | 0x05093000 |
| 302 | }; |
Dan McGee | c03a476 | 2011-09-07 11:23:21 -0500 | [diff] [blame] | 303 | static const u32 timing100[] = { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 304 | 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ |
| 305 | 0x091C4000, |
| 306 | 0x031C2000, |
| 307 | 0x09072000, |
| 308 | 0x04062000 |
| 309 | }; |
| 310 | |
| 311 | sis_set_fifo(ap, adev); |
| 312 | |
Dan McGee | 023a017 | 2011-09-07 11:23:18 -0500 | [diff] [blame] | 313 | port = sis_port_base(adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 314 | pci_read_config_dword(pdev, port, &t1); |
| 315 | t1 &= 0xC0C00FFF; /* Mask out timing */ |
| 316 | |
| 317 | if (t1 & 0x08) /* 100 or 133 ? */ |
| 318 | t1 |= timing133[speed]; |
| 319 | else |
| 320 | t1 |= timing100[speed]; |
| 321 | pci_write_config_byte(pdev, port, t1); |
| 322 | } |
| 323 | |
| 324 | /** |
| 325 | * sis_old_set_dmamode - Initialize host controller PATA DMA timings |
| 326 | * @ap: Port whose timings we are configuring |
| 327 | * @adev: Device to program |
| 328 | * |
| 329 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
| 330 | * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike |
| 331 | * the old ide/pci driver. |
| 332 | * |
| 333 | * LOCKING: |
| 334 | * None (inherited from caller). |
| 335 | */ |
| 336 | |
| 337 | static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 338 | { |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 339 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 340 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 341 | int drive_pci = sis_old_port_base(adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 342 | u16 timing; |
| 343 | |
Dan McGee | c03a476 | 2011-09-07 11:23:21 -0500 | [diff] [blame] | 344 | static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
| 345 | static const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 346 | |
| 347 | pci_read_config_word(pdev, drive_pci, &timing); |
| 348 | |
| 349 | if (adev->dma_mode < XFER_UDMA_0) { |
| 350 | /* bits 3-0 hold recovery timing bits 8-10 active timing and |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 351 | the higher bits are dependent on the device */ |
Bartlomiej Zolnierkiewicz | 4761c06 | 2007-07-31 22:02:41 +0200 | [diff] [blame] | 352 | timing &= ~0x870F; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 353 | timing |= mwdma_bits[speed]; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 354 | } else { |
| 355 | /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ |
| 356 | speed = adev->dma_mode - XFER_UDMA_0; |
| 357 | timing &= ~0x6000; |
| 358 | timing |= udma_bits[speed]; |
| 359 | } |
Bartlomiej Zolnierkiewicz | 4761c06 | 2007-07-31 22:02:41 +0200 | [diff] [blame] | 360 | pci_write_config_word(pdev, drive_pci, timing); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | /** |
| 364 | * sis_66_set_dmamode - Initialize host controller PATA DMA timings |
| 365 | * @ap: Port whose timings we are configuring |
| 366 | * @adev: Device to program |
| 367 | * |
| 368 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
| 369 | * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike |
| 370 | * the old ide/pci driver. |
| 371 | * |
| 372 | * LOCKING: |
| 373 | * None (inherited from caller). |
| 374 | */ |
| 375 | |
| 376 | static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 377 | { |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 378 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 379 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 380 | int drive_pci = sis_old_port_base(adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 381 | u16 timing; |
| 382 | |
Tejun Heo | edeb614 | 2007-09-21 16:29:05 +0900 | [diff] [blame] | 383 | /* MWDMA 0-2 and UDMA 0-5 */ |
Dan McGee | c03a476 | 2011-09-07 11:23:21 -0500 | [diff] [blame] | 384 | static const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
| 385 | static const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 386 | |
| 387 | pci_read_config_word(pdev, drive_pci, &timing); |
| 388 | |
| 389 | if (adev->dma_mode < XFER_UDMA_0) { |
| 390 | /* bits 3-0 hold recovery timing bits 8-10 active timing and |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 391 | the higher bits are dependent on the device, bit 15 udma */ |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 392 | timing &= ~0x870F; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 393 | timing |= mwdma_bits[speed]; |
| 394 | } else { |
| 395 | /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ |
| 396 | speed = adev->dma_mode - XFER_UDMA_0; |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 397 | timing &= ~0xF000; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 398 | timing |= udma_bits[speed]; |
| 399 | } |
| 400 | pci_write_config_word(pdev, drive_pci, timing); |
| 401 | } |
| 402 | |
| 403 | /** |
| 404 | * sis_100_set_dmamode - Initialize host controller PATA DMA timings |
| 405 | * @ap: Port whose timings we are configuring |
| 406 | * @adev: Device to program |
| 407 | * |
| 408 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 409 | * Handles UDMA66 and early UDMA100 devices. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 410 | * |
| 411 | * LOCKING: |
| 412 | * None (inherited from caller). |
| 413 | */ |
| 414 | |
| 415 | static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 416 | { |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 417 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 418 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 419 | int drive_pci = sis_old_port_base(adev); |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 420 | u8 timing; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 421 | |
Dan McGee | c03a476 | 2011-09-07 11:23:21 -0500 | [diff] [blame] | 422 | static const u8 udma_bits[] = { 0x8B, 0x87, 0x85, 0x83, 0x82, 0x81}; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 423 | |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 424 | pci_read_config_byte(pdev, drive_pci + 1, &timing); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 425 | |
| 426 | if (adev->dma_mode < XFER_UDMA_0) { |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 427 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 428 | } else { |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 429 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 430 | speed = adev->dma_mode - XFER_UDMA_0; |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 431 | timing &= ~0x8F; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 432 | timing |= udma_bits[speed]; |
| 433 | } |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 434 | pci_write_config_byte(pdev, drive_pci + 1, timing); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 435 | } |
| 436 | |
| 437 | /** |
| 438 | * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings |
| 439 | * @ap: Port whose timings we are configuring |
| 440 | * @adev: Device to program |
| 441 | * |
| 442 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
Bartlomiej Zolnierkiewicz | 4761c06 | 2007-07-31 22:02:41 +0200 | [diff] [blame] | 443 | * Handles early SiS 961 bridges. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 444 | * |
| 445 | * LOCKING: |
| 446 | * None (inherited from caller). |
| 447 | */ |
| 448 | |
| 449 | static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 450 | { |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 451 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 452 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 453 | int drive_pci = sis_old_port_base(adev); |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 454 | u8 timing; |
| 455 | /* Low 4 bits are timing */ |
| 456 | static const u8 udma_bits[] = { 0x8F, 0x8A, 0x87, 0x85, 0x83, 0x82, 0x81}; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 457 | |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 458 | pci_read_config_byte(pdev, drive_pci + 1, &timing); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 459 | |
| 460 | if (adev->dma_mode < XFER_UDMA_0) { |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 461 | /* NOT SUPPORTED YET: NEED DATA SHEET. DITTO IN OLD DRIVER */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 462 | } else { |
Alan Cox | dd668d1 | 2007-05-21 15:00:53 +0100 | [diff] [blame] | 463 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 464 | speed = adev->dma_mode - XFER_UDMA_0; |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 465 | timing &= ~0x8F; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 466 | timing |= udma_bits[speed]; |
| 467 | } |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 468 | pci_write_config_byte(pdev, drive_pci + 1, timing); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 469 | } |
| 470 | |
| 471 | /** |
| 472 | * sis_133_set_dmamode - Initialize host controller PATA DMA timings |
| 473 | * @ap: Port whose timings we are configuring |
| 474 | * @adev: Device to program |
| 475 | * |
| 476 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 477 | * |
| 478 | * LOCKING: |
| 479 | * None (inherited from caller). |
| 480 | */ |
| 481 | |
| 482 | static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
| 483 | { |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 484 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Dan McGee | 023a017 | 2011-09-07 11:23:18 -0500 | [diff] [blame] | 485 | int port; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 486 | u32 t1; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 487 | |
Dan McGee | 023a017 | 2011-09-07 11:23:18 -0500 | [diff] [blame] | 488 | port = sis_port_base(adev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 489 | pci_read_config_dword(pdev, port, &t1); |
| 490 | |
| 491 | if (adev->dma_mode < XFER_UDMA_0) { |
Dan McGee | 14004f0 | 2011-09-07 11:23:20 -0500 | [diff] [blame] | 492 | /* Recovery << 24 | Act << 16 | Ini << 12, like PIO modes */ |
| 493 | static const u32 timing_u100[] = { 0x19154000, 0x06072000, 0x04062000 }; |
| 494 | static const u32 timing_u133[] = { 0x221C6000, 0x0C0A3000, 0x05093000 }; |
| 495 | int speed = adev->dma_mode - XFER_MW_DMA_0; |
| 496 | |
| 497 | t1 &= 0xC0C00FFF; |
| 498 | /* disable UDMA */ |
Jeff Garzik | 1b52f2a | 2009-12-07 11:41:25 -0500 | [diff] [blame] | 499 | t1 &= ~0x00000004; |
Dan McGee | 14004f0 | 2011-09-07 11:23:20 -0500 | [diff] [blame] | 500 | if (t1 & 0x08) |
| 501 | t1 |= timing_u133[speed]; |
| 502 | else |
| 503 | t1 |= timing_u100[speed]; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 504 | } else { |
Dan McGee | 14004f0 | 2011-09-07 11:23:20 -0500 | [diff] [blame] | 505 | /* bits 4- cycle time 8 - cvs time */ |
| 506 | static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; |
| 507 | static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; |
Dan McGee | 023a017 | 2011-09-07 11:23:18 -0500 | [diff] [blame] | 508 | int speed = adev->dma_mode - XFER_UDMA_0; |
Dan McGee | 14004f0 | 2011-09-07 11:23:20 -0500 | [diff] [blame] | 509 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 510 | t1 &= ~0x00000FF0; |
Dan McGee | 14004f0 | 2011-09-07 11:23:20 -0500 | [diff] [blame] | 511 | /* enable UDMA */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 512 | t1 |= 0x00000004; |
| 513 | if (t1 & 0x08) |
| 514 | t1 |= timing_u133[speed]; |
| 515 | else |
| 516 | t1 |= timing_u100[speed]; |
| 517 | } |
| 518 | pci_write_config_dword(pdev, port, t1); |
| 519 | } |
| 520 | |
Dan McGee | f30f9a5 | 2011-09-07 11:23:19 -0500 | [diff] [blame] | 521 | /** |
| 522 | * sis_133_mode_filter - mode selection filter |
| 523 | * @adev: ATA device |
| 524 | * |
| 525 | * Block UDMA6 on devices that do not support it. |
| 526 | */ |
| 527 | |
| 528 | static unsigned long sis_133_mode_filter(struct ata_device *adev, unsigned long mask) |
| 529 | { |
| 530 | struct ata_port *ap = adev->link->ap; |
| 531 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
| 532 | int port = sis_port_base(adev); |
| 533 | u32 t1; |
| 534 | |
| 535 | pci_read_config_dword(pdev, port, &t1); |
| 536 | /* if ATA133 is disabled, mask it out */ |
| 537 | if (!(t1 & 0x08)) |
| 538 | mask &= ~(0xC0 << ATA_SHIFT_UDMA); |
| 539 | return mask; |
| 540 | } |
| 541 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 542 | static struct scsi_host_template sis_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 543 | ATA_BMDMA_SHT(DRV_NAME), |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 544 | }; |
| 545 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 546 | static struct ata_port_operations sis_133_for_sata_ops = { |
| 547 | .inherits = &ata_bmdma_port_ops, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 548 | .set_piomode = sis_133_set_piomode, |
| 549 | .set_dmamode = sis_133_set_dmamode, |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 550 | .cable_detect = sis_133_cable_detect, |
| 551 | }; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 552 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 553 | static struct ata_port_operations sis_base_ops = { |
| 554 | .inherits = &ata_bmdma_port_ops, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 555 | .prereset = sis_pre_reset, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 556 | }; |
| 557 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 558 | static struct ata_port_operations sis_133_ops = { |
| 559 | .inherits = &sis_base_ops, |
Uwe Koziolek | a3cabb2 | 2007-06-14 23:40:43 +0200 | [diff] [blame] | 560 | .set_piomode = sis_133_set_piomode, |
| 561 | .set_dmamode = sis_133_set_dmamode, |
Uwe Koziolek | a3cabb2 | 2007-06-14 23:40:43 +0200 | [diff] [blame] | 562 | .cable_detect = sis_133_cable_detect, |
Dan McGee | f30f9a5 | 2011-09-07 11:23:19 -0500 | [diff] [blame] | 563 | .mode_filter = sis_133_mode_filter, |
Uwe Koziolek | a3cabb2 | 2007-06-14 23:40:43 +0200 | [diff] [blame] | 564 | }; |
| 565 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 566 | static struct ata_port_operations sis_133_early_ops = { |
| 567 | .inherits = &sis_base_ops, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 568 | .set_piomode = sis_100_set_piomode, |
| 569 | .set_dmamode = sis_133_early_set_dmamode, |
Alan Cox | 2e413f5 | 2007-03-07 16:54:24 +0000 | [diff] [blame] | 570 | .cable_detect = sis_66_cable_detect, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 571 | }; |
| 572 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 573 | static struct ata_port_operations sis_100_ops = { |
| 574 | .inherits = &sis_base_ops, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 575 | .set_piomode = sis_100_set_piomode, |
| 576 | .set_dmamode = sis_100_set_dmamode, |
Alan Cox | 2e413f5 | 2007-03-07 16:54:24 +0000 | [diff] [blame] | 577 | .cable_detect = sis_66_cable_detect, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 578 | }; |
| 579 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 580 | static struct ata_port_operations sis_66_ops = { |
| 581 | .inherits = &sis_base_ops, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 582 | .set_piomode = sis_old_set_piomode, |
| 583 | .set_dmamode = sis_66_set_dmamode, |
Alan Cox | 2e413f5 | 2007-03-07 16:54:24 +0000 | [diff] [blame] | 584 | .cable_detect = sis_66_cable_detect, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 585 | }; |
| 586 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 587 | static struct ata_port_operations sis_old_ops = { |
| 588 | .inherits = &sis_base_ops, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 589 | .set_piomode = sis_old_set_piomode, |
| 590 | .set_dmamode = sis_old_set_dmamode, |
Alan Cox | 2e413f5 | 2007-03-07 16:54:24 +0000 | [diff] [blame] | 591 | .cable_detect = ata_cable_40wire, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 592 | }; |
| 593 | |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 594 | static const struct ata_port_info sis_info = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 595 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 596 | .pio_mask = ATA_PIO4, |
| 597 | .mwdma_mask = ATA_MWDMA2, |
| 598 | /* No UDMA */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 599 | .port_ops = &sis_old_ops, |
| 600 | }; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 601 | static const struct ata_port_info sis_info33 = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 602 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 603 | .pio_mask = ATA_PIO4, |
| 604 | .mwdma_mask = ATA_MWDMA2, |
| 605 | .udma_mask = ATA_UDMA2, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 606 | .port_ops = &sis_old_ops, |
| 607 | }; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 608 | static const struct ata_port_info sis_info66 = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 609 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 610 | .pio_mask = ATA_PIO4, |
| 611 | /* No MWDMA */ |
| 612 | .udma_mask = ATA_UDMA4, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 613 | .port_ops = &sis_66_ops, |
| 614 | }; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 615 | static const struct ata_port_info sis_info100 = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 616 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 617 | .pio_mask = ATA_PIO4, |
| 618 | /* No MWDMA */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 619 | .udma_mask = ATA_UDMA5, |
| 620 | .port_ops = &sis_100_ops, |
| 621 | }; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 622 | static const struct ata_port_info sis_info100_early = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 623 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 624 | .pio_mask = ATA_PIO4, |
| 625 | /* No MWDMA */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 626 | .udma_mask = ATA_UDMA5, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 627 | .port_ops = &sis_66_ops, |
| 628 | }; |
Uwe Koziolek | a3cabb2 | 2007-06-14 23:40:43 +0200 | [diff] [blame] | 629 | static const struct ata_port_info sis_info133 = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 630 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 631 | .pio_mask = ATA_PIO4, |
Dan McGee | 14004f0 | 2011-09-07 11:23:20 -0500 | [diff] [blame] | 632 | .mwdma_mask = ATA_MWDMA2, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 633 | .udma_mask = ATA_UDMA6, |
| 634 | .port_ops = &sis_133_ops, |
| 635 | }; |
Uwe Koziolek | a3cabb2 | 2007-06-14 23:40:43 +0200 | [diff] [blame] | 636 | const struct ata_port_info sis_info133_for_sata = { |
Sergei Shtylyov | c10f97b | 2011-02-04 22:03:34 +0300 | [diff] [blame] | 637 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 638 | .pio_mask = ATA_PIO4, |
| 639 | /* No MWDMA */ |
Uwe Koziolek | a3cabb2 | 2007-06-14 23:40:43 +0200 | [diff] [blame] | 640 | .udma_mask = ATA_UDMA6, |
| 641 | .port_ops = &sis_133_for_sata_ops, |
| 642 | }; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 643 | static const struct ata_port_info sis_info133_early = { |
Jeff Garzik | 1d2808f | 2007-05-28 06:59:48 -0400 | [diff] [blame] | 644 | .flags = ATA_FLAG_SLAVE_POSS, |
Erik Inge Bolsø | 14bdef9 | 2009-03-14 21:38:24 +0100 | [diff] [blame] | 645 | .pio_mask = ATA_PIO4, |
| 646 | /* No MWDMA */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 647 | .udma_mask = ATA_UDMA6, |
| 648 | .port_ops = &sis_133_early_ops, |
| 649 | }; |
| 650 | |
Alan | 9b14dec | 2007-01-08 16:11:07 +0000 | [diff] [blame] | 651 | /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ |
Uwe Koziolek | a3cabb2 | 2007-06-14 23:40:43 +0200 | [diff] [blame] | 652 | EXPORT_SYMBOL_GPL(sis_info133_for_sata); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 653 | |
| 654 | static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) |
| 655 | { |
| 656 | u16 regw; |
| 657 | u8 reg; |
| 658 | |
| 659 | if (sis->info == &sis_info133) { |
| 660 | pci_read_config_word(pdev, 0x50, ®w); |
| 661 | if (regw & 0x08) |
| 662 | pci_write_config_word(pdev, 0x50, regw & ~0x08); |
| 663 | pci_read_config_word(pdev, 0x52, ®w); |
| 664 | if (regw & 0x08) |
| 665 | pci_write_config_word(pdev, 0x52, regw & ~0x08); |
| 666 | return; |
| 667 | } |
| 668 | |
| 669 | if (sis->info == &sis_info133_early || sis->info == &sis_info100) { |
| 670 | /* Fix up latency */ |
| 671 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); |
| 672 | /* Set compatibility bit */ |
| 673 | pci_read_config_byte(pdev, 0x49, ®); |
| 674 | if (!(reg & 0x01)) |
| 675 | pci_write_config_byte(pdev, 0x49, reg | 0x01); |
| 676 | return; |
| 677 | } |
| 678 | |
| 679 | if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { |
| 680 | /* Fix up latency */ |
| 681 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); |
| 682 | /* Set compatibility bit */ |
| 683 | pci_read_config_byte(pdev, 0x52, ®); |
| 684 | if (!(reg & 0x04)) |
| 685 | pci_write_config_byte(pdev, 0x52, reg | 0x04); |
| 686 | return; |
| 687 | } |
| 688 | |
| 689 | if (sis->info == &sis_info33) { |
| 690 | pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); |
| 691 | if (( reg & 0x0F ) != 0x00) |
| 692 | pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); |
| 693 | /* Fall through to ATA16 fixup below */ |
| 694 | } |
| 695 | |
| 696 | if (sis->info == &sis_info || sis->info == &sis_info33) { |
| 697 | /* force per drive recovery and active timings |
| 698 | needed on ATA_33 and below chips */ |
| 699 | pci_read_config_byte(pdev, 0x52, ®); |
| 700 | if (!(reg & 0x08)) |
| 701 | pci_write_config_byte(pdev, 0x52, reg|0x08); |
| 702 | return; |
| 703 | } |
| 704 | |
| 705 | BUG(); |
| 706 | } |
| 707 | |
| 708 | /** |
| 709 | * sis_init_one - Register SiS ATA PCI device with kernel services |
| 710 | * @pdev: PCI device to register |
| 711 | * @ent: Entry in sis_pci_tbl matching with @pdev |
| 712 | * |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 713 | * Called from kernel PCI layer. We probe for combined mode (sigh), |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 714 | * and then hand over control to libata, for it to do the rest. |
| 715 | * |
| 716 | * LOCKING: |
| 717 | * Inherited from PCI layer (may sleep). |
| 718 | * |
| 719 | * RETURNS: |
| 720 | * Zero on success, or -ERRNO value. |
| 721 | */ |
| 722 | |
| 723 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
| 724 | { |
Tejun Heo | 887125e | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 725 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 726 | struct pci_dev *host = NULL; |
| 727 | struct sis_chipset *chipset = NULL; |
Alan Cox | f3769e9 | 2007-04-19 11:09:52 +0100 | [diff] [blame] | 728 | struct sis_chipset *sets; |
Tejun Heo | f08048e | 2008-03-25 12:22:47 +0900 | [diff] [blame] | 729 | int rc; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 730 | |
| 731 | static struct sis_chipset sis_chipsets[] = { |
Jeff Garzik | f20b16f | 2006-12-11 11:14:06 -0500 | [diff] [blame] | 732 | |
Alan Cox | af323a2 | 2006-09-12 17:15:12 +0100 | [diff] [blame] | 733 | { 0x0968, &sis_info133 }, |
| 734 | { 0x0966, &sis_info133 }, |
| 735 | { 0x0965, &sis_info133 }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 736 | { 0x0745, &sis_info100 }, |
| 737 | { 0x0735, &sis_info100 }, |
| 738 | { 0x0733, &sis_info100 }, |
| 739 | { 0x0635, &sis_info100 }, |
| 740 | { 0x0633, &sis_info100 }, |
| 741 | |
| 742 | { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ |
| 743 | { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ |
| 744 | |
| 745 | { 0x0640, &sis_info66 }, |
| 746 | { 0x0630, &sis_info66 }, |
| 747 | { 0x0620, &sis_info66 }, |
| 748 | { 0x0540, &sis_info66 }, |
| 749 | { 0x0530, &sis_info66 }, |
| 750 | |
| 751 | { 0x5600, &sis_info33 }, |
| 752 | { 0x5598, &sis_info33 }, |
| 753 | { 0x5597, &sis_info33 }, |
| 754 | { 0x5591, &sis_info33 }, |
| 755 | { 0x5582, &sis_info33 }, |
| 756 | { 0x5581, &sis_info33 }, |
| 757 | |
| 758 | { 0x5596, &sis_info }, |
| 759 | { 0x5571, &sis_info }, |
| 760 | { 0x5517, &sis_info }, |
| 761 | { 0x5511, &sis_info }, |
| 762 | |
| 763 | {0} |
| 764 | }; |
| 765 | static struct sis_chipset sis133_early = { |
| 766 | 0x0, &sis_info133_early |
| 767 | }; |
| 768 | static struct sis_chipset sis133 = { |
| 769 | 0x0, &sis_info133 |
| 770 | }; |
| 771 | static struct sis_chipset sis100_early = { |
| 772 | 0x0, &sis_info100_early |
| 773 | }; |
| 774 | static struct sis_chipset sis100 = { |
| 775 | 0x0, &sis_info100 |
| 776 | }; |
| 777 | |
Joe Perches | 06296a1 | 2011-04-15 15:52:00 -0700 | [diff] [blame] | 778 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 779 | |
Tejun Heo | f08048e | 2008-03-25 12:22:47 +0900 | [diff] [blame] | 780 | rc = pcim_enable_device(pdev); |
| 781 | if (rc) |
| 782 | return rc; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 783 | |
Tejun Heo | f08048e | 2008-03-25 12:22:47 +0900 | [diff] [blame] | 784 | /* We have to find the bridge first */ |
Alan Cox | f3769e9 | 2007-04-19 11:09:52 +0100 | [diff] [blame] | 785 | for (sets = &sis_chipsets[0]; sets->device; sets++) { |
| 786 | host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 787 | if (host != NULL) { |
Alan Cox | f3769e9 | 2007-04-19 11:09:52 +0100 | [diff] [blame] | 788 | chipset = sets; /* Match found */ |
| 789 | if (sets->device == 0x630) { /* SIS630 */ |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 790 | if (host->revision >= 0x30) /* 630 ET */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 791 | chipset = &sis100_early; |
| 792 | } |
| 793 | break; |
| 794 | } |
| 795 | } |
| 796 | |
| 797 | /* Look for concealed bridges */ |
Alan Cox | f3769e9 | 2007-04-19 11:09:52 +0100 | [diff] [blame] | 798 | if (chipset == NULL) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 799 | /* Second check */ |
| 800 | u32 idemisc; |
| 801 | u16 trueid; |
| 802 | |
| 803 | /* Disable ID masking and register remapping then |
| 804 | see what the real ID is */ |
| 805 | |
| 806 | pci_read_config_dword(pdev, 0x54, &idemisc); |
| 807 | pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); |
| 808 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); |
| 809 | pci_write_config_dword(pdev, 0x54, idemisc); |
| 810 | |
| 811 | switch(trueid) { |
| 812 | case 0x5518: /* SIS 962/963 */ |
Dan McGee | f30f9a5 | 2011-09-07 11:23:19 -0500 | [diff] [blame] | 813 | dev_info(&pdev->dev, |
| 814 | "SiS 962/963 MuTIOL IDE UDMA133 controller\n"); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 815 | chipset = &sis133; |
| 816 | if ((idemisc & 0x40000000) == 0) { |
| 817 | pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); |
Dan McGee | f30f9a5 | 2011-09-07 11:23:19 -0500 | [diff] [blame] | 818 | dev_info(&pdev->dev, |
| 819 | "Switching to 5513 register mapping\n"); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 820 | } |
| 821 | break; |
| 822 | case 0x0180: /* SIS 965/965L */ |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 823 | chipset = &sis133; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 824 | break; |
| 825 | case 0x1180: /* SIS 966/966L */ |
Dan McGee | edc7d12 | 2011-09-07 11:23:22 -0500 | [diff] [blame] | 826 | chipset = &sis133; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 827 | break; |
| 828 | } |
| 829 | } |
| 830 | |
| 831 | /* Further check */ |
| 832 | if (chipset == NULL) { |
| 833 | struct pci_dev *lpc_bridge; |
| 834 | u16 trueid; |
| 835 | u8 prefctl; |
| 836 | u8 idecfg; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 837 | |
| 838 | /* Try the second unmasking technique */ |
| 839 | pci_read_config_byte(pdev, 0x4a, &idecfg); |
| 840 | pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); |
| 841 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); |
| 842 | pci_write_config_byte(pdev, 0x4a, idecfg); |
| 843 | |
| 844 | switch(trueid) { |
| 845 | case 0x5517: |
| 846 | lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ |
| 847 | if (lpc_bridge == NULL) |
| 848 | break; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 849 | pci_read_config_byte(pdev, 0x49, &prefctl); |
| 850 | pci_dev_put(lpc_bridge); |
| 851 | |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 852 | if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 853 | chipset = &sis133_early; |
| 854 | break; |
| 855 | } |
| 856 | chipset = &sis100; |
| 857 | break; |
| 858 | } |
| 859 | } |
| 860 | pci_dev_put(host); |
| 861 | |
| 862 | /* No chipset info, no support */ |
| 863 | if (chipset == NULL) |
| 864 | return -ENODEV; |
| 865 | |
Tejun Heo | 887125e | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 866 | ppi[0] = chipset->info; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 867 | |
| 868 | sis_fixup(pdev, chipset); |
| 869 | |
Tejun Heo | 1c5afdf | 2010-05-19 22:10:22 +0200 | [diff] [blame] | 870 | return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 871 | } |
| 872 | |
Bartlomiej Zolnierkiewicz | 58eb8cd | 2014-05-07 17:17:44 +0200 | [diff] [blame] | 873 | #ifdef CONFIG_PM_SLEEP |
Bartlomiej Zolnierkiewicz | 750c713 | 2009-12-03 20:32:13 +0100 | [diff] [blame] | 874 | static int sis_reinit_one(struct pci_dev *pdev) |
| 875 | { |
Jingoo Han | 0a86e1c | 2013-06-03 14:05:36 +0900 | [diff] [blame] | 876 | struct ata_host *host = pci_get_drvdata(pdev); |
Bartlomiej Zolnierkiewicz | 750c713 | 2009-12-03 20:32:13 +0100 | [diff] [blame] | 877 | int rc; |
| 878 | |
| 879 | rc = ata_pci_device_do_resume(pdev); |
| 880 | if (rc) |
| 881 | return rc; |
| 882 | |
| 883 | sis_fixup(pdev, host->private_data); |
| 884 | |
| 885 | ata_host_resume(host); |
| 886 | return 0; |
| 887 | } |
| 888 | #endif |
| 889 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 890 | static const struct pci_device_id sis_pci_tbl[] = { |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 891 | { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ |
| 892 | { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ |
Uwe Koziolek | a3cabb2 | 2007-06-14 23:40:43 +0200 | [diff] [blame] | 893 | { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ |
Jeff Garzik | 2d2744f | 2006-09-28 20:21:59 -0400 | [diff] [blame] | 894 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 895 | { } |
| 896 | }; |
| 897 | |
| 898 | static struct pci_driver sis_pci_driver = { |
| 899 | .name = DRV_NAME, |
| 900 | .id_table = sis_pci_tbl, |
| 901 | .probe = sis_init_one, |
| 902 | .remove = ata_pci_remove_one, |
Bartlomiej Zolnierkiewicz | 58eb8cd | 2014-05-07 17:17:44 +0200 | [diff] [blame] | 903 | #ifdef CONFIG_PM_SLEEP |
Alan | 62d64ae | 2006-11-27 16:27:20 +0000 | [diff] [blame] | 904 | .suspend = ata_pci_device_suspend, |
Bartlomiej Zolnierkiewicz | 750c713 | 2009-12-03 20:32:13 +0100 | [diff] [blame] | 905 | .resume = sis_reinit_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 906 | #endif |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 907 | }; |
| 908 | |
Axel Lin | 2fc75da | 2012-04-19 13:43:05 +0800 | [diff] [blame] | 909 | module_pci_driver(sis_pci_driver); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 910 | |
| 911 | MODULE_AUTHOR("Alan Cox"); |
| 912 | MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); |
| 913 | MODULE_LICENSE("GPL"); |
| 914 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); |
| 915 | MODULE_VERSION(DRV_VERSION); |