Tom Rix | 6f3cf24 | 2022-02-17 09:34:53 -0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017, Intel Corporation |
| 4 | */ |
| 5 | #include <linux/slab.h> |
| 6 | #include <linux/clk-provider.h> |
Stephen Boyd | 62e59c4 | 2019-04-18 15:20:22 -0700 | [diff] [blame] | 7 | #include <linux/io.h> |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 8 | |
| 9 | #include "stratix10-clk.h" |
| 10 | #include "clk.h" |
| 11 | |
| 12 | /* Clock Manager offsets */ |
| 13 | #define CLK_MGR_PLL_CLK_SRC_SHIFT 16 |
| 14 | #define CLK_MGR_PLL_CLK_SRC_MASK 0x3 |
| 15 | |
| 16 | /* PLL Clock enable bits */ |
| 17 | #define SOCFPGA_PLL_POWER 0 |
| 18 | #define SOCFPGA_PLL_RESET_MASK 0x2 |
| 19 | #define SOCFPGA_PLL_REFDIV_MASK 0x00003F00 |
| 20 | #define SOCFPGA_PLL_REFDIV_SHIFT 8 |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 21 | #define SOCFPGA_PLL_AREFDIV_MASK 0x00000F00 |
| 22 | #define SOCFPGA_PLL_DREFDIV_MASK 0x00003000 |
| 23 | #define SOCFPGA_PLL_DREFDIV_SHIFT 12 |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 24 | #define SOCFPGA_PLL_MDIV_MASK 0xFF000000 |
| 25 | #define SOCFPGA_PLL_MDIV_SHIFT 24 |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 26 | #define SOCFPGA_AGILEX_PLL_MDIV_MASK 0x000003FF |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 27 | #define SWCTRLBTCLKSEL_MASK 0x200 |
| 28 | #define SWCTRLBTCLKSEL_SHIFT 9 |
| 29 | |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 30 | #define SOCFPGA_N5X_PLLDIV_FDIV_MASK GENMASK(16, 8) |
| 31 | #define SOCFPGA_N5X_PLLDIV_FDIV_SHIFT 8 |
| 32 | #define SOCFPGA_N5X_PLLDIV_RDIV_MASK GENMASK(5, 0) |
| 33 | #define SOCFPGA_N5X_PLLDIV_QDIV_MASK GENMASK(26, 24) |
| 34 | #define SOCFPGA_N5X_PLLDIV_QDIV_SHIFT 24 |
| 35 | |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 36 | #define SOCFPGA_BOOT_CLK "boot_clk" |
| 37 | |
| 38 | #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw) |
| 39 | |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 40 | static unsigned long n5x_clk_pll_recalc_rate(struct clk_hw *hwclk, |
| 41 | unsigned long parent_rate) |
| 42 | { |
| 43 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); |
| 44 | unsigned long fdiv, reg, rdiv, qdiv; |
| 45 | u32 power = 1; |
| 46 | |
| 47 | /* read VCO1 reg for numerator and denominator */ |
| 48 | reg = readl(socfpgaclk->hw.reg + 0x8); |
| 49 | fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT; |
| 50 | rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK); |
| 51 | qdiv = (reg & SOCFPGA_N5X_PLLDIV_QDIV_MASK) >> SOCFPGA_N5X_PLLDIV_QDIV_SHIFT; |
| 52 | |
| 53 | while (qdiv) { |
| 54 | power *= 2; |
| 55 | qdiv--; |
| 56 | } |
| 57 | |
| 58 | return ((parent_rate * 2 * (fdiv + 1)) / ((rdiv + 1) * power)); |
| 59 | } |
| 60 | |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 61 | static unsigned long agilex_clk_pll_recalc_rate(struct clk_hw *hwclk, |
| 62 | unsigned long parent_rate) |
| 63 | { |
| 64 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); |
| 65 | unsigned long arefdiv, reg, mdiv; |
| 66 | unsigned long long vco_freq; |
| 67 | |
| 68 | /* read VCO1 reg for numerator and denominator */ |
| 69 | reg = readl(socfpgaclk->hw.reg); |
| 70 | arefdiv = (reg & SOCFPGA_PLL_AREFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT; |
| 71 | |
| 72 | vco_freq = (unsigned long long)parent_rate / arefdiv; |
| 73 | |
| 74 | /* Read mdiv and fdiv from the fdbck register */ |
| 75 | reg = readl(socfpgaclk->hw.reg + 0x24); |
| 76 | mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK; |
| 77 | |
| 78 | vco_freq = (unsigned long long)vco_freq * mdiv; |
| 79 | return (unsigned long)vco_freq; |
| 80 | } |
| 81 | |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 82 | static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, |
| 83 | unsigned long parent_rate) |
| 84 | { |
| 85 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); |
| 86 | unsigned long mdiv; |
| 87 | unsigned long refdiv; |
| 88 | unsigned long reg; |
| 89 | unsigned long long vco_freq; |
| 90 | |
| 91 | /* read VCO1 reg for numerator and denominator */ |
| 92 | reg = readl(socfpgaclk->hw.reg); |
| 93 | refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT; |
Dinh Nguyen | cc26ed7 | 2020-01-14 10:07:25 -0600 | [diff] [blame] | 94 | |
| 95 | vco_freq = parent_rate; |
| 96 | do_div(vco_freq, refdiv); |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 97 | |
| 98 | /* Read mdiv and fdiv from the fdbck register */ |
| 99 | reg = readl(socfpgaclk->hw.reg + 0x4); |
| 100 | mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT; |
Dinh Nguyen | c0a636e | 2018-12-17 18:06:14 -0600 | [diff] [blame] | 101 | vco_freq = (unsigned long long)vco_freq * (mdiv + 6); |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 102 | |
| 103 | return (unsigned long)vco_freq; |
| 104 | } |
| 105 | |
| 106 | static unsigned long clk_boot_clk_recalc_rate(struct clk_hw *hwclk, |
| 107 | unsigned long parent_rate) |
| 108 | { |
| 109 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); |
Colin Ian King | 52d1a8d | 2021-04-06 19:27:46 +0100 | [diff] [blame] | 110 | u32 div; |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 111 | |
| 112 | div = ((readl(socfpgaclk->hw.reg) & |
| 113 | SWCTRLBTCLKSEL_MASK) >> |
| 114 | SWCTRLBTCLKSEL_SHIFT); |
| 115 | div += 1; |
Colin Ian King | 08d92c7 | 2021-12-21 00:37:50 +0000 | [diff] [blame] | 116 | return parent_rate / div; |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | |
| 120 | static u8 clk_pll_get_parent(struct clk_hw *hwclk) |
| 121 | { |
| 122 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); |
| 123 | u32 pll_src; |
| 124 | |
| 125 | pll_src = readl(socfpgaclk->hw.reg); |
| 126 | return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) & |
| 127 | CLK_MGR_PLL_CLK_SRC_MASK; |
| 128 | } |
| 129 | |
| 130 | static u8 clk_boot_get_parent(struct clk_hw *hwclk) |
| 131 | { |
| 132 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); |
| 133 | u32 pll_src; |
| 134 | |
| 135 | pll_src = readl(socfpgaclk->hw.reg); |
| 136 | return (pll_src >> SWCTRLBTCLKSEL_SHIFT) & |
| 137 | SWCTRLBTCLKSEL_MASK; |
| 138 | } |
| 139 | |
| 140 | static int clk_pll_prepare(struct clk_hw *hwclk) |
| 141 | { |
| 142 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); |
| 143 | u32 reg; |
| 144 | |
| 145 | /* Bring PLL out of reset */ |
| 146 | reg = readl(socfpgaclk->hw.reg); |
| 147 | reg |= SOCFPGA_PLL_RESET_MASK; |
| 148 | writel(reg, socfpgaclk->hw.reg); |
| 149 | |
| 150 | return 0; |
| 151 | } |
| 152 | |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 153 | static int n5x_clk_pll_prepare(struct clk_hw *hwclk) |
| 154 | { |
| 155 | struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); |
| 156 | u32 reg; |
| 157 | |
| 158 | /* Bring PLL out of reset */ |
| 159 | reg = readl(socfpgaclk->hw.reg + 0x4); |
| 160 | reg |= SOCFPGA_PLL_RESET_MASK; |
| 161 | writel(reg, socfpgaclk->hw.reg + 0x4); |
| 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | |
| 166 | static const struct clk_ops n5x_clk_pll_ops = { |
| 167 | .recalc_rate = n5x_clk_pll_recalc_rate, |
| 168 | .get_parent = clk_pll_get_parent, |
| 169 | .prepare = n5x_clk_pll_prepare, |
| 170 | }; |
| 171 | |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 172 | static const struct clk_ops agilex_clk_pll_ops = { |
| 173 | .recalc_rate = agilex_clk_pll_recalc_rate, |
| 174 | .get_parent = clk_pll_get_parent, |
| 175 | .prepare = clk_pll_prepare, |
| 176 | }; |
| 177 | |
Dinh Nguyen | d52579c | 2020-05-12 13:16:45 -0500 | [diff] [blame] | 178 | static const struct clk_ops clk_pll_ops = { |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 179 | .recalc_rate = clk_pll_recalc_rate, |
| 180 | .get_parent = clk_pll_get_parent, |
| 181 | .prepare = clk_pll_prepare, |
| 182 | }; |
| 183 | |
Dinh Nguyen | d52579c | 2020-05-12 13:16:45 -0500 | [diff] [blame] | 184 | static const struct clk_ops clk_boot_ops = { |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 185 | .recalc_rate = clk_boot_clk_recalc_rate, |
| 186 | .get_parent = clk_boot_get_parent, |
| 187 | .prepare = clk_pll_prepare, |
| 188 | }; |
| 189 | |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 190 | struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks, |
Dinh Nguyen | 8c0e783 | 2020-01-14 10:07:26 -0600 | [diff] [blame] | 191 | void __iomem *reg) |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 192 | { |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 193 | struct clk_hw *hw_clk; |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 194 | struct socfpga_pll *pll_clk; |
| 195 | struct clk_init_data init; |
Dinh Nguyen | 8c0e783 | 2020-01-14 10:07:26 -0600 | [diff] [blame] | 196 | const char *name = clks->name; |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 197 | int ret; |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 198 | |
| 199 | pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); |
| 200 | if (WARN_ON(!pll_clk)) |
| 201 | return NULL; |
| 202 | |
Dinh Nguyen | 8c0e783 | 2020-01-14 10:07:26 -0600 | [diff] [blame] | 203 | pll_clk->hw.reg = reg + clks->offset; |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 204 | |
| 205 | if (streq(name, SOCFPGA_BOOT_CLK)) |
| 206 | init.ops = &clk_boot_ops; |
| 207 | else |
| 208 | init.ops = &clk_pll_ops; |
| 209 | |
| 210 | init.name = name; |
Dinh Nguyen | 8c0e783 | 2020-01-14 10:07:26 -0600 | [diff] [blame] | 211 | init.flags = clks->flags; |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 212 | |
Dinh Nguyen | 8c0e783 | 2020-01-14 10:07:26 -0600 | [diff] [blame] | 213 | init.num_parents = clks->num_parents; |
Dinh Nguyen | 762d961 | 2020-05-12 13:16:43 -0500 | [diff] [blame] | 214 | init.parent_names = NULL; |
| 215 | init.parent_data = clks->parent_data; |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 216 | pll_clk->hw.hw.init = &init; |
| 217 | |
| 218 | pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 219 | |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 220 | hw_clk = &pll_clk->hw.hw; |
| 221 | |
| 222 | ret = clk_hw_register(NULL, hw_clk); |
| 223 | if (ret) { |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 224 | kfree(pll_clk); |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 225 | return ERR_PTR(ret); |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 226 | } |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 227 | return hw_clk; |
Dinh Nguyen | 07afb8d | 2018-03-21 09:20:12 -0500 | [diff] [blame] | 228 | } |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 229 | |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 230 | struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks, |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 231 | void __iomem *reg) |
| 232 | { |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 233 | struct clk_hw *hw_clk; |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 234 | struct socfpga_pll *pll_clk; |
| 235 | struct clk_init_data init; |
| 236 | const char *name = clks->name; |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 237 | int ret; |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 238 | |
| 239 | pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); |
| 240 | if (WARN_ON(!pll_clk)) |
| 241 | return NULL; |
| 242 | |
| 243 | pll_clk->hw.reg = reg + clks->offset; |
| 244 | |
| 245 | if (streq(name, SOCFPGA_BOOT_CLK)) |
| 246 | init.ops = &clk_boot_ops; |
| 247 | else |
| 248 | init.ops = &agilex_clk_pll_ops; |
| 249 | |
| 250 | init.name = name; |
| 251 | init.flags = clks->flags; |
| 252 | |
| 253 | init.num_parents = clks->num_parents; |
| 254 | init.parent_names = NULL; |
| 255 | init.parent_data = clks->parent_data; |
| 256 | pll_clk->hw.hw.init = &init; |
| 257 | |
| 258 | pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 259 | hw_clk = &pll_clk->hw.hw; |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 260 | |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 261 | ret = clk_hw_register(NULL, hw_clk); |
| 262 | if (ret) { |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 263 | kfree(pll_clk); |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 264 | return ERR_PTR(ret); |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 265 | } |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 266 | return hw_clk; |
Dinh Nguyen | 80c6b7a | 2020-05-12 13:16:47 -0500 | [diff] [blame] | 267 | } |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 268 | |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 269 | struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks, |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 270 | void __iomem *reg) |
| 271 | { |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 272 | struct clk_hw *hw_clk; |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 273 | struct socfpga_pll *pll_clk; |
| 274 | struct clk_init_data init; |
| 275 | const char *name = clks->name; |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 276 | int ret; |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 277 | |
| 278 | pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); |
| 279 | if (WARN_ON(!pll_clk)) |
| 280 | return NULL; |
| 281 | |
| 282 | pll_clk->hw.reg = reg + clks->offset; |
| 283 | |
| 284 | if (streq(name, SOCFPGA_BOOT_CLK)) |
| 285 | init.ops = &clk_boot_ops; |
| 286 | else |
| 287 | init.ops = &n5x_clk_pll_ops; |
| 288 | |
| 289 | init.name = name; |
| 290 | init.flags = clks->flags; |
| 291 | |
| 292 | init.num_parents = clks->num_parents; |
| 293 | init.parent_names = NULL; |
| 294 | init.parent_data = clks->parent_data; |
| 295 | pll_clk->hw.hw.init = &init; |
| 296 | |
| 297 | pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 298 | hw_clk = &pll_clk->hw.hw; |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 299 | |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 300 | ret = clk_hw_register(NULL, hw_clk); |
| 301 | if (ret) { |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 302 | kfree(pll_clk); |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 303 | return ERR_PTR(ret); |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 304 | } |
Dinh Nguyen | ba7e258 | 2021-03-02 15:41:51 -0600 | [diff] [blame] | 305 | return hw_clk; |
Dinh Nguyen | a0f9819 | 2021-02-12 08:30:59 -0600 | [diff] [blame] | 306 | } |