blob: c36fc26dcdffe125a6493c9d1edf6938425125b0 [file] [log] [blame]
Thomas Gleixner97fb5e82019-05-29 07:17:58 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Stephen Boyd45dd0e52015-08-06 16:07:42 +05302/*
Amit Nischal44dbeeb2018-04-09 14:11:44 +05303 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
Stephen Boyd45dd0e52015-08-06 16:07:42 +05304 */
5
6#ifndef __QCOM_GDSC_H__
7#define __QCOM_GDSC_H__
8
9#include <linux/err.h>
10#include <linux/pm_domain.h>
11
12struct regmap;
Bjorn Andersson37416e52020-04-17 00:00:41 -070013struct regulator;
Rajendra Nayak3c53f5e2015-08-06 16:07:45 +053014struct reset_controller_dev;
Stephen Boyd45dd0e52015-08-06 16:07:42 +053015
16/**
17 * struct gdsc - Globally Distributed Switch Controller
18 * @pd: generic power domain
19 * @regmap: regmap for MMIO accesses
20 * @gdscr: gsdc control register
Rajendra Nayak77b10672015-12-01 21:42:12 +053021 * @gds_hw_ctrl: gds_hw_ctrl register
Rajendra Nayak014e1932015-08-06 16:07:44 +053022 * @cxcs: offsets of branch registers to toggle mem/periph bits in
23 * @cxc_count: number of @cxcs
24 * @pwrsts: Possible powerdomain power states
Rajendra Nayak3c53f5e2015-08-06 16:07:45 +053025 * @resets: ids of resets associated with this gdsc
26 * @reset_count: number of @resets
27 * @rcdev: reset controller
Stephen Boyd45dd0e52015-08-06 16:07:42 +053028 */
29struct gdsc {
30 struct generic_pm_domain pd;
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +053031 struct generic_pm_domain *parent;
Stephen Boyd45dd0e52015-08-06 16:07:42 +053032 struct regmap *regmap;
33 unsigned int gdscr;
Rajendra Nayak77b10672015-12-01 21:42:12 +053034 unsigned int gds_hw_ctrl;
Rajendra Nayake7cc4552016-10-20 15:08:06 +053035 unsigned int clamp_io_ctrl;
Rajendra Nayak014e1932015-08-06 16:07:44 +053036 unsigned int *cxcs;
37 unsigned int cxc_count;
38 const u8 pwrsts;
Rajendra Nayaka823bb92015-12-01 21:42:13 +053039/* Powerdomain allowable state bitfields */
40#define PWRSTS_OFF BIT(0)
41#define PWRSTS_RET BIT(1)
42#define PWRSTS_ON BIT(2)
43#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
44#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
45 const u8 flags;
46#define VOTABLE BIT(0)
Rajendra Nayake7cc4552016-10-20 15:08:06 +053047#define CLAMP_IO BIT(1)
Rajendra Nayak904bb4f2016-11-18 17:58:26 +053048#define HW_CTRL BIT(2)
Amit Nischal44dbeeb2018-04-09 14:11:44 +053049#define SW_RESET BIT(3)
50#define AON_RESET BIT(4)
Amit Nischale892e172018-05-01 10:33:33 +053051#define POLL_CFG_GDSCR BIT(5)
Stephen Boyd77122d62018-06-04 12:34:51 -070052#define ALWAYS_ON BIT(6)
Rajendra Nayak3c53f5e2015-08-06 16:07:45 +053053 struct reset_controller_dev *rcdev;
54 unsigned int *resets;
55 unsigned int reset_count;
Bjorn Andersson37416e52020-04-17 00:00:41 -070056
57 const char *supply;
58 struct regulator *rsupply;
Stephen Boyd45dd0e52015-08-06 16:07:42 +053059};
60
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +053061struct gdsc_desc {
62 struct device *dev;
63 struct gdsc **scs;
64 size_t num;
65};
66
Stephen Boyd45dd0e52015-08-06 16:07:42 +053067#ifdef CONFIG_QCOM_GDSC
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +053068int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
69 struct regmap *);
70void gdsc_unregister(struct gdsc_desc *desc);
Stephen Boyd45dd0e52015-08-06 16:07:42 +053071#else
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +053072static inline int gdsc_register(struct gdsc_desc *desc,
Rajendra Nayak3c53f5e2015-08-06 16:07:45 +053073 struct reset_controller_dev *rcdev,
Stephen Boyd45dd0e52015-08-06 16:07:42 +053074 struct regmap *r)
75{
76 return -ENOSYS;
77}
78
Rajendra Nayakc2c7f0a2015-12-01 21:42:11 +053079static inline void gdsc_unregister(struct gdsc_desc *desc) {};
Stephen Boyd45dd0e52015-08-06 16:07:42 +053080#endif /* CONFIG_QCOM_GDSC */
81#endif /* __QCOM_GDSC_H__ */