Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include "amdgpu.h" |
| 24 | #include "gfxhub_v1_0.h" |
| 25 | |
| 26 | #include "vega10/soc15ip.h" |
| 27 | #include "vega10/GC/gc_9_0_offset.h" |
| 28 | #include "vega10/GC/gc_9_0_sh_mask.h" |
| 29 | #include "vega10/GC/gc_9_0_default.h" |
| 30 | #include "vega10/vega10_enum.h" |
| 31 | |
| 32 | #include "soc15_common.h" |
| 33 | |
Chunming Zhou | 2d8e898 | 2016-12-15 11:15:27 +0800 | [diff] [blame] | 34 | u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) |
| 35 | { |
| 36 | return (u64)RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_OFFSET)) << 24; |
| 37 | } |
| 38 | |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 39 | int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) |
| 40 | { |
| 41 | u32 tmp; |
| 42 | u64 value; |
| 43 | u32 i; |
| 44 | |
| 45 | /* Program MC. */ |
| 46 | /* Update configuration */ |
| 47 | WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR), |
| 48 | adev->mc.vram_start >> 18); |
| 49 | WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR), |
| 50 | adev->mc.vram_end >> 18); |
| 51 | |
| 52 | value = adev->vram_scratch.gpu_addr - adev->mc.vram_start |
| 53 | + adev->vm_manager.vram_base_offset; |
| 54 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 55 | mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB), |
| 56 | (u32)(value >> 12)); |
| 57 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 58 | mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB), |
| 59 | (u32)(value >> 44)); |
| 60 | |
Monk Liu | eeb2487 | 2017-03-23 16:32:13 +0800 | [diff] [blame] | 61 | if (amdgpu_sriov_vf(adev)) { |
| 62 | /* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are VF copy registers so |
| 63 | vbios post doesn't program them, for SRIOV driver need to program them */ |
| 64 | WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE), |
| 65 | adev->mc.vram_start >> 24); |
| 66 | WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP), |
| 67 | adev->mc.vram_end >> 24); |
| 68 | } |
| 69 | |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 70 | /* Disable AGP. */ |
| 71 | WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BASE), 0); |
| 72 | WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_TOP), 0); |
| 73 | WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_AGP_BOT), 0xFFFFFFFF); |
| 74 | |
| 75 | /* GART Enable. */ |
| 76 | |
| 77 | /* Setup TLB control */ |
| 78 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL)); |
| 79 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); |
| 80 | tmp = REG_SET_FIELD(tmp, |
| 81 | MC_VM_MX_L1_TLB_CNTL, |
| 82 | SYSTEM_ACCESS_MODE, |
| 83 | 3); |
| 84 | tmp = REG_SET_FIELD(tmp, |
| 85 | MC_VM_MX_L1_TLB_CNTL, |
| 86 | ENABLE_ADVANCED_DRIVER_MODEL, |
| 87 | 1); |
| 88 | tmp = REG_SET_FIELD(tmp, |
| 89 | MC_VM_MX_L1_TLB_CNTL, |
| 90 | SYSTEM_APERTURE_UNMAPPED_ACCESS, |
| 91 | 0); |
| 92 | tmp = REG_SET_FIELD(tmp, |
| 93 | MC_VM_MX_L1_TLB_CNTL, |
| 94 | ECO_BITS, |
| 95 | 0); |
| 96 | tmp = REG_SET_FIELD(tmp, |
| 97 | MC_VM_MX_L1_TLB_CNTL, |
| 98 | MTYPE, |
| 99 | MTYPE_UC);/* XXX for emulation. */ |
| 100 | tmp = REG_SET_FIELD(tmp, |
| 101 | MC_VM_MX_L1_TLB_CNTL, |
| 102 | ATC_EN, |
| 103 | 1); |
| 104 | WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); |
| 105 | |
| 106 | /* Setup L2 cache */ |
| 107 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL)); |
| 108 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); |
| 109 | tmp = REG_SET_FIELD(tmp, |
| 110 | VM_L2_CNTL, |
| 111 | ENABLE_L2_FRAGMENT_PROCESSING, |
| 112 | 0); |
| 113 | tmp = REG_SET_FIELD(tmp, |
| 114 | VM_L2_CNTL, |
| 115 | L2_PDE0_CACHE_TAG_GENERATION_MODE, |
| 116 | 0);/* XXX for emulation, Refer to closed source code.*/ |
| 117 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); |
| 118 | tmp = REG_SET_FIELD(tmp, |
| 119 | VM_L2_CNTL, |
| 120 | CONTEXT1_IDENTITY_ACCESS_MODE, |
| 121 | 1); |
| 122 | tmp = REG_SET_FIELD(tmp, |
| 123 | VM_L2_CNTL, |
| 124 | IDENTITY_MODE_FRAGMENT_SIZE, |
| 125 | 0); |
| 126 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp); |
| 127 | |
| 128 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2)); |
| 129 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); |
| 130 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); |
| 131 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL2), tmp); |
| 132 | |
| 133 | tmp = mmVM_L2_CNTL3_DEFAULT; |
| 134 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), tmp); |
| 135 | |
| 136 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4)); |
| 137 | tmp = REG_SET_FIELD(tmp, |
| 138 | VM_L2_CNTL4, |
| 139 | VMC_TAP_PDE_REQUEST_PHYSICAL, |
| 140 | 0); |
| 141 | tmp = REG_SET_FIELD(tmp, |
| 142 | VM_L2_CNTL4, |
| 143 | VMC_TAP_PTE_REQUEST_PHYSICAL, |
| 144 | 0); |
| 145 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL4), tmp); |
| 146 | |
| 147 | /* setup context0 */ |
| 148 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 149 | mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32), |
| 150 | (u32)(adev->mc.gtt_start >> 12)); |
| 151 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 152 | mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32), |
| 153 | (u32)(adev->mc.gtt_start >> 44)); |
| 154 | |
| 155 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 156 | mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32), |
| 157 | (u32)(adev->mc.gtt_end >> 12)); |
| 158 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 159 | mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32), |
| 160 | (u32)(adev->mc.gtt_end >> 44)); |
| 161 | |
| 162 | BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); |
| 163 | value = adev->gart.table_addr - adev->mc.vram_start |
| 164 | + adev->vm_manager.vram_base_offset; |
| 165 | value &= 0x0000FFFFFFFFF000ULL; |
| 166 | value |= 0x1; /*valid bit*/ |
| 167 | |
| 168 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 169 | mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32), |
| 170 | (u32)value); |
| 171 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 172 | mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32), |
| 173 | (u32)(value >> 32)); |
| 174 | |
| 175 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 176 | mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32), |
| 177 | (u32)(adev->dummy_page.addr >> 12)); |
| 178 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 179 | mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32), |
Alex Xie | 60508d3 | 2017-03-30 13:30:00 -0400 | [diff] [blame] | 180 | (u32)((u64)adev->dummy_page.addr >> 44)); |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 181 | |
| 182 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2)); |
| 183 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, |
| 184 | ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, |
| 185 | 1); |
| 186 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL2), tmp); |
| 187 | |
| 188 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL)); |
| 189 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); |
| 190 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); |
| 191 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL), tmp); |
| 192 | |
| 193 | /* Disable identity aperture.*/ |
| 194 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 195 | mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32), 0XFFFFFFFF); |
| 196 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 197 | mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32), 0x0000000F); |
| 198 | |
| 199 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 200 | mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32), 0); |
| 201 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 202 | mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32), 0); |
| 203 | |
| 204 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 205 | mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32), 0); |
| 206 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 207 | mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0); |
| 208 | |
| 209 | for (i = 0; i <= 14; i++) { |
| 210 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i); |
| 211 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); |
Chunming Zhou | 4fb1cf3 | 2017-03-23 17:38:34 +0800 | [diff] [blame] | 212 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, |
| 213 | adev->vm_manager.num_level); |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 214 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 215 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 216 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 217 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 218 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 219 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 220 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 221 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 222 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 223 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 224 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 225 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 226 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 227 | EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
| 228 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
| 229 | PAGE_TABLE_BLOCK_SIZE, |
Zhang, Jerry | 36b32a6 | 2017-03-29 16:08:32 +0800 | [diff] [blame] | 230 | adev->vm_manager.block_size - 9); |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 231 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i, tmp); |
| 232 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32) + i*2, 0); |
| 233 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32) + i*2, 0); |
| 234 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32) + i*2, |
Felix Kuehling | 22770e5 | 2017-03-28 20:24:53 -0400 | [diff] [blame] | 235 | lower_32_bits(adev->vm_manager.max_pfn - 1)); |
| 236 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2, |
| 237 | upper_32_bits(adev->vm_manager.max_pfn - 1)); |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 238 | } |
| 239 | |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) |
| 245 | { |
| 246 | u32 tmp; |
| 247 | u32 i; |
| 248 | |
| 249 | /* Disable all tables */ |
| 250 | for (i = 0; i < 16; i++) |
| 251 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL) + i, 0); |
| 252 | |
| 253 | /* Setup TLB control */ |
| 254 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL)); |
| 255 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); |
| 256 | tmp = REG_SET_FIELD(tmp, |
| 257 | MC_VM_MX_L1_TLB_CNTL, |
| 258 | ENABLE_ADVANCED_DRIVER_MODEL, |
| 259 | 0); |
| 260 | WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_MX_L1_TLB_CNTL), tmp); |
| 261 | |
| 262 | /* Setup L2 cache */ |
| 263 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL)); |
| 264 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); |
| 265 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL), tmp); |
| 266 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_CNTL3), 0); |
| 267 | } |
| 268 | |
| 269 | /** |
| 270 | * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling |
| 271 | * |
| 272 | * @adev: amdgpu_device pointer |
| 273 | * @value: true redirects VM faults to the default page |
| 274 | */ |
| 275 | void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, |
| 276 | bool value) |
| 277 | { |
| 278 | u32 tmp; |
| 279 | tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL)); |
| 280 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 281 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 282 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 283 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 284 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 285 | PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 286 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 287 | PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 288 | tmp = REG_SET_FIELD(tmp, |
| 289 | VM_L2_PROTECTION_FAULT_CNTL, |
| 290 | TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, |
| 291 | value); |
| 292 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 293 | NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 294 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 295 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 296 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 297 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 298 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 299 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 300 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 301 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 302 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
| 303 | EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
| 304 | WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp); |
| 305 | } |
| 306 | |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 307 | static int gfxhub_v1_0_early_init(void *handle) |
| 308 | { |
| 309 | return 0; |
| 310 | } |
| 311 | |
| 312 | static int gfxhub_v1_0_late_init(void *handle) |
| 313 | { |
| 314 | return 0; |
| 315 | } |
| 316 | |
| 317 | static int gfxhub_v1_0_sw_init(void *handle) |
| 318 | { |
| 319 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 320 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; |
| 321 | |
| 322 | hub->ctx0_ptb_addr_lo32 = |
| 323 | SOC15_REG_OFFSET(GC, 0, |
| 324 | mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); |
| 325 | hub->ctx0_ptb_addr_hi32 = |
| 326 | SOC15_REG_OFFSET(GC, 0, |
| 327 | mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); |
| 328 | hub->vm_inv_eng0_req = |
| 329 | SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); |
| 330 | hub->vm_inv_eng0_ack = |
| 331 | SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); |
| 332 | hub->vm_context0_cntl = |
| 333 | SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); |
| 334 | hub->vm_l2_pro_fault_status = |
| 335 | SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); |
| 336 | hub->vm_l2_pro_fault_cntl = |
| 337 | SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); |
| 338 | |
Alex Xie | e60f8db | 2017-03-09 11:36:26 -0500 | [diff] [blame] | 339 | return 0; |
| 340 | } |
| 341 | |
| 342 | static int gfxhub_v1_0_sw_fini(void *handle) |
| 343 | { |
| 344 | return 0; |
| 345 | } |
| 346 | |
| 347 | static int gfxhub_v1_0_hw_init(void *handle) |
| 348 | { |
| 349 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 350 | unsigned i; |
| 351 | |
| 352 | for (i = 0 ; i < 18; ++i) { |
| 353 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 354 | mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32) + |
| 355 | 2 * i, 0xffffffff); |
| 356 | WREG32(SOC15_REG_OFFSET(GC, 0, |
| 357 | mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32) + |
| 358 | 2 * i, 0x1f); |
| 359 | } |
| 360 | |
| 361 | return 0; |
| 362 | } |
| 363 | |
| 364 | static int gfxhub_v1_0_hw_fini(void *handle) |
| 365 | { |
| 366 | return 0; |
| 367 | } |
| 368 | |
| 369 | static int gfxhub_v1_0_suspend(void *handle) |
| 370 | { |
| 371 | return 0; |
| 372 | } |
| 373 | |
| 374 | static int gfxhub_v1_0_resume(void *handle) |
| 375 | { |
| 376 | return 0; |
| 377 | } |
| 378 | |
| 379 | static bool gfxhub_v1_0_is_idle(void *handle) |
| 380 | { |
| 381 | return true; |
| 382 | } |
| 383 | |
| 384 | static int gfxhub_v1_0_wait_for_idle(void *handle) |
| 385 | { |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | static int gfxhub_v1_0_soft_reset(void *handle) |
| 390 | { |
| 391 | return 0; |
| 392 | } |
| 393 | |
| 394 | static int gfxhub_v1_0_set_clockgating_state(void *handle, |
| 395 | enum amd_clockgating_state state) |
| 396 | { |
| 397 | return 0; |
| 398 | } |
| 399 | |
| 400 | static int gfxhub_v1_0_set_powergating_state(void *handle, |
| 401 | enum amd_powergating_state state) |
| 402 | { |
| 403 | return 0; |
| 404 | } |
| 405 | |
| 406 | const struct amd_ip_funcs gfxhub_v1_0_ip_funcs = { |
| 407 | .name = "gfxhub_v1_0", |
| 408 | .early_init = gfxhub_v1_0_early_init, |
| 409 | .late_init = gfxhub_v1_0_late_init, |
| 410 | .sw_init = gfxhub_v1_0_sw_init, |
| 411 | .sw_fini = gfxhub_v1_0_sw_fini, |
| 412 | .hw_init = gfxhub_v1_0_hw_init, |
| 413 | .hw_fini = gfxhub_v1_0_hw_fini, |
| 414 | .suspend = gfxhub_v1_0_suspend, |
| 415 | .resume = gfxhub_v1_0_resume, |
| 416 | .is_idle = gfxhub_v1_0_is_idle, |
| 417 | .wait_for_idle = gfxhub_v1_0_wait_for_idle, |
| 418 | .soft_reset = gfxhub_v1_0_soft_reset, |
| 419 | .set_clockgating_state = gfxhub_v1_0_set_clockgating_state, |
| 420 | .set_powergating_state = gfxhub_v1_0_set_powergating_state, |
| 421 | }; |
| 422 | |
| 423 | const struct amdgpu_ip_block_version gfxhub_v1_0_ip_block = |
| 424 | { |
| 425 | .type = AMD_IP_BLOCK_TYPE_GFXHUB, |
| 426 | .major = 1, |
| 427 | .minor = 0, |
| 428 | .rev = 0, |
| 429 | .funcs = &gfxhub_v1_0_ip_funcs, |
| 430 | }; |