Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2010 Juergen Beisert, Pengutronix |
| 3 | * |
| 4 | * This code is based on: |
| 5 | * Author: Vitaly Wool <vital@embeddedalley.com> |
| 6 | * |
| 7 | * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
| 8 | * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License |
| 12 | * as published by the Free Software Foundation; either version 2 |
| 13 | * of the License, or (at your option) any later version. |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | */ |
| 19 | |
| 20 | #define DRIVER_NAME "mxsfb" |
| 21 | |
| 22 | /** |
| 23 | * @file |
| 24 | * @brief LCDIF driver for i.MX23 and i.MX28 |
| 25 | * |
| 26 | * The LCDIF support four modes of operation |
| 27 | * - MPU interface (to drive smart displays) -> not supported yet |
| 28 | * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet |
| 29 | * - Dotclock interface (to drive LC displays with RGB data and sync signals) |
| 30 | * - DVI (to drive ITU-R BT656) -> not supported yet |
| 31 | * |
| 32 | * This driver depends on a correct setup of the pins used for this purpose |
| 33 | * (platform specific). |
| 34 | * |
| 35 | * For the developer: Don't forget to set the data bus width to the display |
| 36 | * in the imx_fb_videomode structure. You will else end up with ugly colours. |
| 37 | * If you fight against jitter you can vary the clock delay. This is a feature |
| 38 | * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give |
| 39 | * the required value in the imx_fb_videomode structure. |
| 40 | */ |
| 41 | |
Axel Lin | 3689367 | 2011-09-01 08:11:59 +0800 | [diff] [blame] | 42 | #include <linux/module.h> |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 43 | #include <linux/kernel.h> |
| 44 | #include <linux/platform_device.h> |
| 45 | #include <linux/clk.h> |
| 46 | #include <linux/dma-mapping.h> |
| 47 | #include <linux/io.h> |
Shawn Guo | fe233b9 | 2012-05-06 23:01:41 +0800 | [diff] [blame] | 48 | #include <linux/pinctrl/consumer.h> |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 49 | #include <mach/mxsfb.h> |
| 50 | |
| 51 | #define REG_SET 4 |
| 52 | #define REG_CLR 8 |
| 53 | |
| 54 | #define LCDC_CTRL 0x00 |
| 55 | #define LCDC_CTRL1 0x10 |
| 56 | #define LCDC_V4_CTRL2 0x20 |
| 57 | #define LCDC_V3_TRANSFER_COUNT 0x20 |
| 58 | #define LCDC_V4_TRANSFER_COUNT 0x30 |
| 59 | #define LCDC_V4_CUR_BUF 0x40 |
| 60 | #define LCDC_V4_NEXT_BUF 0x50 |
| 61 | #define LCDC_V3_CUR_BUF 0x30 |
| 62 | #define LCDC_V3_NEXT_BUF 0x40 |
| 63 | #define LCDC_TIMING 0x60 |
| 64 | #define LCDC_VDCTRL0 0x70 |
| 65 | #define LCDC_VDCTRL1 0x80 |
| 66 | #define LCDC_VDCTRL2 0x90 |
| 67 | #define LCDC_VDCTRL3 0xa0 |
| 68 | #define LCDC_VDCTRL4 0xb0 |
| 69 | #define LCDC_DVICTRL0 0xc0 |
| 70 | #define LCDC_DVICTRL1 0xd0 |
| 71 | #define LCDC_DVICTRL2 0xe0 |
| 72 | #define LCDC_DVICTRL3 0xf0 |
| 73 | #define LCDC_DVICTRL4 0x100 |
| 74 | #define LCDC_V4_DATA 0x180 |
| 75 | #define LCDC_V3_DATA 0x1b0 |
| 76 | #define LCDC_V4_DEBUG0 0x1d0 |
| 77 | #define LCDC_V3_DEBUG0 0x1f0 |
| 78 | |
| 79 | #define CTRL_SFTRST (1 << 31) |
| 80 | #define CTRL_CLKGATE (1 << 30) |
| 81 | #define CTRL_BYPASS_COUNT (1 << 19) |
| 82 | #define CTRL_VSYNC_MODE (1 << 18) |
| 83 | #define CTRL_DOTCLK_MODE (1 << 17) |
| 84 | #define CTRL_DATA_SELECT (1 << 16) |
| 85 | #define CTRL_SET_BUS_WIDTH(x) (((x) & 0x3) << 10) |
| 86 | #define CTRL_GET_BUS_WIDTH(x) (((x) >> 10) & 0x3) |
| 87 | #define CTRL_SET_WORD_LENGTH(x) (((x) & 0x3) << 8) |
| 88 | #define CTRL_GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) |
| 89 | #define CTRL_MASTER (1 << 5) |
| 90 | #define CTRL_DF16 (1 << 3) |
| 91 | #define CTRL_DF18 (1 << 2) |
| 92 | #define CTRL_DF24 (1 << 1) |
| 93 | #define CTRL_RUN (1 << 0) |
| 94 | |
| 95 | #define CTRL1_FIFO_CLEAR (1 << 21) |
| 96 | #define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) |
| 97 | #define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) |
| 98 | |
| 99 | #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16) |
| 100 | #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff) |
| 101 | #define TRANSFER_COUNT_SET_HCOUNT(x) ((x) & 0xffff) |
| 102 | #define TRANSFER_COUNT_GET_HCOUNT(x) ((x) & 0xffff) |
| 103 | |
| 104 | |
| 105 | #define VDCTRL0_ENABLE_PRESENT (1 << 28) |
| 106 | #define VDCTRL0_VSYNC_ACT_HIGH (1 << 27) |
| 107 | #define VDCTRL0_HSYNC_ACT_HIGH (1 << 26) |
| 108 | #define VDCTRL0_DOTCLK_ACT_FAILING (1 << 25) |
| 109 | #define VDCTRL0_ENABLE_ACT_HIGH (1 << 24) |
| 110 | #define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) |
| 111 | #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) |
| 112 | #define VDCTRL0_HALF_LINE (1 << 19) |
| 113 | #define VDCTRL0_HALF_LINE_MODE (1 << 18) |
| 114 | #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) |
| 115 | #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) |
| 116 | |
| 117 | #define VDCTRL2_SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) |
| 118 | #define VDCTRL2_GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) |
| 119 | |
| 120 | #define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) |
| 121 | #define VDCTRL3_VSYNC_ONLY (1 << 28) |
| 122 | #define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) |
| 123 | #define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) |
| 124 | #define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) |
| 125 | #define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) |
| 126 | |
| 127 | #define VDCTRL4_SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* v4 only */ |
| 128 | #define VDCTRL4_GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* v4 only */ |
| 129 | #define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) |
| 130 | #define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) |
| 131 | |
| 132 | #define DEBUG0_HSYNC (1 < 26) |
| 133 | #define DEBUG0_VSYNC (1 < 25) |
| 134 | |
| 135 | #define MIN_XRES 120 |
| 136 | #define MIN_YRES 120 |
| 137 | |
| 138 | #define RED 0 |
| 139 | #define GREEN 1 |
| 140 | #define BLUE 2 |
| 141 | #define TRANSP 3 |
| 142 | |
| 143 | enum mxsfb_devtype { |
| 144 | MXSFB_V3, |
| 145 | MXSFB_V4, |
| 146 | }; |
| 147 | |
| 148 | /* CPU dependent register offsets */ |
| 149 | struct mxsfb_devdata { |
| 150 | unsigned transfer_count; |
| 151 | unsigned cur_buf; |
| 152 | unsigned next_buf; |
| 153 | unsigned debug0; |
| 154 | unsigned hs_wdth_mask; |
| 155 | unsigned hs_wdth_shift; |
| 156 | unsigned ipversion; |
| 157 | }; |
| 158 | |
| 159 | struct mxsfb_info { |
| 160 | struct fb_info fb_info; |
| 161 | struct platform_device *pdev; |
| 162 | struct clk *clk; |
| 163 | void __iomem *base; /* registers */ |
| 164 | unsigned allocated_size; |
| 165 | int enabled; |
| 166 | unsigned ld_intf_width; |
| 167 | unsigned dotclk_delay; |
| 168 | const struct mxsfb_devdata *devdata; |
| 169 | int mapped; |
| 170 | }; |
| 171 | |
| 172 | #define mxsfb_is_v3(host) (host->devdata->ipversion == 3) |
| 173 | #define mxsfb_is_v4(host) (host->devdata->ipversion == 4) |
| 174 | |
| 175 | static const struct mxsfb_devdata mxsfb_devdata[] = { |
| 176 | [MXSFB_V3] = { |
| 177 | .transfer_count = LCDC_V3_TRANSFER_COUNT, |
| 178 | .cur_buf = LCDC_V3_CUR_BUF, |
| 179 | .next_buf = LCDC_V3_NEXT_BUF, |
| 180 | .debug0 = LCDC_V3_DEBUG0, |
| 181 | .hs_wdth_mask = 0xff, |
| 182 | .hs_wdth_shift = 24, |
| 183 | .ipversion = 3, |
| 184 | }, |
| 185 | [MXSFB_V4] = { |
| 186 | .transfer_count = LCDC_V4_TRANSFER_COUNT, |
| 187 | .cur_buf = LCDC_V4_CUR_BUF, |
| 188 | .next_buf = LCDC_V4_NEXT_BUF, |
| 189 | .debug0 = LCDC_V4_DEBUG0, |
| 190 | .hs_wdth_mask = 0x3fff, |
| 191 | .hs_wdth_shift = 18, |
| 192 | .ipversion = 4, |
| 193 | }, |
| 194 | }; |
| 195 | |
| 196 | #define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info)) |
| 197 | |
| 198 | /* mask and shift depends on architecture */ |
| 199 | static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val) |
| 200 | { |
| 201 | return (val & host->devdata->hs_wdth_mask) << |
| 202 | host->devdata->hs_wdth_shift; |
| 203 | } |
| 204 | |
| 205 | static inline u32 get_hsync_pulse_width(struct mxsfb_info *host, unsigned val) |
| 206 | { |
| 207 | return (val >> host->devdata->hs_wdth_shift) & |
| 208 | host->devdata->hs_wdth_mask; |
| 209 | } |
| 210 | |
| 211 | static const struct fb_bitfield def_rgb565[] = { |
| 212 | [RED] = { |
| 213 | .offset = 11, |
| 214 | .length = 5, |
| 215 | }, |
| 216 | [GREEN] = { |
| 217 | .offset = 5, |
| 218 | .length = 6, |
| 219 | }, |
| 220 | [BLUE] = { |
| 221 | .offset = 0, |
| 222 | .length = 5, |
| 223 | }, |
| 224 | [TRANSP] = { /* no support for transparency */ |
| 225 | .length = 0, |
| 226 | } |
| 227 | }; |
| 228 | |
| 229 | static const struct fb_bitfield def_rgb666[] = { |
| 230 | [RED] = { |
| 231 | .offset = 16, |
| 232 | .length = 6, |
| 233 | }, |
| 234 | [GREEN] = { |
| 235 | .offset = 8, |
| 236 | .length = 6, |
| 237 | }, |
| 238 | [BLUE] = { |
| 239 | .offset = 0, |
| 240 | .length = 6, |
| 241 | }, |
| 242 | [TRANSP] = { /* no support for transparency */ |
| 243 | .length = 0, |
| 244 | } |
| 245 | }; |
| 246 | |
| 247 | static const struct fb_bitfield def_rgb888[] = { |
| 248 | [RED] = { |
| 249 | .offset = 16, |
| 250 | .length = 8, |
| 251 | }, |
| 252 | [GREEN] = { |
| 253 | .offset = 8, |
| 254 | .length = 8, |
| 255 | }, |
| 256 | [BLUE] = { |
| 257 | .offset = 0, |
| 258 | .length = 8, |
| 259 | }, |
| 260 | [TRANSP] = { /* no support for transparency */ |
| 261 | .length = 0, |
| 262 | } |
| 263 | }; |
| 264 | |
| 265 | static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf) |
| 266 | { |
| 267 | chan &= 0xffff; |
| 268 | chan >>= 16 - bf->length; |
| 269 | return chan << bf->offset; |
| 270 | } |
| 271 | |
| 272 | static int mxsfb_check_var(struct fb_var_screeninfo *var, |
| 273 | struct fb_info *fb_info) |
| 274 | { |
| 275 | struct mxsfb_info *host = to_imxfb_host(fb_info); |
| 276 | const struct fb_bitfield *rgb = NULL; |
| 277 | |
| 278 | if (var->xres < MIN_XRES) |
| 279 | var->xres = MIN_XRES; |
| 280 | if (var->yres < MIN_YRES) |
| 281 | var->yres = MIN_YRES; |
| 282 | |
| 283 | var->xres_virtual = var->xres; |
| 284 | |
| 285 | var->yres_virtual = var->yres; |
| 286 | |
| 287 | switch (var->bits_per_pixel) { |
| 288 | case 16: |
| 289 | /* always expect RGB 565 */ |
| 290 | rgb = def_rgb565; |
| 291 | break; |
| 292 | case 32: |
| 293 | switch (host->ld_intf_width) { |
| 294 | case STMLCDIF_8BIT: |
| 295 | pr_debug("Unsupported LCD bus width mapping\n"); |
| 296 | break; |
| 297 | case STMLCDIF_16BIT: |
| 298 | case STMLCDIF_18BIT: |
| 299 | /* 24 bit to 18 bit mapping */ |
| 300 | rgb = def_rgb666; |
| 301 | break; |
| 302 | case STMLCDIF_24BIT: |
| 303 | /* real 24 bit */ |
| 304 | rgb = def_rgb888; |
| 305 | break; |
| 306 | } |
| 307 | break; |
| 308 | default: |
| 309 | pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel); |
| 310 | return -EINVAL; |
| 311 | } |
| 312 | |
| 313 | /* |
| 314 | * Copy the RGB parameters for this display |
| 315 | * from the machine specific parameters. |
| 316 | */ |
| 317 | var->red = rgb[RED]; |
| 318 | var->green = rgb[GREEN]; |
| 319 | var->blue = rgb[BLUE]; |
| 320 | var->transp = rgb[TRANSP]; |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static void mxsfb_enable_controller(struct fb_info *fb_info) |
| 326 | { |
| 327 | struct mxsfb_info *host = to_imxfb_host(fb_info); |
| 328 | u32 reg; |
| 329 | |
| 330 | dev_dbg(&host->pdev->dev, "%s\n", __func__); |
| 331 | |
Shawn Guo | ca4c22d3 | 2011-12-20 14:12:54 +0800 | [diff] [blame] | 332 | clk_prepare_enable(host->clk); |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 333 | clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U); |
| 334 | |
| 335 | /* if it was disabled, re-enable the mode again */ |
| 336 | writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); |
| 337 | |
| 338 | /* enable the SYNC signals first, then the DMA engine */ |
| 339 | reg = readl(host->base + LCDC_VDCTRL4); |
| 340 | reg |= VDCTRL4_SYNC_SIGNALS_ON; |
| 341 | writel(reg, host->base + LCDC_VDCTRL4); |
| 342 | |
| 343 | writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET); |
| 344 | |
| 345 | host->enabled = 1; |
| 346 | } |
| 347 | |
| 348 | static void mxsfb_disable_controller(struct fb_info *fb_info) |
| 349 | { |
| 350 | struct mxsfb_info *host = to_imxfb_host(fb_info); |
| 351 | unsigned loop; |
| 352 | u32 reg; |
| 353 | |
| 354 | dev_dbg(&host->pdev->dev, "%s\n", __func__); |
| 355 | |
| 356 | /* |
| 357 | * Even if we disable the controller here, it will still continue |
| 358 | * until its FIFOs are running out of data |
| 359 | */ |
| 360 | writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_CLR); |
| 361 | |
| 362 | loop = 1000; |
| 363 | while (loop) { |
| 364 | reg = readl(host->base + LCDC_CTRL); |
| 365 | if (!(reg & CTRL_RUN)) |
| 366 | break; |
| 367 | loop--; |
| 368 | } |
| 369 | |
| 370 | writel(VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4 + REG_CLR); |
| 371 | |
Shawn Guo | ca4c22d3 | 2011-12-20 14:12:54 +0800 | [diff] [blame] | 372 | clk_disable_unprepare(host->clk); |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 373 | |
| 374 | host->enabled = 0; |
| 375 | } |
| 376 | |
| 377 | static int mxsfb_set_par(struct fb_info *fb_info) |
| 378 | { |
| 379 | struct mxsfb_info *host = to_imxfb_host(fb_info); |
| 380 | u32 ctrl, vdctrl0, vdctrl4; |
| 381 | int line_size, fb_size; |
| 382 | int reenable = 0; |
| 383 | |
| 384 | line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3); |
| 385 | fb_size = fb_info->var.yres_virtual * line_size; |
| 386 | |
| 387 | if (fb_size > fb_info->fix.smem_len) |
| 388 | return -ENOMEM; |
| 389 | |
| 390 | fb_info->fix.line_length = line_size; |
| 391 | |
| 392 | /* |
| 393 | * It seems, you can't re-program the controller if it is still running. |
| 394 | * This may lead into shifted pictures (FIFO issue?). |
| 395 | * So, first stop the controller and drain its FIFOs |
| 396 | */ |
| 397 | if (host->enabled) { |
| 398 | reenable = 1; |
| 399 | mxsfb_disable_controller(fb_info); |
| 400 | } |
| 401 | |
| 402 | /* clear the FIFOs */ |
| 403 | writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); |
| 404 | |
| 405 | ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER | |
Justin P. Mattock | 6eab04a | 2011-04-08 19:49:08 -0700 | [diff] [blame] | 406 | CTRL_SET_BUS_WIDTH(host->ld_intf_width); |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 407 | |
| 408 | switch (fb_info->var.bits_per_pixel) { |
| 409 | case 16: |
| 410 | dev_dbg(&host->pdev->dev, "Setting up RGB565 mode\n"); |
| 411 | ctrl |= CTRL_SET_WORD_LENGTH(0); |
| 412 | writel(CTRL1_SET_BYTE_PACKAGING(0xf), host->base + LCDC_CTRL1); |
| 413 | break; |
| 414 | case 32: |
| 415 | dev_dbg(&host->pdev->dev, "Setting up RGB888/666 mode\n"); |
| 416 | ctrl |= CTRL_SET_WORD_LENGTH(3); |
| 417 | switch (host->ld_intf_width) { |
| 418 | case STMLCDIF_8BIT: |
| 419 | dev_dbg(&host->pdev->dev, |
| 420 | "Unsupported LCD bus width mapping\n"); |
| 421 | return -EINVAL; |
| 422 | case STMLCDIF_16BIT: |
| 423 | case STMLCDIF_18BIT: |
| 424 | /* 24 bit to 18 bit mapping */ |
| 425 | ctrl |= CTRL_DF24; /* ignore the upper 2 bits in |
| 426 | * each colour component |
| 427 | */ |
| 428 | break; |
| 429 | case STMLCDIF_24BIT: |
| 430 | /* real 24 bit */ |
| 431 | break; |
| 432 | } |
| 433 | /* do not use packed pixels = one pixel per word instead */ |
| 434 | writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1); |
| 435 | break; |
| 436 | default: |
| 437 | dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n", |
| 438 | fb_info->var.bits_per_pixel); |
| 439 | return -EINVAL; |
| 440 | } |
| 441 | |
| 442 | writel(ctrl, host->base + LCDC_CTRL); |
| 443 | |
| 444 | writel(TRANSFER_COUNT_SET_VCOUNT(fb_info->var.yres) | |
| 445 | TRANSFER_COUNT_SET_HCOUNT(fb_info->var.xres), |
| 446 | host->base + host->devdata->transfer_count); |
| 447 | |
| 448 | vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ |
| 449 | VDCTRL0_VSYNC_PERIOD_UNIT | |
| 450 | VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | |
| 451 | VDCTRL0_SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len); |
| 452 | if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT) |
| 453 | vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH; |
| 454 | if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT) |
| 455 | vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH; |
| 456 | if (fb_info->var.sync & FB_SYNC_DATA_ENABLE_HIGH_ACT) |
| 457 | vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH; |
| 458 | if (fb_info->var.sync & FB_SYNC_DOTCLK_FAILING_ACT) |
| 459 | vdctrl0 |= VDCTRL0_DOTCLK_ACT_FAILING; |
| 460 | |
| 461 | writel(vdctrl0, host->base + LCDC_VDCTRL0); |
| 462 | |
| 463 | /* frame length in lines */ |
| 464 | writel(fb_info->var.upper_margin + fb_info->var.vsync_len + |
| 465 | fb_info->var.lower_margin + fb_info->var.yres, |
| 466 | host->base + LCDC_VDCTRL1); |
| 467 | |
| 468 | /* line length in units of clocks or pixels */ |
| 469 | writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) | |
| 470 | VDCTRL2_SET_HSYNC_PERIOD(fb_info->var.left_margin + |
| 471 | fb_info->var.hsync_len + fb_info->var.right_margin + |
| 472 | fb_info->var.xres), |
| 473 | host->base + LCDC_VDCTRL2); |
| 474 | |
| 475 | writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin + |
| 476 | fb_info->var.hsync_len) | |
| 477 | SET_VERT_WAIT_CNT(fb_info->var.upper_margin + |
| 478 | fb_info->var.vsync_len), |
| 479 | host->base + LCDC_VDCTRL3); |
| 480 | |
| 481 | vdctrl4 = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres); |
| 482 | if (mxsfb_is_v4(host)) |
| 483 | vdctrl4 |= VDCTRL4_SET_DOTCLK_DLY(host->dotclk_delay); |
| 484 | writel(vdctrl4, host->base + LCDC_VDCTRL4); |
| 485 | |
| 486 | writel(fb_info->fix.smem_start + |
| 487 | fb_info->fix.line_length * fb_info->var.yoffset, |
| 488 | host->base + host->devdata->next_buf); |
| 489 | |
| 490 | if (reenable) |
| 491 | mxsfb_enable_controller(fb_info); |
| 492 | |
| 493 | return 0; |
| 494 | } |
| 495 | |
| 496 | static int mxsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
| 497 | u_int transp, struct fb_info *fb_info) |
| 498 | { |
| 499 | unsigned int val; |
| 500 | int ret = -EINVAL; |
| 501 | |
| 502 | /* |
| 503 | * If greyscale is true, then we convert the RGB value |
| 504 | * to greyscale no matter what visual we are using. |
| 505 | */ |
| 506 | if (fb_info->var.grayscale) |
| 507 | red = green = blue = (19595 * red + 38470 * green + |
| 508 | 7471 * blue) >> 16; |
| 509 | |
| 510 | switch (fb_info->fix.visual) { |
| 511 | case FB_VISUAL_TRUECOLOR: |
| 512 | /* |
| 513 | * 12 or 16-bit True Colour. We encode the RGB value |
| 514 | * according to the RGB bitfield information. |
| 515 | */ |
| 516 | if (regno < 16) { |
| 517 | u32 *pal = fb_info->pseudo_palette; |
| 518 | |
| 519 | val = chan_to_field(red, &fb_info->var.red); |
| 520 | val |= chan_to_field(green, &fb_info->var.green); |
| 521 | val |= chan_to_field(blue, &fb_info->var.blue); |
| 522 | |
| 523 | pal[regno] = val; |
| 524 | ret = 0; |
| 525 | } |
| 526 | break; |
| 527 | |
| 528 | case FB_VISUAL_STATIC_PSEUDOCOLOR: |
| 529 | case FB_VISUAL_PSEUDOCOLOR: |
| 530 | break; |
| 531 | } |
| 532 | |
| 533 | return ret; |
| 534 | } |
| 535 | |
| 536 | static int mxsfb_blank(int blank, struct fb_info *fb_info) |
| 537 | { |
| 538 | struct mxsfb_info *host = to_imxfb_host(fb_info); |
| 539 | |
| 540 | switch (blank) { |
| 541 | case FB_BLANK_POWERDOWN: |
| 542 | case FB_BLANK_VSYNC_SUSPEND: |
| 543 | case FB_BLANK_HSYNC_SUSPEND: |
| 544 | case FB_BLANK_NORMAL: |
| 545 | if (host->enabled) |
| 546 | mxsfb_disable_controller(fb_info); |
| 547 | break; |
| 548 | |
| 549 | case FB_BLANK_UNBLANK: |
| 550 | if (!host->enabled) |
| 551 | mxsfb_enable_controller(fb_info); |
| 552 | break; |
| 553 | } |
| 554 | return 0; |
| 555 | } |
| 556 | |
| 557 | static int mxsfb_pan_display(struct fb_var_screeninfo *var, |
| 558 | struct fb_info *fb_info) |
| 559 | { |
| 560 | struct mxsfb_info *host = to_imxfb_host(fb_info); |
| 561 | unsigned offset; |
| 562 | |
| 563 | if (var->xoffset != 0) |
| 564 | return -EINVAL; |
| 565 | |
| 566 | offset = fb_info->fix.line_length * var->yoffset; |
| 567 | |
| 568 | /* update on next VSYNC */ |
| 569 | writel(fb_info->fix.smem_start + offset, |
| 570 | host->base + host->devdata->next_buf); |
| 571 | |
| 572 | return 0; |
| 573 | } |
| 574 | |
| 575 | static struct fb_ops mxsfb_ops = { |
| 576 | .owner = THIS_MODULE, |
| 577 | .fb_check_var = mxsfb_check_var, |
| 578 | .fb_set_par = mxsfb_set_par, |
| 579 | .fb_setcolreg = mxsfb_setcolreg, |
| 580 | .fb_blank = mxsfb_blank, |
| 581 | .fb_pan_display = mxsfb_pan_display, |
| 582 | .fb_fillrect = cfb_fillrect, |
| 583 | .fb_copyarea = cfb_copyarea, |
| 584 | .fb_imageblit = cfb_imageblit, |
| 585 | }; |
| 586 | |
| 587 | static int __devinit mxsfb_restore_mode(struct mxsfb_info *host) |
| 588 | { |
| 589 | struct fb_info *fb_info = &host->fb_info; |
| 590 | unsigned line_count; |
| 591 | unsigned period; |
| 592 | unsigned long pa, fbsize; |
| 593 | int bits_per_pixel, ofs; |
| 594 | u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl; |
| 595 | struct fb_videomode vmode; |
| 596 | |
| 597 | /* Only restore the mode when the controller is running */ |
| 598 | ctrl = readl(host->base + LCDC_CTRL); |
| 599 | if (!(ctrl & CTRL_RUN)) |
| 600 | return -EINVAL; |
| 601 | |
| 602 | vdctrl0 = readl(host->base + LCDC_VDCTRL0); |
| 603 | vdctrl2 = readl(host->base + LCDC_VDCTRL2); |
| 604 | vdctrl3 = readl(host->base + LCDC_VDCTRL3); |
| 605 | vdctrl4 = readl(host->base + LCDC_VDCTRL4); |
| 606 | |
| 607 | transfer_count = readl(host->base + host->devdata->transfer_count); |
| 608 | |
| 609 | vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count); |
| 610 | vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count); |
| 611 | |
| 612 | switch (CTRL_GET_WORD_LENGTH(ctrl)) { |
| 613 | case 0: |
| 614 | bits_per_pixel = 16; |
| 615 | break; |
| 616 | case 3: |
| 617 | bits_per_pixel = 32; |
| 618 | case 1: |
| 619 | default: |
| 620 | return -EINVAL; |
| 621 | } |
| 622 | |
| 623 | fb_info->var.bits_per_pixel = bits_per_pixel; |
| 624 | |
| 625 | vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U); |
| 626 | vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2); |
| 627 | vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len; |
| 628 | vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len - |
| 629 | vmode.left_margin - vmode.xres; |
| 630 | vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0); |
| 631 | period = readl(host->base + LCDC_VDCTRL1); |
| 632 | vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len; |
| 633 | vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres; |
| 634 | |
| 635 | vmode.vmode = FB_VMODE_NONINTERLACED; |
| 636 | |
| 637 | vmode.sync = 0; |
| 638 | if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH) |
| 639 | vmode.sync |= FB_SYNC_HOR_HIGH_ACT; |
| 640 | if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH) |
| 641 | vmode.sync |= FB_SYNC_VERT_HIGH_ACT; |
| 642 | |
| 643 | pr_debug("Reconstructed video mode:\n"); |
| 644 | pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n", |
| 645 | vmode.xres, vmode.yres, |
| 646 | vmode.hsync_len, vmode.left_margin, vmode.right_margin, |
| 647 | vmode.vsync_len, vmode.upper_margin, vmode.lower_margin); |
| 648 | pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock)); |
| 649 | |
| 650 | fb_add_videomode(&vmode, &fb_info->modelist); |
| 651 | |
| 652 | host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl); |
| 653 | host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4); |
| 654 | |
| 655 | fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3); |
| 656 | |
| 657 | pa = readl(host->base + host->devdata->cur_buf); |
| 658 | fbsize = fb_info->fix.line_length * vmode.yres; |
| 659 | if (pa < fb_info->fix.smem_start) |
| 660 | return -EINVAL; |
| 661 | if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len) |
| 662 | return -EINVAL; |
| 663 | ofs = pa - fb_info->fix.smem_start; |
| 664 | if (ofs) { |
| 665 | memmove(fb_info->screen_base, fb_info->screen_base + ofs, fbsize); |
| 666 | writel(fb_info->fix.smem_start, host->base + host->devdata->next_buf); |
| 667 | } |
| 668 | |
| 669 | line_count = fb_info->fix.smem_len / fb_info->fix.line_length; |
| 670 | fb_info->fix.ypanstep = 1; |
| 671 | |
Shawn Guo | ca4c22d3 | 2011-12-20 14:12:54 +0800 | [diff] [blame] | 672 | clk_prepare_enable(host->clk); |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 673 | host->enabled = 1; |
| 674 | |
| 675 | return 0; |
| 676 | } |
| 677 | |
| 678 | static int __devinit mxsfb_init_fbinfo(struct mxsfb_info *host) |
| 679 | { |
| 680 | struct fb_info *fb_info = &host->fb_info; |
| 681 | struct fb_var_screeninfo *var = &fb_info->var; |
| 682 | struct mxsfb_platform_data *pdata = host->pdev->dev.platform_data; |
| 683 | dma_addr_t fb_phys; |
| 684 | void *fb_virt; |
| 685 | unsigned fb_size = pdata->fb_size; |
| 686 | |
| 687 | fb_info->fbops = &mxsfb_ops; |
| 688 | fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; |
| 689 | strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id)); |
| 690 | fb_info->fix.type = FB_TYPE_PACKED_PIXELS; |
| 691 | fb_info->fix.ypanstep = 1; |
| 692 | fb_info->fix.visual = FB_VISUAL_TRUECOLOR, |
| 693 | fb_info->fix.accel = FB_ACCEL_NONE; |
| 694 | |
| 695 | var->bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16; |
| 696 | var->nonstd = 0; |
| 697 | var->activate = FB_ACTIVATE_NOW; |
| 698 | var->accel_flags = 0; |
| 699 | var->vmode = FB_VMODE_NONINTERLACED; |
| 700 | |
| 701 | host->dotclk_delay = pdata->dotclk_delay; |
| 702 | host->ld_intf_width = pdata->ld_intf_width; |
| 703 | |
| 704 | /* Memory allocation for framebuffer */ |
| 705 | if (pdata->fb_phys) { |
| 706 | if (!fb_size) |
| 707 | return -EINVAL; |
| 708 | |
| 709 | fb_phys = pdata->fb_phys; |
| 710 | |
| 711 | if (!request_mem_region(fb_phys, fb_size, host->pdev->name)) |
| 712 | return -ENOMEM; |
| 713 | |
| 714 | fb_virt = ioremap(fb_phys, fb_size); |
| 715 | if (!fb_virt) { |
| 716 | release_mem_region(fb_phys, fb_size); |
| 717 | return -ENOMEM; |
| 718 | } |
| 719 | host->mapped = 1; |
| 720 | } else { |
| 721 | if (!fb_size) |
| 722 | fb_size = SZ_2M; /* default */ |
| 723 | fb_virt = alloc_pages_exact(fb_size, GFP_DMA); |
| 724 | if (!fb_virt) |
| 725 | return -ENOMEM; |
| 726 | |
| 727 | fb_phys = virt_to_phys(fb_virt); |
| 728 | } |
| 729 | |
| 730 | fb_info->fix.smem_start = fb_phys; |
| 731 | fb_info->screen_base = fb_virt; |
| 732 | fb_info->screen_size = fb_info->fix.smem_len = fb_size; |
| 733 | |
| 734 | if (mxsfb_restore_mode(host)) |
| 735 | memset(fb_virt, 0, fb_size); |
| 736 | |
| 737 | return 0; |
| 738 | } |
| 739 | |
| 740 | static void __devexit mxsfb_free_videomem(struct mxsfb_info *host) |
| 741 | { |
| 742 | struct fb_info *fb_info = &host->fb_info; |
| 743 | |
| 744 | if (host->mapped) { |
| 745 | iounmap(fb_info->screen_base); |
| 746 | release_mem_region(fb_info->fix.smem_start, |
| 747 | fb_info->screen_size); |
| 748 | } else { |
| 749 | free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len); |
| 750 | } |
| 751 | } |
| 752 | |
| 753 | static int __devinit mxsfb_probe(struct platform_device *pdev) |
| 754 | { |
| 755 | struct mxsfb_platform_data *pdata = pdev->dev.platform_data; |
| 756 | struct resource *res; |
| 757 | struct mxsfb_info *host; |
| 758 | struct fb_info *fb_info; |
| 759 | struct fb_modelist *modelist; |
Shawn Guo | fe233b9 | 2012-05-06 23:01:41 +0800 | [diff] [blame] | 760 | struct pinctrl *pinctrl; |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 761 | int i, ret; |
| 762 | |
| 763 | if (!pdata) { |
| 764 | dev_err(&pdev->dev, "No platformdata. Giving up\n"); |
| 765 | return -ENODEV; |
| 766 | } |
| 767 | |
| 768 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 769 | if (!res) { |
| 770 | dev_err(&pdev->dev, "Cannot get memory IO resource\n"); |
| 771 | return -ENODEV; |
| 772 | } |
| 773 | |
| 774 | if (!request_mem_region(res->start, resource_size(res), pdev->name)) |
| 775 | return -EBUSY; |
| 776 | |
| 777 | fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev); |
| 778 | if (!fb_info) { |
| 779 | dev_err(&pdev->dev, "Failed to allocate fbdev\n"); |
| 780 | ret = -ENOMEM; |
| 781 | goto error_alloc_info; |
| 782 | } |
| 783 | |
| 784 | host = to_imxfb_host(fb_info); |
| 785 | |
| 786 | host->base = ioremap(res->start, resource_size(res)); |
| 787 | if (!host->base) { |
| 788 | dev_err(&pdev->dev, "ioremap failed\n"); |
| 789 | ret = -ENOMEM; |
| 790 | goto error_ioremap; |
| 791 | } |
| 792 | |
| 793 | host->pdev = pdev; |
| 794 | platform_set_drvdata(pdev, host); |
| 795 | |
| 796 | host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; |
| 797 | |
Shawn Guo | fe233b9 | 2012-05-06 23:01:41 +0800 | [diff] [blame] | 798 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
| 799 | if (IS_ERR(pinctrl)) { |
| 800 | ret = PTR_ERR(pinctrl); |
| 801 | goto error_getpin; |
| 802 | } |
| 803 | |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 804 | host->clk = clk_get(&host->pdev->dev, NULL); |
| 805 | if (IS_ERR(host->clk)) { |
| 806 | ret = PTR_ERR(host->clk); |
| 807 | goto error_getclock; |
| 808 | } |
| 809 | |
| 810 | fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); |
| 811 | if (!fb_info->pseudo_palette) { |
| 812 | ret = -ENOMEM; |
| 813 | goto error_pseudo_pallette; |
| 814 | } |
| 815 | |
| 816 | INIT_LIST_HEAD(&fb_info->modelist); |
| 817 | |
| 818 | ret = mxsfb_init_fbinfo(host); |
| 819 | if (ret != 0) |
| 820 | goto error_init_fb; |
| 821 | |
| 822 | for (i = 0; i < pdata->mode_count; i++) |
| 823 | fb_add_videomode(&pdata->mode_list[i], &fb_info->modelist); |
| 824 | |
| 825 | modelist = list_first_entry(&fb_info->modelist, |
| 826 | struct fb_modelist, list); |
| 827 | fb_videomode_to_var(&fb_info->var, &modelist->mode); |
| 828 | |
| 829 | /* init the color fields */ |
| 830 | mxsfb_check_var(&fb_info->var, fb_info); |
| 831 | |
| 832 | platform_set_drvdata(pdev, fb_info); |
| 833 | |
| 834 | ret = register_framebuffer(fb_info); |
| 835 | if (ret != 0) { |
| 836 | dev_err(&pdev->dev,"Failed to register framebuffer\n"); |
| 837 | goto error_register; |
| 838 | } |
| 839 | |
| 840 | if (!host->enabled) { |
| 841 | writel(0, host->base + LCDC_CTRL); |
| 842 | mxsfb_set_par(fb_info); |
| 843 | mxsfb_enable_controller(fb_info); |
| 844 | } |
| 845 | |
| 846 | dev_info(&pdev->dev, "initialized\n"); |
| 847 | |
| 848 | return 0; |
| 849 | |
| 850 | error_register: |
| 851 | if (host->enabled) |
Shawn Guo | ca4c22d3 | 2011-12-20 14:12:54 +0800 | [diff] [blame] | 852 | clk_disable_unprepare(host->clk); |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 853 | fb_destroy_modelist(&fb_info->modelist); |
| 854 | error_init_fb: |
| 855 | kfree(fb_info->pseudo_palette); |
| 856 | error_pseudo_pallette: |
| 857 | clk_put(host->clk); |
| 858 | error_getclock: |
Shawn Guo | fe233b9 | 2012-05-06 23:01:41 +0800 | [diff] [blame] | 859 | error_getpin: |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 860 | iounmap(host->base); |
| 861 | error_ioremap: |
| 862 | framebuffer_release(fb_info); |
| 863 | error_alloc_info: |
| 864 | release_mem_region(res->start, resource_size(res)); |
| 865 | |
| 866 | return ret; |
| 867 | } |
| 868 | |
| 869 | static int __devexit mxsfb_remove(struct platform_device *pdev) |
| 870 | { |
| 871 | struct fb_info *fb_info = platform_get_drvdata(pdev); |
| 872 | struct mxsfb_info *host = to_imxfb_host(fb_info); |
| 873 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 874 | |
| 875 | if (host->enabled) |
| 876 | mxsfb_disable_controller(fb_info); |
| 877 | |
| 878 | unregister_framebuffer(fb_info); |
| 879 | kfree(fb_info->pseudo_palette); |
| 880 | mxsfb_free_videomem(host); |
| 881 | iounmap(host->base); |
| 882 | clk_put(host->clk); |
| 883 | |
| 884 | framebuffer_release(fb_info); |
| 885 | release_mem_region(res->start, resource_size(res)); |
| 886 | |
| 887 | platform_set_drvdata(pdev, NULL); |
| 888 | |
| 889 | return 0; |
| 890 | } |
| 891 | |
| 892 | static struct platform_device_id mxsfb_devtype[] = { |
| 893 | { |
| 894 | .name = "imx23-fb", |
| 895 | .driver_data = MXSFB_V3, |
| 896 | }, { |
| 897 | .name = "imx28-fb", |
| 898 | .driver_data = MXSFB_V4, |
| 899 | }, { |
| 900 | /* sentinel */ |
| 901 | } |
| 902 | }; |
| 903 | MODULE_DEVICE_TABLE(platform, mxsfb_devtype); |
| 904 | |
| 905 | static struct platform_driver mxsfb_driver = { |
| 906 | .probe = mxsfb_probe, |
| 907 | .remove = __devexit_p(mxsfb_remove), |
| 908 | .id_table = mxsfb_devtype, |
| 909 | .driver = { |
| 910 | .name = DRIVER_NAME, |
| 911 | }, |
| 912 | }; |
| 913 | |
Marek Vasut | 396fa99 | 2011-12-19 16:37:59 +0100 | [diff] [blame] | 914 | module_platform_driver(mxsfb_driver); |
Sascha Hauer | f0a523b | 2011-01-14 15:22:31 +0100 | [diff] [blame] | 915 | |
| 916 | MODULE_DESCRIPTION("Freescale mxs framebuffer driver"); |
| 917 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
| 918 | MODULE_LICENSE("GPL"); |