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android-kvm / linux / c66c63049966a4c23dc429d2e5f4d063c8b78aeb / . / drivers / scsi / ips.c
blob: bc33d54a40112a1fd676dd4367a39105adc8900e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*****************************************************************************/
2/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 2000 IBM Corporation */
9/* Copyright (C) 2002,2003 Adaptec, Inc. */
10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions about this driver should be mailed to: */
46/* ipslinux@adaptec.com */
47/* */
48/* For system support issues, contact your local IBM Customer support. */
49/* Directions to find IBM Customer Support for each country can be found at: */
50/* http://www.ibm.com/planetwide/ */
51/* */
52/*****************************************************************************/
53
54/*****************************************************************************/
55/* Change Log */
56/* */
57/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58/* 0.99.03 - Make interrupt routine handle all completed request on the */
59/* adapter not just the first one */
60/* - Make sure passthru commands get woken up if we run out of */
61/* SCBs */
62/* - Send all of the commands on the queue at once rather than */
63/* one at a time since the card will support it. */
64/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65/* the interface to the utilities to change */
66/* - Fix error recovery code */
67/* 0.99.05 - Fix an oops when we get certain passthru commands */
68/* 1.00.00 - Initial Public Release */
69/* Functionally equivalent to 0.99.05 */
70/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71/* - Change version to 3.60 to coincide with release numbering. */
72/* 3.60.01 - Remove bogus error check in passthru routine */
73/* 3.60.02 - Make DCDB direction based on lookup table */
74/* - Only allow one DCDB command to a SCSI ID at a time */
75/* 4.00.00 - Add support for ServeRAID 4 */
76/* 4.00.01 - Add support for First Failure Data Capture */
77/* 4.00.02 - Fix problem with PT DCDB with no buffer */
78/* 4.00.03 - Add alternative passthru interface */
79/* - Add ability to flash BIOS */
80/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81/* 4.00.05 - Remove wish_block from init routine */
82/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83/* 2.3.18 and later */
84/* - Sync with other changes from the 2.3 kernels */
85/* 4.00.06 - Fix timeout with initial FFDC command */
86/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87/* 4.10.00 - Add support for ServeRAID 4M/4L */
88/* 4.10.13 - Fix for dynamic unload and proc file system */
89/* 4.20.03 - Rename version to coincide with new release schedules */
90/* Performance fixes */
91/* Fix truncation of /proc files with cat */
92/* Merge in changes through kernel 2.4.0test1ac21 */
93/* 4.20.13 - Fix some failure cases / reset code */
94/* - Hook into the reboot_notifier to flush the controller cache */
95/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97/* - Add IPSSEND Flash Support */
98/* - Set Sense Data for Unknown SCSI Command */
99/* - Use Slot Number from NVRAM Page 5 */
100/* - Restore caller's DCDB Structure */
101/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102/* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103/* - Don't release HA Lock in ips_next() until SC taken off queue */
104/* - Unregister SCSI device in ips_release() */
105/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107/* Code Clean-Up for 2.4.x kernel */
108/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110/* - Don't Issue Internal FFDC Command if there are Active Commands */
111/* - Close Window for getting too many IOCTL's active */
112/* 4.80.00 - Make ia64 Safe */
113/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114/* - Adjustments to Device Queue Depth */
115/* 4.80.14 - Take all semaphores off stack */
116/* - Clean Up New_IOCTL path */
117/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118/* - 5 second delay needed after resetting an i960 adapter */
119/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124/* 4.90.11 - Don't actually RESET unless it's physically required */
125/* - Remove unused compile options */
126/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127/* - Get rid on IOCTL_NEW_COMMAND code */
128/* - Add Extended DCDB Commands for Tape Support in 5I */
129/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130/* 5.10.15 - remove unused code (sem, macros, etc.) */
131/* 5.30.00 - use __devexit_p() */
132/* 6.00.00 - Add 6x Adapters and Battery Flash */
133/* 6.10.00 - Remove 1G Addressing Limitations */
134/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]136/* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]137/* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138/* - Fix sort order of 7k */
139/* - Remove 3 unused "inline" functions */
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]140/* 7.12.xx - Use STATIC functions wherever possible */
Jack Hammerc1a15462005-07-26 10:20:33 -0400[diff] [blame]141/* - Clean up deprecated MODULE_PARM calls */
Jack Hammera60768e2005-11-03 09:46:00 -0500[diff] [blame]142/* 7.12.05 - Remove Version Matching per IBM request */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]143/*****************************************************************************/
144
145/*
146 * Conditional Compilation directives for this driver:
147 *
148 * IPS_DEBUG - Turn on debugging info
149 *
150 * Parameters:
151 *
152 * debug:<number> - Set debug level to <number>
153 * NOTE: only works when IPS_DEBUG compile directive is used.
154 * 1 - Normal debug messages
155 * 2 - Verbose debug messages
156 * 11 - Method trace (non interrupt)
157 * 12 - Method trace (includes interrupt)
158 *
159 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
160 * nommap - Don't use memory mapped I/O
161 * ioctlsize - Initial size of the IOCTL buffer
162 */
163
164#include <asm/io.h>
165#include <asm/byteorder.h>
166#include <asm/page.h>
167#include <linux/stddef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]168#include <linux/string.h>
169#include <linux/errno.h>
170#include <linux/kernel.h>
171#include <linux/ioport.h>
172#include <linux/slab.h>
173#include <linux/delay.h>
174#include <linux/pci.h>
175#include <linux/proc_fs.h>
176#include <linux/reboot.h>
177#include <linux/interrupt.h>
178
179#include <linux/blkdev.h>
180#include <linux/types.h>
Matthias Gehre910638a2006-03-28 01:56:48 -0800[diff] [blame]181#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]182
183#include <scsi/sg.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]184#include "scsi.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]185#include <scsi/scsi_host.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]186
187#include "ips.h"
188
189#include <linux/module.h>
190
191#include <linux/stat.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]192
193#include <linux/spinlock.h>
194#include <linux/init.h>
195
196#include <linux/smp.h>
197
198#ifdef MODULE
199static char *ips = NULL;
200module_param(ips, charp, 0);
201#endif
202
203/*
204 * DRIVER_VER
205 */
Bernhard Walle8c8fdc52007-09-22 21:55:19 +0200[diff] [blame]206#define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
207#define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]208
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]209#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
be7db052005-04-17 15:26:13 -0500[diff] [blame]210 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]211 DMA_BIDIRECTIONAL : \
be7db052005-04-17 15:26:13 -0500[diff] [blame]212 scb->scsi_cmd->sc_data_direction)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]213
214#ifdef IPS_DEBUG
215#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
216#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
217#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
218#else
219#define METHOD_TRACE(s, i)
220#define DEBUG(i, s)
221#define DEBUG_VAR(i, s, v...)
222#endif
223
224/*
225 * Function prototypes
226 */
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]227static int ips_eh_abort(struct scsi_cmnd *);
228static int ips_eh_reset(struct scsi_cmnd *);
Jeff Garzikf2812332010-11-16 02:10:29 -0500[diff] [blame]229static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]230static const char *ips_info(struct Scsi_Host *);
David Howells7d12e782006-10-05 14:55:46 +0100[diff] [blame]231static irqreturn_t do_ipsintr(int, void *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]232static int ips_hainit(ips_ha_t *);
233static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
234static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
235static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
236static int ips_online(ips_ha_t *, ips_scb_t *);
237static int ips_inquiry(ips_ha_t *, ips_scb_t *);
238static int ips_rdcap(ips_ha_t *, ips_scb_t *);
239static int ips_msense(ips_ha_t *, ips_scb_t *);
240static int ips_reqsen(ips_ha_t *, ips_scb_t *);
241static int ips_deallocatescbs(ips_ha_t *, int);
242static int ips_allocatescbs(ips_ha_t *);
243static int ips_reset_copperhead(ips_ha_t *);
244static int ips_reset_copperhead_memio(ips_ha_t *);
245static int ips_reset_morpheus(ips_ha_t *);
246static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
247static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
248static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
249static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
250static int ips_isintr_copperhead(ips_ha_t *);
251static int ips_isintr_copperhead_memio(ips_ha_t *);
252static int ips_isintr_morpheus(ips_ha_t *);
253static int ips_wait(ips_ha_t *, int, int);
254static int ips_write_driver_status(ips_ha_t *, int);
255static int ips_read_adapter_status(ips_ha_t *, int);
256static int ips_read_subsystem_parameters(ips_ha_t *, int);
257static int ips_read_config(ips_ha_t *, int);
258static int ips_clear_adapter(ips_ha_t *, int);
259static int ips_readwrite_page5(ips_ha_t *, int, int);
260static int ips_init_copperhead(ips_ha_t *);
261static int ips_init_copperhead_memio(ips_ha_t *);
262static int ips_init_morpheus(ips_ha_t *);
263static int ips_isinit_copperhead(ips_ha_t *);
264static int ips_isinit_copperhead_memio(ips_ha_t *);
265static int ips_isinit_morpheus(ips_ha_t *);
266static int ips_erase_bios(ips_ha_t *);
267static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
268static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
269static int ips_erase_bios_memio(ips_ha_t *);
270static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
271static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
272static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
273static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
274static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
275static void ips_free_flash_copperhead(ips_ha_t * ha);
276static void ips_get_bios_version(ips_ha_t *, int);
277static void ips_identify_controller(ips_ha_t *);
278static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
279static void ips_enable_int_copperhead(ips_ha_t *);
280static void ips_enable_int_copperhead_memio(ips_ha_t *);
281static void ips_enable_int_morpheus(ips_ha_t *);
282static int ips_intr_copperhead(ips_ha_t *);
283static int ips_intr_morpheus(ips_ha_t *);
284static void ips_next(ips_ha_t *, int);
285static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
286static void ipsintr_done(ips_ha_t *, struct ips_scb *);
287static void ips_done(ips_ha_t *, ips_scb_t *);
288static void ips_free(ips_ha_t *);
289static void ips_init_scb(ips_ha_t *, ips_scb_t *);
290static void ips_freescb(ips_ha_t *, ips_scb_t *);
291static void ips_setup_funclist(ips_ha_t *);
292static void ips_statinit(ips_ha_t *);
293static void ips_statinit_memio(ips_ha_t *);
Arnd Bergmannf990bee2018-04-20 18:04:40 +0200[diff] [blame]294static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time64_t);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]295static void ips_ffdc_reset(ips_ha_t *, int);
296static void ips_ffdc_time(ips_ha_t *);
297static uint32_t ips_statupd_copperhead(ips_ha_t *);
298static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
299static uint32_t ips_statupd_morpheus(ips_ha_t *);
300static ips_scb_t *ips_getscb(ips_ha_t *);
301static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
Ingo Molnarac6424b2017-06-20 12:06:13 +0200[diff] [blame]302static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]303static void ips_putq_copp_tail(ips_copp_queue_t *,
304 ips_copp_wait_item_t *);
305static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
306static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
Ingo Molnarac6424b2017-06-20 12:06:13 +0200[diff] [blame]307static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *);
308static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *,
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]309 struct scsi_cmnd *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]310static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
311 ips_copp_wait_item_t *);
312static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
313
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]314static int ips_is_passthru(struct scsi_cmnd *);
315static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]316static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
317static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]318static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]319 unsigned int count);
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]320static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
321 unsigned int count);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]322
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]323static int ips_write_info(struct Scsi_Host *, char *, int);
324static int ips_show_info(struct seq_file *, struct Scsi_Host *);
325static int ips_host_info(ips_ha_t *, struct seq_file *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]326static int ips_abort_init(ips_ha_t * ha, int index);
327static int ips_init_phase2(int index);
328
329static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
330static int ips_register_scsi(int index);
331
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]332static int ips_poll_for_flush_complete(ips_ha_t * ha);
333static void ips_flush_and_reset(ips_ha_t *ha);
334
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]335/*
336 * global variables
337 */
338static const char ips_name[] = "ips";
339static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
340static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
341static unsigned int ips_next_controller;
342static unsigned int ips_num_controllers;
343static unsigned int ips_released_controllers;
344static int ips_hotplug;
345static int ips_cmd_timeout = 60;
346static int ips_reset_timeout = 60 * 5;
347static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
348static int ips_force_i2o = 1; /* Always use I2O command delivery */
349static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
350static int ips_cd_boot; /* Booting from Manager CD */
351static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
352static dma_addr_t ips_flashbusaddr;
353static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
354static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
Christoph Hellwigd0be4a7d2005-10-31 18:31:40 +0100[diff] [blame]355static struct scsi_host_template ips_driver_template = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]356 .info = ips_info,
357 .queuecommand = ips_queue,
358 .eh_abort_handler = ips_eh_abort,
359 .eh_host_reset_handler = ips_eh_reset,
360 .proc_name = "ips",
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]361 .show_info = ips_show_info,
362 .write_info = ips_write_info,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]363 .slave_configure = ips_slave_configure,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]364 .bios_param = ips_biosparam,
365 .this_id = -1,
366 .sg_tablesize = IPS_MAX_SG,
367 .cmd_per_lun = 3,
Martin K. Petersen54b2b502013-10-23 06:25:40 -0400[diff] [blame]368 .no_write_same = 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]369};
370
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]371
372/* This table describes all ServeRAID Adapters */
373static struct pci_device_id ips_pci_table[] = {
374 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
375 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
376 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
377 { 0, }
378};
379
380MODULE_DEVICE_TABLE( pci, ips_pci_table );
381
382static char ips_hot_plug_name[] = "ips";
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]383
Greg Kroah-Hartman6f039792012-12-21 13:08:55 -0800[diff] [blame]384static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
385static void ips_remove_device(struct pci_dev *pci_dev);
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]386
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]387static struct pci_driver ips_pci_driver = {
388 .name = ips_hot_plug_name,
389 .id_table = ips_pci_table,
390 .probe = ips_insert_device,
Greg Kroah-Hartman6f039792012-12-21 13:08:55 -0800[diff] [blame]391 .remove = ips_remove_device,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]392};
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]393
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]394
395/*
396 * Necessary forward function protoypes
397 */
398static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
399
400#define MAX_ADAPTER_NAME 15
401
402static char ips_adapter_name[][30] = {
403 "ServeRAID",
404 "ServeRAID II",
405 "ServeRAID on motherboard",
406 "ServeRAID on motherboard",
407 "ServeRAID 3H",
408 "ServeRAID 3L",
409 "ServeRAID 4H",
410 "ServeRAID 4M",
411 "ServeRAID 4L",
412 "ServeRAID 4Mx",
413 "ServeRAID 4Lx",
414 "ServeRAID 5i",
415 "ServeRAID 5i",
416 "ServeRAID 6M",
417 "ServeRAID 6i",
418 "ServeRAID 7t",
419 "ServeRAID 7k",
420 "ServeRAID 7M"
421};
422
423static struct notifier_block ips_notifier = {
424 ips_halt, NULL, 0
425};
426
427/*
428 * Direction table
429 */
430static char ips_command_direction[] = {
431 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
432 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
433 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
434 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
435 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
436 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
437 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
438 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
439 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
440 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
441 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
442 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
443 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
444 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
445 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
446 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
447 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
448 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
449 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
450 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
451 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
452 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
453 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
454 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
465 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
466 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
467 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
469 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
470 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
471 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
482};
483
484
485/****************************************************************************/
486/* */
487/* Routine Name: ips_setup */
488/* */
489/* Routine Description: */
490/* */
491/* setup parameters to the driver */
492/* */
493/****************************************************************************/
494static int
495ips_setup(char *ips_str)
496{
497
498 int i;
499 char *key;
500 char *value;
Colin Ian King5ece56a2019-09-06 17:45:22 +0100[diff] [blame]501 static const IPS_OPTION options[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]502 {"noi2o", &ips_force_i2o, 0},
503 {"nommap", &ips_force_memio, 0},
504 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
505 {"cdboot", &ips_cd_boot, 0},
506 {"maxcmds", &MaxLiteCmds, 32},
507 };
508
509 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
510 /* Search for value */
511 while ((key = strsep(&ips_str, ",."))) {
512 if (!*key)
513 continue;
514 value = strchr(key, ':');
515 if (value)
516 *value++ = '\0';
517 /*
518 * We now have key/value pairs.
519 * Update the variables
520 */
Tobias Klauser6391a112006-06-08 22:23:48 -0700[diff] [blame]521 for (i = 0; i < ARRAY_SIZE(options); i++) {
Rasmus Villemoes48a96872014-10-13 15:54:44 -0700[diff] [blame]522 if (strncasecmp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]523 (key, options[i].option_name,
524 strlen(options[i].option_name)) == 0) {
525 if (value)
526 *options[i].option_flag =
527 simple_strtoul(value, NULL, 0);
528 else
529 *options[i].option_flag =
530 options[i].option_value;
531 break;
532 }
533 }
534 }
535
536 return (1);
537}
538
539__setup("ips=", ips_setup);
540
541/****************************************************************************/
542/* */
543/* Routine Name: ips_detect */
544/* */
545/* Routine Description: */
546/* */
547/* Detect and initialize the driver */
548/* */
549/* NOTE: this routine is called under the io_request_lock spinlock */
550/* */
551/****************************************************************************/
552static int
Christoph Hellwigd0be4a7d2005-10-31 18:31:40 +0100[diff] [blame]553ips_detect(struct scsi_host_template * SHT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]554{
555 int i;
556
557 METHOD_TRACE("ips_detect", 1);
558
559#ifdef MODULE
560 if (ips)
561 ips_setup(ips);
562#endif
563
564 for (i = 0; i < ips_num_controllers; i++) {
565 if (ips_register_scsi(i))
566 ips_free(ips_ha[i]);
567 ips_released_controllers++;
568 }
569 ips_hotplug = 1;
570 return (ips_num_controllers);
571}
572
573/****************************************************************************/
574/* configure the function pointers to use the functions that will work */
575/* with the found version of the adapter */
576/****************************************************************************/
577static void
578ips_setup_funclist(ips_ha_t * ha)
579{
580
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]581 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]582 * Setup Functions
583 */
584 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
585 /* morpheus / marco / sebring */
586 ha->func.isintr = ips_isintr_morpheus;
587 ha->func.isinit = ips_isinit_morpheus;
588 ha->func.issue = ips_issue_i2o_memio;
589 ha->func.init = ips_init_morpheus;
590 ha->func.statupd = ips_statupd_morpheus;
591 ha->func.reset = ips_reset_morpheus;
592 ha->func.intr = ips_intr_morpheus;
593 ha->func.enableint = ips_enable_int_morpheus;
594 } else if (IPS_USE_MEMIO(ha)) {
595 /* copperhead w/MEMIO */
596 ha->func.isintr = ips_isintr_copperhead_memio;
597 ha->func.isinit = ips_isinit_copperhead_memio;
598 ha->func.init = ips_init_copperhead_memio;
599 ha->func.statupd = ips_statupd_copperhead_memio;
600 ha->func.statinit = ips_statinit_memio;
601 ha->func.reset = ips_reset_copperhead_memio;
602 ha->func.intr = ips_intr_copperhead;
603 ha->func.erasebios = ips_erase_bios_memio;
604 ha->func.programbios = ips_program_bios_memio;
605 ha->func.verifybios = ips_verify_bios_memio;
606 ha->func.enableint = ips_enable_int_copperhead_memio;
607 if (IPS_USE_I2O_DELIVER(ha))
608 ha->func.issue = ips_issue_i2o_memio;
609 else
610 ha->func.issue = ips_issue_copperhead_memio;
611 } else {
612 /* copperhead */
613 ha->func.isintr = ips_isintr_copperhead;
614 ha->func.isinit = ips_isinit_copperhead;
615 ha->func.init = ips_init_copperhead;
616 ha->func.statupd = ips_statupd_copperhead;
617 ha->func.statinit = ips_statinit;
618 ha->func.reset = ips_reset_copperhead;
619 ha->func.intr = ips_intr_copperhead;
620 ha->func.erasebios = ips_erase_bios;
621 ha->func.programbios = ips_program_bios;
622 ha->func.verifybios = ips_verify_bios;
623 ha->func.enableint = ips_enable_int_copperhead;
624
625 if (IPS_USE_I2O_DELIVER(ha))
626 ha->func.issue = ips_issue_i2o;
627 else
628 ha->func.issue = ips_issue_copperhead;
629 }
630}
631
632/****************************************************************************/
633/* */
634/* Routine Name: ips_release */
635/* */
636/* Routine Description: */
637/* */
638/* Remove a driver */
639/* */
640/****************************************************************************/
641static int
642ips_release(struct Scsi_Host *sh)
643{
644 ips_scb_t *scb;
645 ips_ha_t *ha;
646 int i;
647
648 METHOD_TRACE("ips_release", 1);
649
Matthew Wilcoxa50ee7a2007-08-15 12:57:00 -0600[diff] [blame]650 scsi_remove_host(sh);
651
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]652 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
653
654 if (i == IPS_MAX_ADAPTERS) {
655 printk(KERN_WARNING
656 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
657 BUG();
658 return (FALSE);
659 }
660
661 ha = IPS_HA(sh);
662
663 if (!ha)
664 return (FALSE);
665
666 /* flush the cache on the controller */
667 scb = &ha->scbs[ha->max_cmds - 1];
668
669 ips_init_scb(ha, scb);
670
671 scb->timeout = ips_cmd_timeout;
672 scb->cdb[0] = IPS_CMD_FLUSH;
673
674 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
675 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
676 scb->cmd.flush_cache.state = IPS_NORM_STATE;
677 scb->cmd.flush_cache.reserved = 0;
678 scb->cmd.flush_cache.reserved2 = 0;
679 scb->cmd.flush_cache.reserved3 = 0;
680 scb->cmd.flush_cache.reserved4 = 0;
681
682 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
683
684 /* send command */
685 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
686 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
687
688 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
689
690 ips_sh[i] = NULL;
691 ips_ha[i] = NULL;
692
693 /* free extra memory */
694 ips_free(ha);
695
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]696 /* free IRQ */
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]697 free_irq(ha->pcidev->irq, ha);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]698
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]699 scsi_host_put(sh);
700
701 ips_released_controllers++;
702
703 return (FALSE);
704}
705
706/****************************************************************************/
707/* */
708/* Routine Name: ips_halt */
709/* */
710/* Routine Description: */
711/* */
712/* Perform cleanup when the system reboots */
713/* */
714/****************************************************************************/
715static int
716ips_halt(struct notifier_block *nb, ulong event, void *buf)
717{
718 ips_scb_t *scb;
719 ips_ha_t *ha;
720 int i;
721
722 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
723 (event != SYS_POWER_OFF))
724 return (NOTIFY_DONE);
725
726 for (i = 0; i < ips_next_controller; i++) {
727 ha = (ips_ha_t *) ips_ha[i];
728
729 if (!ha)
730 continue;
731
732 if (!ha->active)
733 continue;
734
735 /* flush the cache on the controller */
736 scb = &ha->scbs[ha->max_cmds - 1];
737
738 ips_init_scb(ha, scb);
739
740 scb->timeout = ips_cmd_timeout;
741 scb->cdb[0] = IPS_CMD_FLUSH;
742
743 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
744 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
745 scb->cmd.flush_cache.state = IPS_NORM_STATE;
746 scb->cmd.flush_cache.reserved = 0;
747 scb->cmd.flush_cache.reserved2 = 0;
748 scb->cmd.flush_cache.reserved3 = 0;
749 scb->cmd.flush_cache.reserved4 = 0;
750
751 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
752
753 /* send command */
754 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
755 IPS_FAILURE)
756 IPS_PRINTK(KERN_WARNING, ha->pcidev,
757 "Incomplete Flush.\n");
758 else
759 IPS_PRINTK(KERN_WARNING, ha->pcidev,
760 "Flushing Complete.\n");
761 }
762
763 return (NOTIFY_OK);
764}
765
766/****************************************************************************/
767/* */
768/* Routine Name: ips_eh_abort */
769/* */
770/* Routine Description: */
771/* */
772/* Abort a command (using the new error code stuff) */
773/* Note: this routine is called under the io_request_lock */
774/****************************************************************************/
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]775int ips_eh_abort(struct scsi_cmnd *SC)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]776{
777 ips_ha_t *ha;
778 ips_copp_wait_item_t *item;
779 int ret;
Jeff Garzik 8fa728a2005-05-28 07:54:40 -0400[diff] [blame]780 struct Scsi_Host *host;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]781
782 METHOD_TRACE("ips_eh_abort", 1);
783
784 if (!SC)
785 return (FAILED);
786
Jeff Garzik 8fa728a2005-05-28 07:54:40 -0400[diff] [blame]787 host = SC->device->host;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]788 ha = (ips_ha_t *) SC->device->host->hostdata;
789
790 if (!ha)
791 return (FAILED);
792
793 if (!ha->active)
794 return (FAILED);
795
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]796 spin_lock(host->host_lock);
Jeff Garzik 8fa728a2005-05-28 07:54:40 -0400[diff] [blame]797
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]798 /* See if the command is on the copp queue */
799 item = ha->copp_waitlist.head;
800 while ((item) && (item->scsi_cmd != SC))
801 item = item->next;
802
803 if (item) {
804 /* Found it */
805 ips_removeq_copp(&ha->copp_waitlist, item);
806 ret = (SUCCESS);
807
808 /* See if the command is on the wait queue */
809 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
810 /* command not sent yet */
811 ret = (SUCCESS);
812 } else {
813 /* command must have already been sent */
814 ret = (FAILED);
815 }
Jeff Garzik 8fa728a2005-05-28 07:54:40 -0400[diff] [blame]816
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]817 spin_unlock(host->host_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]818 return ret;
819}
820
821/****************************************************************************/
822/* */
823/* Routine Name: ips_eh_reset */
824/* */
825/* Routine Description: */
826/* */
827/* Reset the controller (with new eh error code) */
828/* */
829/* NOTE: this routine is called under the io_request_lock spinlock */
830/* */
831/****************************************************************************/
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]832static int __ips_eh_reset(struct scsi_cmnd *SC)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]833{
834 int ret;
835 int i;
836 ips_ha_t *ha;
837 ips_scb_t *scb;
838 ips_copp_wait_item_t *item;
839
840 METHOD_TRACE("ips_eh_reset", 1);
841
842#ifdef NO_IPS_RESET
843 return (FAILED);
844#else
845
846 if (!SC) {
847 DEBUG(1, "Reset called with NULL scsi command");
848
849 return (FAILED);
850 }
851
852 ha = (ips_ha_t *) SC->device->host->hostdata;
853
854 if (!ha) {
855 DEBUG(1, "Reset called with NULL ha struct");
856
857 return (FAILED);
858 }
859
860 if (!ha->active)
861 return (FAILED);
862
863 /* See if the command is on the copp queue */
864 item = ha->copp_waitlist.head;
865 while ((item) && (item->scsi_cmd != SC))
866 item = item->next;
867
868 if (item) {
869 /* Found it */
870 ips_removeq_copp(&ha->copp_waitlist, item);
871 return (SUCCESS);
872 }
873
874 /* See if the command is on the wait queue */
875 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
876 /* command not sent yet */
877 return (SUCCESS);
878 }
879
880 /* An explanation for the casual observer: */
881 /* Part of the function of a RAID controller is automatic error */
882 /* detection and recovery. As such, the only problem that physically */
883 /* resetting an adapter will ever fix is when, for some reason, */
884 /* the driver is not successfully communicating with the adapter. */
885 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
886 /* then there's no real purpose in a physical reset. This will complete */
887 /* much faster and avoids any problems that might be caused by a */
888 /* physical reset ( such as having to fail all the outstanding I/O's ). */
889
890 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
891 scb = &ha->scbs[ha->max_cmds - 1];
892
893 ips_init_scb(ha, scb);
894
895 scb->timeout = ips_cmd_timeout;
896 scb->cdb[0] = IPS_CMD_FLUSH;
897
898 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
899 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
900 scb->cmd.flush_cache.state = IPS_NORM_STATE;
901 scb->cmd.flush_cache.reserved = 0;
902 scb->cmd.flush_cache.reserved2 = 0;
903 scb->cmd.flush_cache.reserved3 = 0;
904 scb->cmd.flush_cache.reserved4 = 0;
905
906 /* Attempt the flush command */
907 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
908 if (ret == IPS_SUCCESS) {
909 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
910 "Reset Request - Flushed Cache\n");
911 return (SUCCESS);
912 }
913 }
914
915 /* Either we can't communicate with the adapter or it's an IOCTL request */
916 /* from a utility. A physical reset is needed at this point. */
917
918 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
919
920 /*
921 * command must have already been sent
922 * reset the controller
923 */
924 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
925 ret = (*ha->func.reset) (ha);
926
927 if (!ret) {
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]928 struct scsi_cmnd *scsi_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]929
930 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
931 "Controller reset failed - controller now offline.\n");
932
933 /* Now fail all of the active commands */
934 DEBUG_VAR(1, "(%s%d) Failing active commands",
935 ips_name, ha->host_num);
936
937 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
938 scb->scsi_cmd->result = DID_ERROR << 16;
939 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
940 ips_freescb(ha, scb);
941 }
942
943 /* Now fail all of the pending commands */
944 DEBUG_VAR(1, "(%s%d) Failing pending commands",
945 ips_name, ha->host_num);
946
947 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
948 scsi_cmd->result = DID_ERROR;
949 scsi_cmd->scsi_done(scsi_cmd);
950 }
951
952 ha->active = FALSE;
953 return (FAILED);
954 }
955
956 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]957 struct scsi_cmnd *scsi_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]958
959 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
960 "Controller reset failed - controller now offline.\n");
961
962 /* Now fail all of the active commands */
963 DEBUG_VAR(1, "(%s%d) Failing active commands",
964 ips_name, ha->host_num);
965
966 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
967 scb->scsi_cmd->result = DID_ERROR << 16;
968 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
969 ips_freescb(ha, scb);
970 }
971
972 /* Now fail all of the pending commands */
973 DEBUG_VAR(1, "(%s%d) Failing pending commands",
974 ips_name, ha->host_num);
975
976 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
977 scsi_cmd->result = DID_ERROR << 16;
978 scsi_cmd->scsi_done(scsi_cmd);
979 }
980
981 ha->active = FALSE;
982 return (FAILED);
983 }
984
985 /* FFDC */
986 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
Arnd Bergmannf990bee2018-04-20 18:04:40 +0200[diff] [blame]987 ha->last_ffdc = ktime_get_real_seconds();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]988 ha->reset_count++;
989 ips_ffdc_reset(ha, IPS_INTR_IORL);
990 }
991
992 /* Now fail all of the active commands */
993 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
994
995 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
Martin K. Petersen1c9fbaf2009-01-04 03:14:11 -0500[diff] [blame]996 scb->scsi_cmd->result = DID_RESET << 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]997 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
998 ips_freescb(ha, scb);
999 }
1000
1001 /* Reset DCDB active command bits */
1002 for (i = 1; i < ha->nbus; i++)
1003 ha->dcdb_active[i - 1] = 0;
1004
1005 /* Reset the number of active IOCTLs */
1006 ha->num_ioctl = 0;
1007
1008 ips_next(ha, IPS_INTR_IORL);
1009
1010 return (SUCCESS);
1011#endif /* NO_IPS_RESET */
1012
1013}
1014
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]1015static int ips_eh_reset(struct scsi_cmnd *SC)
Jeff Garzik df0ae242005-05-28 07:57:14 -0400[diff] [blame]1016{
1017 int rc;
1018
1019 spin_lock_irq(SC->device->host->host_lock);
1020 rc = __ips_eh_reset(SC);
1021 spin_unlock_irq(SC->device->host->host_lock);
1022
1023 return rc;
1024}
1025
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1026/****************************************************************************/
1027/* */
1028/* Routine Name: ips_queue */
1029/* */
1030/* Routine Description: */
1031/* */
1032/* Send a command to the controller */
1033/* */
1034/* NOTE: */
1035/* Linux obtains io_request_lock before calling this function */
1036/* */
1037/****************************************************************************/
Jeff Garzikf2812332010-11-16 02:10:29 -0500[diff] [blame]1038static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1039{
1040 ips_ha_t *ha;
1041 ips_passthru_t *pt;
1042
1043 METHOD_TRACE("ips_queue", 1);
1044
1045 ha = (ips_ha_t *) SC->device->host->hostdata;
1046
1047 if (!ha)
Hannes Reinecke88188172021-01-13 10:04:56 +0100[diff] [blame]1048 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1049
1050 if (!ha->active)
Hannes Reinecke88188172021-01-13 10:04:56 +0100[diff] [blame]1051 goto out_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1052
1053 if (ips_is_passthru(SC)) {
1054 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1055 SC->result = DID_BUS_BUSY << 16;
1056 done(SC);
1057
1058 return (0);
1059 }
1060 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1061 SC->result = DID_BUS_BUSY << 16;
1062 done(SC);
1063
1064 return (0);
1065 }
1066
1067 SC->scsi_done = done;
1068
1069 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1070 ips_name,
1071 ha->host_num,
1072 SC->cmnd[0],
1073 SC->device->channel, SC->device->id, SC->device->lun);
1074
1075 /* Check for command to initiator IDs */
Jeff Garzik422c0d62005-10-24 18:05:09 -0400[diff] [blame]1076 if ((scmd_channel(SC) > 0)
1077 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1078 SC->result = DID_NO_CONNECT << 16;
1079 done(SC);
1080
1081 return (0);
1082 }
1083
1084 if (ips_is_passthru(SC)) {
1085
1086 ips_copp_wait_item_t *scratch;
1087
1088 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1089 /* There can never be any system activity ( network or disk ), but check */
1090 /* anyway just as a good practice. */
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1091 pt = (ips_passthru_t *) scsi_sglist(SC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1092 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1093 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1094 if (ha->scb_activelist.count != 0) {
1095 SC->result = DID_BUS_BUSY << 16;
1096 done(SC);
1097 return (0);
1098 }
1099 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
Mike Christieba3af0a2006-02-22 02:11:59 -0600[diff] [blame]1100 __ips_eh_reset(SC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1101 SC->result = DID_OK << 16;
1102 SC->scsi_done(SC);
1103 return (0);
1104 }
1105
1106 /* allocate space for the scribble */
1107 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1108
1109 if (!scratch) {
1110 SC->result = DID_ERROR << 16;
1111 done(SC);
1112
1113 return (0);
1114 }
1115
1116 scratch->scsi_cmd = SC;
1117 scratch->next = NULL;
1118
1119 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1120 } else {
1121 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1122 }
1123
1124 ips_next(ha, IPS_INTR_IORL);
1125
1126 return (0);
Hannes Reinecke88188172021-01-13 10:04:56 +0100[diff] [blame]1127out_error:
1128 SC->result = DID_ERROR << 16;
1129 done(SC);
1130
1131 return (0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1132}
1133
Jeff Garzikf2812332010-11-16 02:10:29 -0500[diff] [blame]1134static DEF_SCSI_QCMD(ips_queue)
1135
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1136/****************************************************************************/
1137/* */
1138/* Routine Name: ips_biosparam */
1139/* */
1140/* Routine Description: */
1141/* */
1142/* Set bios geometry for the controller */
1143/* */
1144/****************************************************************************/
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]1145static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1146 sector_t capacity, int geom[])
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1147{
1148 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1149 int heads;
1150 int sectors;
1151 int cylinders;
1152
1153 METHOD_TRACE("ips_biosparam", 1);
1154
1155 if (!ha)
1156 /* ?!?! host adater info invalid */
1157 return (0);
1158
1159 if (!ha->active)
1160 return (0);
1161
1162 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1163 /* ?!?! Enquiry command failed */
1164 return (0);
1165
1166 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1167 heads = IPS_NORM_HEADS;
1168 sectors = IPS_NORM_SECTORS;
1169 } else {
1170 heads = IPS_COMP_HEADS;
1171 sectors = IPS_COMP_SECTORS;
1172 }
1173
1174 cylinders = (unsigned long) capacity / (heads * sectors);
1175
1176 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1177 heads, sectors, cylinders);
1178
1179 geom[0] = heads;
1180 geom[1] = sectors;
1181 geom[2] = cylinders;
1182
1183 return (0);
1184}
1185
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1186/****************************************************************************/
1187/* */
1188/* Routine Name: ips_slave_configure */
1189/* */
1190/* Routine Description: */
1191/* */
1192/* Set queue depths on devices once scan is complete */
1193/* */
1194/****************************************************************************/
1195static int
Christoph Hellwigf64a1812005-10-31 18:32:08 +0100[diff] [blame]1196ips_slave_configure(struct scsi_device * SDptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1197{
1198 ips_ha_t *ha;
1199 int min;
1200
1201 ha = IPS_HA(SDptr->host);
1202 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1203 min = ha->max_cmds / 2;
1204 if (ha->enq->ucLogDriveCount <= 2)
1205 min = ha->max_cmds - 1;
Christoph Hellwigdb5ed4d2014-11-13 15:08:42 +0100[diff] [blame]1206 scsi_change_queue_depth(SDptr, min);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1207 }
Jack Hammer560c26c2006-01-13 10:06:50 -0500[diff] [blame]1208
1209 SDptr->skip_ms_page_8 = 1;
1210 SDptr->skip_ms_page_3f = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1211 return 0;
1212}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1213
1214/****************************************************************************/
1215/* */
1216/* Routine Name: do_ipsintr */
1217/* */
1218/* Routine Description: */
1219/* */
1220/* Wrapper for the interrupt handler */
1221/* */
1222/****************************************************************************/
1223static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +0100[diff] [blame]1224do_ipsintr(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1225{
1226 ips_ha_t *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1227 struct Scsi_Host *host;
1228 int irqstatus;
1229
1230 METHOD_TRACE("do_ipsintr", 2);
1231
1232 ha = (ips_ha_t *) dev_id;
1233 if (!ha)
1234 return IRQ_NONE;
1235 host = ips_sh[ha->host_num];
1236 /* interrupt during initialization */
1237 if (!host) {
1238 (*ha->func.intr) (ha);
1239 return IRQ_HANDLED;
1240 }
1241
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]1242 spin_lock(host->host_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1243
1244 if (!ha->active) {
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]1245 spin_unlock(host->host_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1246 return IRQ_HANDLED;
1247 }
1248
1249 irqstatus = (*ha->func.intr) (ha);
1250
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]1251 spin_unlock(host->host_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1252
1253 /* start the next command */
1254 ips_next(ha, IPS_INTR_ON);
1255 return IRQ_RETVAL(irqstatus);
1256}
1257
1258/****************************************************************************/
1259/* */
1260/* Routine Name: ips_intr_copperhead */
1261/* */
1262/* Routine Description: */
1263/* */
1264/* Polling interrupt handler */
1265/* */
1266/* ASSUMES interrupts are disabled */
1267/* */
1268/****************************************************************************/
1269int
1270ips_intr_copperhead(ips_ha_t * ha)
1271{
1272 ips_stat_t *sp;
1273 ips_scb_t *scb;
1274 IPS_STATUS cstatus;
1275 int intrstatus;
1276
1277 METHOD_TRACE("ips_intr", 2);
1278
1279 if (!ha)
1280 return 0;
1281
1282 if (!ha->active)
1283 return 0;
1284
1285 intrstatus = (*ha->func.isintr) (ha);
1286
1287 if (!intrstatus) {
1288 /*
1289 * Unexpected/Shared interrupt
1290 */
1291
1292 return 0;
1293 }
1294
1295 while (TRUE) {
1296 sp = &ha->sp;
1297
1298 intrstatus = (*ha->func.isintr) (ha);
1299
1300 if (!intrstatus)
1301 break;
1302 else
1303 cstatus.value = (*ha->func.statupd) (ha);
1304
1305 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
Joe Perchesb1c11812008-02-03 17:28:22 +0200[diff] [blame]1306 /* Spurious Interrupt ? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1307 continue;
1308 }
1309
1310 ips_chkstatus(ha, &cstatus);
1311 scb = (ips_scb_t *) sp->scb_addr;
1312
1313 /*
1314 * use the callback function to finish things up
1315 * NOTE: interrupts are OFF for this
1316 */
1317 (*scb->callback) (ha, scb);
1318 } /* end while */
1319 return 1;
1320}
1321
1322/****************************************************************************/
1323/* */
1324/* Routine Name: ips_intr_morpheus */
1325/* */
1326/* Routine Description: */
1327/* */
1328/* Polling interrupt handler */
1329/* */
1330/* ASSUMES interrupts are disabled */
1331/* */
1332/****************************************************************************/
1333int
1334ips_intr_morpheus(ips_ha_t * ha)
1335{
1336 ips_stat_t *sp;
1337 ips_scb_t *scb;
1338 IPS_STATUS cstatus;
1339 int intrstatus;
1340
1341 METHOD_TRACE("ips_intr_morpheus", 2);
1342
1343 if (!ha)
1344 return 0;
1345
1346 if (!ha->active)
1347 return 0;
1348
1349 intrstatus = (*ha->func.isintr) (ha);
1350
1351 if (!intrstatus) {
1352 /*
1353 * Unexpected/Shared interrupt
1354 */
1355
1356 return 0;
1357 }
1358
1359 while (TRUE) {
1360 sp = &ha->sp;
1361
1362 intrstatus = (*ha->func.isintr) (ha);
1363
1364 if (!intrstatus)
1365 break;
1366 else
1367 cstatus.value = (*ha->func.statupd) (ha);
1368
1369 if (cstatus.value == 0xffffffff)
1370 /* No more to process */
1371 break;
1372
1373 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1374 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1375 "Spurious interrupt; no ccb.\n");
1376
1377 continue;
1378 }
1379
1380 ips_chkstatus(ha, &cstatus);
1381 scb = (ips_scb_t *) sp->scb_addr;
1382
1383 /*
1384 * use the callback function to finish things up
1385 * NOTE: interrupts are OFF for this
1386 */
1387 (*scb->callback) (ha, scb);
1388 } /* end while */
1389 return 1;
1390}
1391
1392/****************************************************************************/
1393/* */
1394/* Routine Name: ips_info */
1395/* */
1396/* Routine Description: */
1397/* */
1398/* Return info about the driver */
1399/* */
1400/****************************************************************************/
1401static const char *
1402ips_info(struct Scsi_Host *SH)
1403{
1404 static char buffer[256];
1405 char *bp;
1406 ips_ha_t *ha;
1407
1408 METHOD_TRACE("ips_info", 1);
1409
1410 ha = IPS_HA(SH);
1411
1412 if (!ha)
1413 return (NULL);
1414
1415 bp = &buffer[0];
1416 memset(bp, 0, sizeof (buffer));
1417
1418 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1419 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1420
1421 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1422 strcat(bp, " <");
1423 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1424 strcat(bp, ">");
1425 }
1426
1427 return (bp);
1428}
1429
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1430static int
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]1431ips_write_info(struct Scsi_Host *host, char *buffer, int length)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1432{
1433 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1434 ips_ha_t *ha = NULL;
1435
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1436 /* Find our host structure */
1437 for (i = 0; i < ips_next_controller; i++) {
1438 if (ips_sh[i]) {
1439 if (ips_sh[i] == host) {
1440 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1441 break;
1442 }
1443 }
1444 }
1445
1446 if (!ha)
1447 return (-EINVAL);
1448
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]1449 return 0;
1450}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1451
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]1452static int
1453ips_show_info(struct seq_file *m, struct Scsi_Host *host)
1454{
1455 int i;
1456 ips_ha_t *ha = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1457
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]1458 /* Find our host structure */
1459 for (i = 0; i < ips_next_controller; i++) {
1460 if (ips_sh[i]) {
1461 if (ips_sh[i] == host) {
1462 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1463 break;
1464 }
1465 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1466 }
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]1467
1468 if (!ha)
1469 return (-EINVAL);
1470
1471 return ips_host_info(ha, m);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1472}
1473
1474/*--------------------------------------------------------------------------*/
1475/* Helper Functions */
1476/*--------------------------------------------------------------------------*/
1477
1478/****************************************************************************/
1479/* */
1480/* Routine Name: ips_is_passthru */
1481/* */
1482/* Routine Description: */
1483/* */
1484/* Determine if the specified SCSI command is really a passthru command */
1485/* */
1486/****************************************************************************/
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]1487static int ips_is_passthru(struct scsi_cmnd *SC)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1488{
Jack Hammera3632fa2005-10-25 14:13:03 -0400[diff] [blame]1489 unsigned long flags;
1490
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1491 METHOD_TRACE("ips_is_passthru", 1);
1492
1493 if (!SC)
1494 return (0);
1495
1496 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1497 (SC->device->channel == 0) &&
1498 (SC->device->id == IPS_ADAPTER_ID) &&
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1499 (SC->device->lun == 0) && scsi_sglist(SC)) {
1500 struct scatterlist *sg = scsi_sglist(SC);
1501 char *buffer;
Jack Hammera3632fa2005-10-25 14:13:03 -0400[diff] [blame]1502
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1503 /* kmap_atomic() ensures addressability of the user buffer.*/
1504 /* local_irq_save() protects the KM_IRQ0 address slot. */
1505 local_irq_save(flags);
Cong Wang77dfce02011-11-25 23:14:23 +0800[diff] [blame]1506 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1507 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1508 buffer[2] == 'P' && buffer[3] == 'P') {
Cong Wang77dfce02011-11-25 23:14:23 +0800[diff] [blame]1509 kunmap_atomic(buffer - sg->offset);
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1510 local_irq_restore(flags);
1511 return 1;
1512 }
Cong Wang77dfce02011-11-25 23:14:23 +0800[diff] [blame]1513 kunmap_atomic(buffer - sg->offset);
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1514 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1515 }
1516 return 0;
1517}
1518
1519/****************************************************************************/
1520/* */
1521/* Routine Name: ips_alloc_passthru_buffer */
1522/* */
1523/* Routine Description: */
1524/* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1525/* is too small or doesn't exist */
1526/****************************************************************************/
1527static int
1528ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1529{
1530 void *bigger_buf;
1531 dma_addr_t dma_busaddr;
1532
1533 if (ha->ioctl_data && length <= ha->ioctl_len)
1534 return 0;
1535 /* there is no buffer or it's not big enough, allocate a new one */
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]1536 bigger_buf = dma_alloc_coherent(&ha->pcidev->dev, length, &dma_busaddr,
1537 GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1538 if (bigger_buf) {
1539 /* free the old memory */
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]1540 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
1541 ha->ioctl_data, ha->ioctl_busaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1542 /* use the new memory */
1543 ha->ioctl_data = (char *) bigger_buf;
1544 ha->ioctl_len = length;
1545 ha->ioctl_busaddr = dma_busaddr;
1546 } else {
1547 return -1;
1548 }
1549 return 0;
1550}
1551
1552/****************************************************************************/
1553/* */
1554/* Routine Name: ips_make_passthru */
1555/* */
1556/* Routine Description: */
1557/* */
1558/* Make a passthru command out of the info in the Scsi block */
1559/* */
1560/****************************************************************************/
1561static int
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]1562ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1563{
1564 ips_passthru_t *pt;
1565 int length = 0;
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1566 int i, ret;
1567 struct scatterlist *sg = scsi_sglist(SC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1568
1569 METHOD_TRACE("ips_make_passthru", 1);
1570
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1571 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
FUJITA Tomonori2b28a472008-02-19 17:02:27 +0900[diff] [blame]1572 length += sg->length;
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1573
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1574 if (length < sizeof (ips_passthru_t)) {
1575 /* wrong size */
1576 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1577 ips_name, ha->host_num);
1578 return (IPS_FAILURE);
1579 }
1580 if (ips_alloc_passthru_buffer(ha, length)) {
1581 /* allocation failure! If ha->ioctl_data exists, use it to return
1582 some error codes. Return a failed command to the scsi layer. */
1583 if (ha->ioctl_data) {
1584 pt = (ips_passthru_t *) ha->ioctl_data;
1585 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1586 pt->BasicStatus = 0x0B;
1587 pt->ExtendedStatus = 0x00;
1588 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1589 }
1590 return IPS_FAILURE;
1591 }
1592 ha->ioctl_datasize = length;
1593
1594 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1595 pt = (ips_passthru_t *) ha->ioctl_data;
1596
1597 /*
1598 * Some notes about the passthru interface used
1599 *
1600 * IF the scsi op_code == 0x0d then we assume
1601 * that the data came along with/goes with the
1602 * packet we received from the sg driver. In this
1603 * case the CmdBSize field of the pt structure is
1604 * used for the size of the buffer.
1605 */
1606
1607 switch (pt->CoppCmd) {
1608 case IPS_NUMCTRLS:
1609 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1610 &ips_num_controllers, sizeof (int));
1611 ips_scmd_buf_write(SC, ha->ioctl_data,
1612 sizeof (ips_passthru_t) + sizeof (int));
1613 SC->result = DID_OK << 16;
1614
1615 return (IPS_SUCCESS_IMM);
1616
1617 case IPS_COPPUSRCMD:
1618 case IPS_COPPIOCCMD:
1619 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1620 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1621 /* wrong size */
1622 DEBUG_VAR(1,
1623 "(%s%d) Passthru structure wrong size",
1624 ips_name, ha->host_num);
1625
1626 return (IPS_FAILURE);
1627 }
1628
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]1629 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1630 pt->CoppCP.cmd.flashfw.op_code ==
1631 IPS_CMD_RW_BIOSFW) {
1632 ret = ips_flash_copperhead(ha, pt, scb);
1633 ips_scmd_buf_write(SC, ha->ioctl_data,
1634 sizeof (ips_passthru_t));
1635 return ret;
1636 }
1637 if (ips_usrcmd(ha, pt, scb))
1638 return (IPS_SUCCESS);
1639 else
1640 return (IPS_FAILURE);
1641 }
1642
1643 break;
1644
1645 } /* end switch */
1646
1647 return (IPS_FAILURE);
1648}
1649
1650/****************************************************************************/
1651/* Routine Name: ips_flash_copperhead */
1652/* Routine Description: */
1653/* Flash the BIOS/FW on a Copperhead style controller */
1654/****************************************************************************/
1655static int
1656ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1657{
1658 int datasize;
1659
1660 /* Trombone is the only copperhead that can do packet flash, but only
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]1661 * for firmware. No one said it had to make sense. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1662 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1663 if (ips_usrcmd(ha, pt, scb))
1664 return IPS_SUCCESS;
1665 else
1666 return IPS_FAILURE;
1667 }
1668 pt->BasicStatus = 0x0B;
1669 pt->ExtendedStatus = 0;
1670 scb->scsi_cmd->result = DID_OK << 16;
1671 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1672 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1673 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1674 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1675 pt->BasicStatus = 0;
1676 return ips_flash_bios(ha, pt, scb);
1677 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1678 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1679 ha->flash_data = ips_FlashData;
1680 ha->flash_busaddr = ips_flashbusaddr;
1681 ha->flash_len = PAGE_SIZE << 7;
1682 ha->flash_datasize = 0;
1683 } else if (!ha->flash_data) {
1684 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1685 pt->CoppCP.cmd.flashfw.count;
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]1686 ha->flash_data = dma_alloc_coherent(&ha->pcidev->dev,
1687 datasize, &ha->flash_busaddr, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1688 if (!ha->flash_data){
1689 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1690 return IPS_FAILURE;
1691 }
1692 ha->flash_datasize = 0;
1693 ha->flash_len = datasize;
1694 } else
1695 return IPS_FAILURE;
1696 } else {
1697 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1698 ha->flash_len) {
1699 ips_free_flash_copperhead(ha);
1700 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1701 "failed size sanity check\n");
1702 return IPS_FAILURE;
1703 }
1704 }
1705 if (!ha->flash_data)
1706 return IPS_FAILURE;
1707 pt->BasicStatus = 0;
1708 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1709 pt->CoppCP.cmd.flashfw.count);
1710 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1711 if (pt->CoppCP.cmd.flashfw.packet_num ==
1712 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1713 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1714 return ips_flash_bios(ha, pt, scb);
1715 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1716 return ips_flash_firmware(ha, pt, scb);
1717 }
1718 return IPS_SUCCESS_IMM;
1719}
1720
1721/****************************************************************************/
1722/* Routine Name: ips_flash_bios */
1723/* Routine Description: */
1724/* flashes the bios of a copperhead adapter */
1725/****************************************************************************/
1726static int
1727ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1728{
1729
1730 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1731 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1732 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1733 (!ha->func.verifybios))
1734 goto error;
1735 if ((*ha->func.erasebios) (ha)) {
1736 DEBUG_VAR(1,
1737 "(%s%d) flash bios failed - unable to erase flash",
1738 ips_name, ha->host_num);
1739 goto error;
1740 } else
1741 if ((*ha->func.programbios) (ha,
1742 ha->flash_data +
1743 IPS_BIOS_HEADER,
1744 ha->flash_datasize -
1745 IPS_BIOS_HEADER, 0)) {
1746 DEBUG_VAR(1,
1747 "(%s%d) flash bios failed - unable to flash",
1748 ips_name, ha->host_num);
1749 goto error;
1750 } else
1751 if ((*ha->func.verifybios) (ha,
1752 ha->flash_data +
1753 IPS_BIOS_HEADER,
1754 ha->flash_datasize -
1755 IPS_BIOS_HEADER, 0)) {
1756 DEBUG_VAR(1,
1757 "(%s%d) flash bios failed - unable to verify flash",
1758 ips_name, ha->host_num);
1759 goto error;
1760 }
1761 ips_free_flash_copperhead(ha);
1762 return IPS_SUCCESS_IMM;
1763 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1764 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1765 if (!ha->func.erasebios)
1766 goto error;
1767 if ((*ha->func.erasebios) (ha)) {
1768 DEBUG_VAR(1,
1769 "(%s%d) flash bios failed - unable to erase flash",
1770 ips_name, ha->host_num);
1771 goto error;
1772 }
1773 return IPS_SUCCESS_IMM;
1774 }
1775 error:
1776 pt->BasicStatus = 0x0B;
1777 pt->ExtendedStatus = 0x00;
1778 ips_free_flash_copperhead(ha);
1779 return IPS_FAILURE;
1780}
1781
1782/****************************************************************************/
1783/* */
1784/* Routine Name: ips_fill_scb_sg_single */
1785/* */
1786/* Routine Description: */
1787/* Fill in a single scb sg_list element from an address */
1788/* return a -1 if a breakup occurred */
1789/****************************************************************************/
1790static int
1791ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1792 ips_scb_t * scb, int indx, unsigned int e_len)
1793{
1794
1795 int ret_val = 0;
1796
1797 if ((scb->data_len + e_len) > ha->max_xfer) {
1798 e_len = ha->max_xfer - scb->data_len;
1799 scb->breakup = indx;
1800 ++scb->sg_break;
1801 ret_val = -1;
1802 } else {
1803 scb->breakup = 0;
1804 scb->sg_break = 0;
1805 }
1806 if (IPS_USE_ENH_SGLIST(ha)) {
1807 scb->sg_list.enh_list[indx].address_lo =
Christoph Hellwig6f6eb3c2018-10-18 15:03:33 +0200[diff] [blame]1808 cpu_to_le32(lower_32_bits(busaddr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1809 scb->sg_list.enh_list[indx].address_hi =
Christoph Hellwig6f6eb3c2018-10-18 15:03:33 +0200[diff] [blame]1810 cpu_to_le32(upper_32_bits(busaddr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1811 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1812 } else {
1813 scb->sg_list.std_list[indx].address =
Christoph Hellwig6f6eb3c2018-10-18 15:03:33 +0200[diff] [blame]1814 cpu_to_le32(lower_32_bits(busaddr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1815 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1816 }
1817
1818 ++scb->sg_len;
1819 scb->data_len += e_len;
1820 return ret_val;
1821}
1822
1823/****************************************************************************/
1824/* Routine Name: ips_flash_firmware */
1825/* Routine Description: */
1826/* flashes the firmware of a copperhead adapter */
1827/****************************************************************************/
1828static int
1829ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1830{
1831 IPS_SG_LIST sg_list;
1832 uint32_t cmd_busaddr;
1833
1834 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1835 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1836 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1837 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1838 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1839 } else {
1840 pt->BasicStatus = 0x0B;
1841 pt->ExtendedStatus = 0x00;
1842 ips_free_flash_copperhead(ha);
1843 return IPS_FAILURE;
1844 }
1845 /* Save the S/G list pointer so it doesn't get clobbered */
1846 sg_list.list = scb->sg_list.list;
1847 cmd_busaddr = scb->scb_busaddr;
1848 /* copy in the CP */
1849 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1850 /* FIX stuff that might be wrong */
1851 scb->sg_list.list = sg_list.list;
1852 scb->scb_busaddr = cmd_busaddr;
1853 scb->bus = scb->scsi_cmd->device->channel;
1854 scb->target_id = scb->scsi_cmd->device->id;
1855 scb->lun = scb->scsi_cmd->device->lun;
1856 scb->sg_len = 0;
1857 scb->data_len = 0;
1858 scb->flags = 0;
1859 scb->op_code = 0;
1860 scb->callback = ipsintr_done;
1861 scb->timeout = ips_cmd_timeout;
1862
1863 scb->data_len = ha->flash_datasize;
1864 scb->data_busaddr =
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]1865 dma_map_single(&ha->pcidev->dev, ha->flash_data, scb->data_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1866 IPS_DMA_DIR(scb));
1867 scb->flags |= IPS_SCB_MAP_SINGLE;
1868 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1869 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1870 if (pt->TimeOut)
1871 scb->timeout = pt->TimeOut;
1872 scb->scsi_cmd->result = DID_OK << 16;
1873 return IPS_SUCCESS;
1874}
1875
1876/****************************************************************************/
1877/* Routine Name: ips_free_flash_copperhead */
1878/* Routine Description: */
1879/* release the memory resources used to hold the flash image */
1880/****************************************************************************/
1881static void
1882ips_free_flash_copperhead(ips_ha_t * ha)
1883{
1884 if (ha->flash_data == ips_FlashData)
1885 test_and_clear_bit(0, &ips_FlashDataInUse);
1886 else if (ha->flash_data)
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]1887 dma_free_coherent(&ha->pcidev->dev, ha->flash_len,
1888 ha->flash_data, ha->flash_busaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1889 ha->flash_data = NULL;
1890}
1891
1892/****************************************************************************/
1893/* */
1894/* Routine Name: ips_usrcmd */
1895/* */
1896/* Routine Description: */
1897/* */
1898/* Process a user command and make it ready to send */
1899/* */
1900/****************************************************************************/
1901static int
1902ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1903{
1904 IPS_SG_LIST sg_list;
1905 uint32_t cmd_busaddr;
1906
1907 METHOD_TRACE("ips_usrcmd", 1);
1908
1909 if ((!scb) || (!pt) || (!ha))
1910 return (0);
1911
1912 /* Save the S/G list pointer so it doesn't get clobbered */
1913 sg_list.list = scb->sg_list.list;
1914 cmd_busaddr = scb->scb_busaddr;
1915 /* copy in the CP */
1916 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1917 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1918
1919 /* FIX stuff that might be wrong */
1920 scb->sg_list.list = sg_list.list;
1921 scb->scb_busaddr = cmd_busaddr;
1922 scb->bus = scb->scsi_cmd->device->channel;
1923 scb->target_id = scb->scsi_cmd->device->id;
1924 scb->lun = scb->scsi_cmd->device->lun;
1925 scb->sg_len = 0;
1926 scb->data_len = 0;
1927 scb->flags = 0;
1928 scb->op_code = 0;
1929 scb->callback = ipsintr_done;
1930 scb->timeout = ips_cmd_timeout;
1931 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1932
1933 /* we don't support DCDB/READ/WRITE Scatter Gather */
1934 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1935 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1936 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1937 return (0);
1938
1939 if (pt->CmdBSize) {
1940 scb->data_len = pt->CmdBSize;
1941 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1942 } else {
1943 scb->data_busaddr = 0L;
1944 }
1945
1946 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1947 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1948 (unsigned long) &scb->
1949 dcdb -
1950 (unsigned long) scb);
1951
1952 if (pt->CmdBSize) {
1953 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1954 scb->dcdb.buffer_pointer =
1955 cpu_to_le32(scb->data_busaddr);
1956 else
1957 scb->cmd.basic_io.sg_addr =
1958 cpu_to_le32(scb->data_busaddr);
1959 }
1960
1961 /* set timeouts */
1962 if (pt->TimeOut) {
1963 scb->timeout = pt->TimeOut;
1964
1965 if (pt->TimeOut <= 10)
1966 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1967 else if (pt->TimeOut <= 60)
1968 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1969 else
1970 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1971 }
1972
1973 /* assume success */
1974 scb->scsi_cmd->result = DID_OK << 16;
1975
1976 /* success */
1977 return (1);
1978}
1979
1980/****************************************************************************/
1981/* */
1982/* Routine Name: ips_cleanup_passthru */
1983/* */
1984/* Routine Description: */
1985/* */
1986/* Cleanup after a passthru command */
1987/* */
1988/****************************************************************************/
1989static void
1990ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1991{
1992 ips_passthru_t *pt;
1993
1994 METHOD_TRACE("ips_cleanup_passthru", 1);
1995
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]1996 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1997 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
1998 ips_name, ha->host_num);
1999
2000 return;
2001 }
2002 pt = (ips_passthru_t *) ha->ioctl_data;
2003
2004 /* Copy data back to the user */
2005 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2006 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2007
2008 pt->BasicStatus = scb->basic_status;
2009 pt->ExtendedStatus = scb->extended_status;
2010 pt->AdapterType = ha->ad_type;
2011
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2012 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2013 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2014 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2015 ips_free_flash_copperhead(ha);
2016
2017 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2018}
2019
2020/****************************************************************************/
2021/* */
2022/* Routine Name: ips_host_info */
2023/* */
2024/* Routine Description: */
2025/* */
2026/* The passthru interface for the driver */
2027/* */
2028/****************************************************************************/
2029static int
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2030ips_host_info(ips_ha_t *ha, struct seq_file *m)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2031{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2032 METHOD_TRACE("ips_host_info", 1);
2033
Rasmus Villemoes91c40f22014-12-03 00:10:52 +0100[diff] [blame]2034 seq_puts(m, "\nIBM ServeRAID General Information:\n\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2035
2036 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2037 (le16_to_cpu(ha->nvram->adapter_type) != 0))
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2038 seq_printf(m, "\tController Type : %s\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2039 ips_adapter_name[ha->ad_type - 1]);
2040 else
Rasmus Villemoes91c40f22014-12-03 00:10:52 +0100[diff] [blame]2041 seq_puts(m, "\tController Type : Unknown\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2042
2043 if (ha->io_addr)
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2044 seq_printf(m,
Al Viro1bb71092013-03-31 12:17:09 -0400[diff] [blame]2045 "\tIO region : 0x%x (%d bytes)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2046 ha->io_addr, ha->io_len);
2047
2048 if (ha->mem_addr) {
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2049 seq_printf(m,
Al Viro1bb71092013-03-31 12:17:09 -0400[diff] [blame]2050 "\tMemory region : 0x%x (%d bytes)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2051 ha->mem_addr, ha->mem_len);
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2052 seq_printf(m,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2053 "\tShared memory address : 0x%lx\n",
Al Viro1bb71092013-03-31 12:17:09 -0400[diff] [blame]2054 (unsigned long)ha->mem_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2055 }
2056
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2057 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2058
2059 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2060 /* That keeps everything happy for "text" operations on the proc file. */
2061
2062 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]2063 if (ha->nvram->bios_low[3] == 0) {
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2064 seq_printf(m,
2065 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2066 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2067 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2068 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2069 ha->nvram->bios_low[2]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2070
2071 } else {
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2072 seq_printf(m,
2073 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2074 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2075 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2076 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2077 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2078 }
2079
2080 }
2081
2082 if (ha->enq->CodeBlkVersion[7] == 0) {
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2083 seq_printf(m,
2084 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2085 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2086 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2087 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2088 ha->enq->CodeBlkVersion[6]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2089 } else {
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2090 seq_printf(m,
2091 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2092 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2093 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2094 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2095 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2096 }
2097
2098 if (ha->enq->BootBlkVersion[7] == 0) {
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2099 seq_printf(m,
2100 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2101 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2102 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2103 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2104 ha->enq->BootBlkVersion[6]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2105 } else {
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2106 seq_printf(m,
2107 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2108 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2109 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2110 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2111 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2112 }
2113
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2114 seq_printf(m, "\tDriver Version : %s%s\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2115 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2116
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2117 seq_printf(m, "\tDriver Build : %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2118 IPS_BUILD_IDENT);
2119
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2120 seq_printf(m, "\tMax Physical Devices : %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2121 ha->enq->ucMaxPhysicalDevices);
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2122 seq_printf(m, "\tMax Active Commands : %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2123 ha->max_cmds);
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2124 seq_printf(m, "\tCurrent Queued Commands : %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2125 ha->scb_waitlist.count);
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2126 seq_printf(m, "\tCurrent Active Commands : %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2127 ha->scb_activelist.count - ha->num_ioctl);
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2128 seq_printf(m, "\tCurrent Queued PT Commands : %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2129 ha->copp_waitlist.count);
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2130 seq_printf(m, "\tCurrent Active PT Commands : %d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2131 ha->num_ioctl);
2132
Rasmus Villemoesf50332f2014-12-03 00:10:54 +0100[diff] [blame]2133 seq_putc(m, '\n');
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2134
Al Viroaacce702013-03-31 12:15:44 -0400[diff] [blame]2135 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2136}
2137
2138/****************************************************************************/
2139/* */
2140/* Routine Name: ips_identify_controller */
2141/* */
2142/* Routine Description: */
2143/* */
2144/* Identify this controller */
2145/* */
2146/****************************************************************************/
2147static void
2148ips_identify_controller(ips_ha_t * ha)
2149{
2150 METHOD_TRACE("ips_identify_controller", 1);
2151
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2152 switch (ha->pcidev->device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2153 case IPS_DEVICEID_COPPERHEAD:
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2154 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2155 ha->ad_type = IPS_ADTYPE_SERVERAID;
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2156 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2157 ha->ad_type = IPS_ADTYPE_SERVERAID2;
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2158 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2159 ha->ad_type = IPS_ADTYPE_NAVAJO;
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2160 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2161 && (ha->slot_num == 0)) {
2162 ha->ad_type = IPS_ADTYPE_KIOWA;
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2163 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2164 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2165 if (ha->enq->ucMaxPhysicalDevices == 15)
2166 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2167 else
2168 ha->ad_type = IPS_ADTYPE_SERVERAID3;
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2169 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2170 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2171 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2172 }
2173 break;
2174
2175 case IPS_DEVICEID_MORPHEUS:
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2176 switch (ha->pcidev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2177 case IPS_SUBDEVICEID_4L:
2178 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2179 break;
2180
2181 case IPS_SUBDEVICEID_4M:
2182 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2183 break;
2184
2185 case IPS_SUBDEVICEID_4MX:
2186 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2187 break;
2188
2189 case IPS_SUBDEVICEID_4LX:
2190 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2191 break;
2192
2193 case IPS_SUBDEVICEID_5I2:
2194 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2195 break;
2196
2197 case IPS_SUBDEVICEID_5I1:
2198 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2199 break;
2200 }
2201
2202 break;
2203
2204 case IPS_DEVICEID_MARCO:
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2205 switch (ha->pcidev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2206 case IPS_SUBDEVICEID_6M:
2207 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2208 break;
2209 case IPS_SUBDEVICEID_6I:
2210 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2211 break;
2212 case IPS_SUBDEVICEID_7k:
2213 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2214 break;
2215 case IPS_SUBDEVICEID_7M:
2216 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2217 break;
2218 }
2219 break;
2220 }
2221}
2222
2223/****************************************************************************/
2224/* */
2225/* Routine Name: ips_get_bios_version */
2226/* */
2227/* Routine Description: */
2228/* */
2229/* Get the BIOS revision number */
2230/* */
2231/****************************************************************************/
2232static void
2233ips_get_bios_version(ips_ha_t * ha, int intr)
2234{
2235 ips_scb_t *scb;
2236 int ret;
2237 uint8_t major;
2238 uint8_t minor;
2239 uint8_t subminor;
2240 uint8_t *buffer;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2241
2242 METHOD_TRACE("ips_get_bios_version", 1);
2243
2244 major = 0;
2245 minor = 0;
2246
Lee Jones00e24562020-07-23 13:24:19 +0100[diff] [blame]2247 memcpy(ha->bios_version, " ?", 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2248
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2249 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2250 if (IPS_USE_MEMIO(ha)) {
2251 /* Memory Mapped I/O */
2252
2253 /* test 1st byte */
2254 writel(0, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2255 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2256 udelay(25); /* 25 us */
2257
2258 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2259 return;
2260
2261 writel(1, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2262 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2263 udelay(25); /* 25 us */
2264
2265 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2266 return;
2267
2268 /* Get Major version */
2269 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2270 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2271 udelay(25); /* 25 us */
2272
2273 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2274
2275 /* Get Minor version */
2276 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2277 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2278 udelay(25); /* 25 us */
2279 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2280
2281 /* Get SubMinor version */
2282 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2283 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2284 udelay(25); /* 25 us */
2285 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2286
2287 } else {
2288 /* Programmed I/O */
2289
2290 /* test 1st byte */
2291 outl(0, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2292 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2293 udelay(25); /* 25 us */
2294
2295 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2296 return;
2297
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]2298 outl(1, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2299 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2300 udelay(25); /* 25 us */
2301
2302 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2303 return;
2304
2305 /* Get Major version */
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]2306 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2307 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2308 udelay(25); /* 25 us */
2309
2310 major = inb(ha->io_addr + IPS_REG_FLDP);
2311
2312 /* Get Minor version */
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]2313 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2314 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2315 udelay(25); /* 25 us */
2316
2317 minor = inb(ha->io_addr + IPS_REG_FLDP);
2318
2319 /* Get SubMinor version */
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]2320 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]2321 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2322 udelay(25); /* 25 us */
2323
2324 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2325
2326 }
2327 } else {
2328 /* Morpheus Family - Send Command to the card */
2329
2330 buffer = ha->ioctl_data;
2331
2332 memset(buffer, 0, 0x1000);
2333
2334 scb = &ha->scbs[ha->max_cmds - 1];
2335
2336 ips_init_scb(ha, scb);
2337
2338 scb->timeout = ips_cmd_timeout;
2339 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2340
2341 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2342 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2343 scb->cmd.flashfw.type = 1;
2344 scb->cmd.flashfw.direction = 0;
2345 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2346 scb->cmd.flashfw.total_packets = 1;
2347 scb->cmd.flashfw.packet_num = 0;
2348 scb->data_len = 0x1000;
2349 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2350
2351 /* issue the command */
2352 if (((ret =
2353 ips_send_wait(ha, scb, ips_cmd_timeout,
2354 intr)) == IPS_FAILURE)
2355 || (ret == IPS_SUCCESS_IMM)
2356 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2357 /* Error occurred */
2358
2359 return;
2360 }
2361
2362 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2363 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2364 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2365 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2366 } else {
2367 return;
2368 }
2369 }
2370
Andy Shevchenko1bc50452016-10-22 20:32:29 +0300[diff] [blame]2371 ha->bios_version[0] = hex_asc_upper_hi(major);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2372 ha->bios_version[1] = '.';
Andy Shevchenko1bc50452016-10-22 20:32:29 +0300[diff] [blame]2373 ha->bios_version[2] = hex_asc_upper_lo(major);
2374 ha->bios_version[3] = hex_asc_upper_lo(subminor);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2375 ha->bios_version[4] = '.';
Andy Shevchenko1bc50452016-10-22 20:32:29 +0300[diff] [blame]2376 ha->bios_version[5] = hex_asc_upper_hi(minor);
2377 ha->bios_version[6] = hex_asc_upper_lo(minor);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2378 ha->bios_version[7] = 0;
2379}
2380
2381/****************************************************************************/
2382/* */
2383/* Routine Name: ips_hainit */
2384/* */
2385/* Routine Description: */
2386/* */
2387/* Initialize the controller */
2388/* */
2389/* NOTE: Assumes to be called from with a lock */
2390/* */
2391/****************************************************************************/
2392static int
2393ips_hainit(ips_ha_t * ha)
2394{
2395 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2396
2397 METHOD_TRACE("ips_hainit", 1);
2398
2399 if (!ha)
2400 return (0);
2401
2402 if (ha->func.statinit)
2403 (*ha->func.statinit) (ha);
2404
2405 if (ha->func.enableint)
2406 (*ha->func.enableint) (ha);
2407
2408 /* Send FFDC */
2409 ha->reset_count = 1;
Arnd Bergmannf990bee2018-04-20 18:04:40 +0200[diff] [blame]2410 ha->last_ffdc = ktime_get_real_seconds();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2411 ips_ffdc_reset(ha, IPS_INTR_IORL);
2412
2413 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2414 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2415 "unable to read config from controller.\n");
2416
2417 return (0);
2418 }
2419 /* end if */
2420 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2421 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2422 "unable to read controller status.\n");
2423
2424 return (0);
2425 }
2426
2427 /* Identify this controller */
2428 ips_identify_controller(ha);
2429
2430 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2431 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2432 "unable to read subsystem parameters.\n");
2433
2434 return (0);
2435 }
2436
2437 /* write nvram user page 5 */
2438 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2439 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2440 "unable to write driver info to controller.\n");
2441
2442 return (0);
2443 }
2444
2445 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2446 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2447 ips_clear_adapter(ha, IPS_INTR_IORL);
2448
2449 /* set limits on SID, LUN, BUS */
2450 ha->ntargets = IPS_MAX_TARGETS + 1;
2451 ha->nlun = 1;
2452 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2453
2454 switch (ha->conf->logical_drive[0].ucStripeSize) {
2455 case 4:
2456 ha->max_xfer = 0x10000;
2457 break;
2458
2459 case 5:
2460 ha->max_xfer = 0x20000;
2461 break;
2462
2463 case 6:
2464 ha->max_xfer = 0x40000;
2465 break;
2466
2467 case 7:
2468 default:
2469 ha->max_xfer = 0x80000;
2470 break;
2471 }
2472
2473 /* setup max concurrent commands */
2474 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2475 /* Use the new method */
2476 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2477 } else {
2478 /* use the old method */
2479 switch (ha->conf->logical_drive[0].ucStripeSize) {
2480 case 4:
2481 ha->max_cmds = 32;
2482 break;
2483
2484 case 5:
2485 ha->max_cmds = 16;
2486 break;
2487
2488 case 6:
2489 ha->max_cmds = 8;
2490 break;
2491
2492 case 7:
2493 default:
2494 ha->max_cmds = 4;
2495 break;
2496 }
2497 }
2498
2499 /* Limit the Active Commands on a Lite Adapter */
2500 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2501 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2502 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2503 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2504 ha->max_cmds = MaxLiteCmds;
2505 }
2506
2507 /* set controller IDs */
2508 ha->ha_id[0] = IPS_ADAPTER_ID;
2509 for (i = 1; i < ha->nbus; i++) {
2510 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2511 ha->dcdb_active[i - 1] = 0;
2512 }
2513
2514 return (1);
2515}
2516
2517/****************************************************************************/
2518/* */
2519/* Routine Name: ips_next */
2520/* */
2521/* Routine Description: */
2522/* */
2523/* Take the next command off the queue and send it to the controller */
2524/* */
2525/****************************************************************************/
2526static void
2527ips_next(ips_ha_t * ha, int intr)
2528{
2529 ips_scb_t *scb;
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]2530 struct scsi_cmnd *SC;
2531 struct scsi_cmnd *p;
2532 struct scsi_cmnd *q;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2533 ips_copp_wait_item_t *item;
2534 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2535 struct Scsi_Host *host;
2536 METHOD_TRACE("ips_next", 1);
2537
2538 if (!ha)
2539 return;
2540 host = ips_sh[ha->host_num];
2541 /*
2542 * Block access to the queue function so
2543 * this command won't time out
2544 */
2545 if (intr == IPS_INTR_ON)
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]2546 spin_lock(host->host_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2547
2548 if ((ha->subsys->param[3] & 0x300000)
2549 && (ha->scb_activelist.count == 0)) {
Arnd Bergmannf990bee2018-04-20 18:04:40 +0200[diff] [blame]2550 time64_t now = ktime_get_real_seconds();
2551 if (now - ha->last_ffdc > IPS_SECS_8HOURS) {
2552 ha->last_ffdc = now;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2553 ips_ffdc_time(ha);
2554 }
2555 }
2556
2557 /*
2558 * Send passthru commands
2559 * These have priority over normal I/O
2560 * but shouldn't affect performance too much
2561 * since we limit the number that can be active
2562 * on the card at any one time
2563 */
2564 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2565 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2566
2567 item = ips_removeq_copp_head(&ha->copp_waitlist);
2568 ha->num_ioctl++;
2569 if (intr == IPS_INTR_ON)
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]2570 spin_unlock(host->host_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2571 scb->scsi_cmd = item->scsi_cmd;
2572 kfree(item);
2573
2574 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2575
2576 if (intr == IPS_INTR_ON)
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]2577 spin_lock(host->host_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2578 switch (ret) {
2579 case IPS_FAILURE:
2580 if (scb->scsi_cmd) {
2581 scb->scsi_cmd->result = DID_ERROR << 16;
2582 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2583 }
2584
2585 ips_freescb(ha, scb);
2586 break;
2587 case IPS_SUCCESS_IMM:
2588 if (scb->scsi_cmd) {
2589 scb->scsi_cmd->result = DID_OK << 16;
2590 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2591 }
2592
2593 ips_freescb(ha, scb);
2594 break;
2595 default:
2596 break;
2597 } /* end case */
2598
2599 if (ret != IPS_SUCCESS) {
2600 ha->num_ioctl--;
2601 continue;
2602 }
2603
2604 ret = ips_send_cmd(ha, scb);
2605
2606 if (ret == IPS_SUCCESS)
2607 ips_putq_scb_head(&ha->scb_activelist, scb);
2608 else
2609 ha->num_ioctl--;
2610
2611 switch (ret) {
2612 case IPS_FAILURE:
2613 if (scb->scsi_cmd) {
2614 scb->scsi_cmd->result = DID_ERROR << 16;
2615 }
2616
2617 ips_freescb(ha, scb);
2618 break;
2619 case IPS_SUCCESS_IMM:
2620 ips_freescb(ha, scb);
2621 break;
2622 default:
2623 break;
2624 } /* end case */
2625
2626 }
2627
2628 /*
2629 * Send "Normal" I/O commands
2630 */
2631
2632 p = ha->scb_waitlist.head;
2633 while ((p) && (scb = ips_getscb(ha))) {
Jeff Garzik422c0d62005-10-24 18:05:09 -0400[diff] [blame]2634 if ((scmd_channel(p) > 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2635 && (ha->
Jeff Garzik422c0d62005-10-24 18:05:09 -0400[diff] [blame]2636 dcdb_active[scmd_channel(p) -
2637 1] & (1 << scmd_id(p)))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2638 ips_freescb(ha, scb);
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]2639 p = (struct scsi_cmnd *) p->host_scribble;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2640 continue;
2641 }
2642
2643 q = p;
2644 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2645
2646 if (intr == IPS_INTR_ON)
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]2647 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2648
2649 SC->result = DID_OK;
2650 SC->host_scribble = NULL;
2651
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2652 scb->target_id = SC->device->id;
2653 scb->lun = SC->device->lun;
2654 scb->bus = SC->device->channel;
2655 scb->scsi_cmd = SC;
2656 scb->breakup = 0;
2657 scb->data_len = 0;
2658 scb->callback = ipsintr_done;
2659 scb->timeout = ips_cmd_timeout;
2660 memset(&scb->cmd, 0, 16);
2661
2662 /* copy in the CDB */
2663 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2664
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]2665 scb->sg_count = scsi_dma_map(SC);
2666 BUG_ON(scb->sg_count < 0);
2667 if (scb->sg_count) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2668 struct scatterlist *sg;
2669 int i;
2670
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2671 scb->flags |= IPS_SCB_MAP_SG;
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]2672
2673 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2674 if (ips_fill_scb_sg_single
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]2675 (ha, sg_dma_address(sg), scb, i,
2676 sg_dma_len(sg)) < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2677 break;
2678 }
2679 scb->dcdb.transfer_length = scb->data_len;
2680 } else {
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]2681 scb->data_busaddr = 0L;
2682 scb->sg_len = 0;
2683 scb->data_len = 0;
2684 scb->dcdb.transfer_length = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2685 }
2686
2687 scb->dcdb.cmd_attribute =
2688 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2689
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]2690 /* Allow a WRITE BUFFER Command to Have no Data */
2691 /* This is Used by Tape Flash Utilites */
2692 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2693 (scb->data_len == 0))
2694 scb->dcdb.cmd_attribute = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2695
2696 if (!(scb->dcdb.cmd_attribute & 0x3))
2697 scb->dcdb.transfer_length = 0;
2698
2699 if (scb->data_len >= IPS_MAX_XFER) {
2700 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2701 scb->dcdb.transfer_length = 0;
2702 }
2703 if (intr == IPS_INTR_ON)
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]2704 spin_lock(host->host_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2705
2706 ret = ips_send_cmd(ha, scb);
2707
2708 switch (ret) {
2709 case IPS_SUCCESS:
2710 ips_putq_scb_head(&ha->scb_activelist, scb);
2711 break;
2712 case IPS_FAILURE:
2713 if (scb->scsi_cmd) {
2714 scb->scsi_cmd->result = DID_ERROR << 16;
2715 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2716 }
2717
2718 if (scb->bus)
2719 ha->dcdb_active[scb->bus - 1] &=
2720 ~(1 << scb->target_id);
2721
2722 ips_freescb(ha, scb);
2723 break;
2724 case IPS_SUCCESS_IMM:
2725 if (scb->scsi_cmd)
2726 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2727
2728 if (scb->bus)
2729 ha->dcdb_active[scb->bus - 1] &=
2730 ~(1 << scb->target_id);
2731
2732 ips_freescb(ha, scb);
2733 break;
2734 default:
2735 break;
2736 } /* end case */
2737
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]2738 p = (struct scsi_cmnd *) p->host_scribble;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2739
2740 } /* end while */
2741
2742 if (intr == IPS_INTR_ON)
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]2743 spin_unlock(host->host_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2744}
2745
2746/****************************************************************************/
2747/* */
2748/* Routine Name: ips_putq_scb_head */
2749/* */
2750/* Routine Description: */
2751/* */
2752/* Add an item to the head of the queue */
2753/* */
2754/* ASSUMED to be called from within the HA lock */
2755/* */
2756/****************************************************************************/
2757static void
2758ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2759{
2760 METHOD_TRACE("ips_putq_scb_head", 1);
2761
2762 if (!item)
2763 return;
2764
2765 item->q_next = queue->head;
2766 queue->head = item;
2767
2768 if (!queue->tail)
2769 queue->tail = item;
2770
2771 queue->count++;
2772}
2773
2774/****************************************************************************/
2775/* */
2776/* Routine Name: ips_removeq_scb_head */
2777/* */
2778/* Routine Description: */
2779/* */
2780/* Remove the head of the queue */
2781/* */
2782/* ASSUMED to be called from within the HA lock */
2783/* */
2784/****************************************************************************/
2785static ips_scb_t *
2786ips_removeq_scb_head(ips_scb_queue_t * queue)
2787{
2788 ips_scb_t *item;
2789
2790 METHOD_TRACE("ips_removeq_scb_head", 1);
2791
2792 item = queue->head;
2793
2794 if (!item) {
2795 return (NULL);
2796 }
2797
2798 queue->head = item->q_next;
2799 item->q_next = NULL;
2800
2801 if (queue->tail == item)
2802 queue->tail = NULL;
2803
2804 queue->count--;
2805
2806 return (item);
2807}
2808
2809/****************************************************************************/
2810/* */
2811/* Routine Name: ips_removeq_scb */
2812/* */
2813/* Routine Description: */
2814/* */
2815/* Remove an item from a queue */
2816/* */
2817/* ASSUMED to be called from within the HA lock */
2818/* */
2819/****************************************************************************/
2820static ips_scb_t *
2821ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2822{
2823 ips_scb_t *p;
2824
2825 METHOD_TRACE("ips_removeq_scb", 1);
2826
2827 if (!item)
2828 return (NULL);
2829
2830 if (item == queue->head) {
2831 return (ips_removeq_scb_head(queue));
2832 }
2833
2834 p = queue->head;
2835
2836 while ((p) && (item != p->q_next))
2837 p = p->q_next;
2838
2839 if (p) {
2840 /* found a match */
2841 p->q_next = item->q_next;
2842
2843 if (!item->q_next)
2844 queue->tail = p;
2845
2846 item->q_next = NULL;
2847 queue->count--;
2848
2849 return (item);
2850 }
2851
2852 return (NULL);
2853}
2854
2855/****************************************************************************/
2856/* */
2857/* Routine Name: ips_putq_wait_tail */
2858/* */
2859/* Routine Description: */
2860/* */
2861/* Add an item to the tail of the queue */
2862/* */
2863/* ASSUMED to be called from within the HA lock */
2864/* */
2865/****************************************************************************/
Ingo Molnarac6424b2017-06-20 12:06:13 +0200[diff] [blame]2866static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2867{
2868 METHOD_TRACE("ips_putq_wait_tail", 1);
2869
2870 if (!item)
2871 return;
2872
2873 item->host_scribble = NULL;
2874
2875 if (queue->tail)
2876 queue->tail->host_scribble = (char *) item;
2877
2878 queue->tail = item;
2879
2880 if (!queue->head)
2881 queue->head = item;
2882
2883 queue->count++;
2884}
2885
2886/****************************************************************************/
2887/* */
2888/* Routine Name: ips_removeq_wait_head */
2889/* */
2890/* Routine Description: */
2891/* */
2892/* Remove the head of the queue */
2893/* */
2894/* ASSUMED to be called from within the HA lock */
2895/* */
2896/****************************************************************************/
Ingo Molnarac6424b2017-06-20 12:06:13 +0200[diff] [blame]2897static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2898{
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]2899 struct scsi_cmnd *item;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2900
2901 METHOD_TRACE("ips_removeq_wait_head", 1);
2902
2903 item = queue->head;
2904
2905 if (!item) {
2906 return (NULL);
2907 }
2908
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]2909 queue->head = (struct scsi_cmnd *) item->host_scribble;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2910 item->host_scribble = NULL;
2911
2912 if (queue->tail == item)
2913 queue->tail = NULL;
2914
2915 queue->count--;
2916
2917 return (item);
2918}
2919
2920/****************************************************************************/
2921/* */
2922/* Routine Name: ips_removeq_wait */
2923/* */
2924/* Routine Description: */
2925/* */
2926/* Remove an item from a queue */
2927/* */
2928/* ASSUMED to be called from within the HA lock */
2929/* */
2930/****************************************************************************/
Ingo Molnarac6424b2017-06-20 12:06:13 +0200[diff] [blame]2931static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue,
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]2932 struct scsi_cmnd *item)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2933{
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]2934 struct scsi_cmnd *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2935
2936 METHOD_TRACE("ips_removeq_wait", 1);
2937
2938 if (!item)
2939 return (NULL);
2940
2941 if (item == queue->head) {
2942 return (ips_removeq_wait_head(queue));
2943 }
2944
2945 p = queue->head;
2946
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]2947 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
2948 p = (struct scsi_cmnd *) p->host_scribble;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2949
2950 if (p) {
2951 /* found a match */
2952 p->host_scribble = item->host_scribble;
2953
2954 if (!item->host_scribble)
2955 queue->tail = p;
2956
2957 item->host_scribble = NULL;
2958 queue->count--;
2959
2960 return (item);
2961 }
2962
2963 return (NULL);
2964}
2965
2966/****************************************************************************/
2967/* */
2968/* Routine Name: ips_putq_copp_tail */
2969/* */
2970/* Routine Description: */
2971/* */
2972/* Add an item to the tail of the queue */
2973/* */
2974/* ASSUMED to be called from within the HA lock */
2975/* */
2976/****************************************************************************/
2977static void
2978ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
2979{
2980 METHOD_TRACE("ips_putq_copp_tail", 1);
2981
2982 if (!item)
2983 return;
2984
2985 item->next = NULL;
2986
2987 if (queue->tail)
2988 queue->tail->next = item;
2989
2990 queue->tail = item;
2991
2992 if (!queue->head)
2993 queue->head = item;
2994
2995 queue->count++;
2996}
2997
2998/****************************************************************************/
2999/* */
3000/* Routine Name: ips_removeq_copp_head */
3001/* */
3002/* Routine Description: */
3003/* */
3004/* Remove the head of the queue */
3005/* */
3006/* ASSUMED to be called from within the HA lock */
3007/* */
3008/****************************************************************************/
3009static ips_copp_wait_item_t *
3010ips_removeq_copp_head(ips_copp_queue_t * queue)
3011{
3012 ips_copp_wait_item_t *item;
3013
3014 METHOD_TRACE("ips_removeq_copp_head", 1);
3015
3016 item = queue->head;
3017
3018 if (!item) {
3019 return (NULL);
3020 }
3021
3022 queue->head = item->next;
3023 item->next = NULL;
3024
3025 if (queue->tail == item)
3026 queue->tail = NULL;
3027
3028 queue->count--;
3029
3030 return (item);
3031}
3032
3033/****************************************************************************/
3034/* */
3035/* Routine Name: ips_removeq_copp */
3036/* */
3037/* Routine Description: */
3038/* */
3039/* Remove an item from a queue */
3040/* */
3041/* ASSUMED to be called from within the HA lock */
3042/* */
3043/****************************************************************************/
3044static ips_copp_wait_item_t *
3045ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3046{
3047 ips_copp_wait_item_t *p;
3048
3049 METHOD_TRACE("ips_removeq_copp", 1);
3050
3051 if (!item)
3052 return (NULL);
3053
3054 if (item == queue->head) {
3055 return (ips_removeq_copp_head(queue));
3056 }
3057
3058 p = queue->head;
3059
3060 while ((p) && (item != p->next))
3061 p = p->next;
3062
3063 if (p) {
3064 /* found a match */
3065 p->next = item->next;
3066
3067 if (!item->next)
3068 queue->tail = p;
3069
3070 item->next = NULL;
3071 queue->count--;
3072
3073 return (item);
3074 }
3075
3076 return (NULL);
3077}
3078
3079/****************************************************************************/
3080/* */
3081/* Routine Name: ipsintr_blocking */
3082/* */
3083/* Routine Description: */
3084/* */
3085/* Finalize an interrupt for internal commands */
3086/* */
3087/****************************************************************************/
3088static void
3089ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3090{
3091 METHOD_TRACE("ipsintr_blocking", 2);
3092
3093 ips_freescb(ha, scb);
3094 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3095 ha->waitflag = FALSE;
3096
3097 return;
3098 }
3099}
3100
3101/****************************************************************************/
3102/* */
3103/* Routine Name: ipsintr_done */
3104/* */
3105/* Routine Description: */
3106/* */
3107/* Finalize an interrupt for non-internal commands */
3108/* */
3109/****************************************************************************/
3110static void
3111ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3112{
3113 METHOD_TRACE("ipsintr_done", 2);
3114
3115 if (!scb) {
3116 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3117 "Spurious interrupt; scb NULL.\n");
3118
3119 return;
3120 }
3121
3122 if (scb->scsi_cmd == NULL) {
3123 /* unexpected interrupt */
3124 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3125 "Spurious interrupt; scsi_cmd not set.\n");
3126
3127 return;
3128 }
3129
3130 ips_done(ha, scb);
3131}
3132
3133/****************************************************************************/
3134/* */
3135/* Routine Name: ips_done */
3136/* */
3137/* Routine Description: */
3138/* */
3139/* Do housekeeping on completed commands */
3140/* ASSUMED to be called form within the request lock */
3141/****************************************************************************/
3142static void
3143ips_done(ips_ha_t * ha, ips_scb_t * scb)
3144{
3145 int ret;
3146
3147 METHOD_TRACE("ips_done", 1);
3148
3149 if (!scb)
3150 return;
3151
3152 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3153 ips_cleanup_passthru(ha, scb);
3154 ha->num_ioctl--;
3155 } else {
3156 /*
3157 * Check to see if this command had too much
3158 * data and had to be broke up. If so, queue
3159 * the rest of the data and continue.
3160 */
3161 if ((scb->breakup) || (scb->sg_break)) {
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3162 struct scatterlist *sg;
FUJITA Tomonorie0eaf882007-07-16 15:24:14 +0200[diff] [blame]3163 int i, sg_dma_index, ips_sg_index = 0;
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3164
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3165 /* we had a data breakup */
3166 scb->data_len = 0;
3167
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3168 sg = scsi_sglist(scb->scsi_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3169
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3170 /* Spin forward to last dma chunk */
3171 sg_dma_index = scb->breakup;
FUJITA Tomonorie0eaf882007-07-16 15:24:14 +0200[diff] [blame]3172 for (i = 0; i < scb->breakup; i++)
3173 sg = sg_next(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3174
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3175 /* Take care of possible partial on last chunk */
3176 ips_fill_scb_sg_single(ha,
FUJITA Tomonorie0eaf882007-07-16 15:24:14 +0200[diff] [blame]3177 sg_dma_address(sg),
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3178 scb, ips_sg_index++,
FUJITA Tomonorie0eaf882007-07-16 15:24:14 +0200[diff] [blame]3179 sg_dma_len(sg));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3180
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3181 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
FUJITA Tomonorie0eaf882007-07-16 15:24:14 +0200[diff] [blame]3182 sg_dma_index++, sg = sg_next(sg)) {
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3183 if (ips_fill_scb_sg_single
3184 (ha,
FUJITA Tomonorie0eaf882007-07-16 15:24:14 +0200[diff] [blame]3185 sg_dma_address(sg),
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3186 scb, ips_sg_index++,
FUJITA Tomonorie0eaf882007-07-16 15:24:14 +0200[diff] [blame]3187 sg_dma_len(sg)) < 0)
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]3188 break;
3189 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3190
3191 scb->dcdb.transfer_length = scb->data_len;
3192 scb->dcdb.cmd_attribute |=
3193 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3194
3195 if (!(scb->dcdb.cmd_attribute & 0x3))
3196 scb->dcdb.transfer_length = 0;
3197
3198 if (scb->data_len >= IPS_MAX_XFER) {
3199 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3200 scb->dcdb.transfer_length = 0;
3201 }
3202
3203 ret = ips_send_cmd(ha, scb);
3204
3205 switch (ret) {
3206 case IPS_FAILURE:
3207 if (scb->scsi_cmd) {
3208 scb->scsi_cmd->result = DID_ERROR << 16;
3209 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3210 }
3211
3212 ips_freescb(ha, scb);
3213 break;
3214 case IPS_SUCCESS_IMM:
3215 if (scb->scsi_cmd) {
3216 scb->scsi_cmd->result = DID_ERROR << 16;
3217 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3218 }
3219
3220 ips_freescb(ha, scb);
3221 break;
3222 default:
3223 break;
3224 } /* end case */
3225
3226 return;
3227 }
3228 } /* end if passthru */
3229
3230 if (scb->bus) {
3231 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3232 }
3233
3234 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3235
3236 ips_freescb(ha, scb);
3237}
3238
3239/****************************************************************************/
3240/* */
3241/* Routine Name: ips_map_status */
3242/* */
3243/* Routine Description: */
3244/* */
3245/* Map Controller Error codes to Linux Error Codes */
3246/* */
3247/****************************************************************************/
3248static int
3249ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3250{
3251 int errcode;
3252 int device_error;
3253 uint32_t transfer_len;
3254 IPS_DCDB_TABLE_TAPE *tapeDCDB;
Jack Hammera5b3c862006-01-31 13:17:55 -0500[diff] [blame]3255 IPS_SCSI_INQ_DATA inquiryData;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3256
3257 METHOD_TRACE("ips_map_status", 1);
3258
3259 if (scb->bus) {
3260 DEBUG_VAR(2,
3261 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3262 ips_name, ha->host_num,
3263 scb->scsi_cmd->device->channel,
3264 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3265 scb->basic_status, scb->extended_status,
3266 scb->extended_status ==
3267 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3268 scb->extended_status ==
3269 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3270 scb->extended_status ==
3271 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3272 }
3273
3274 /* default driver error */
3275 errcode = DID_ERROR;
3276 device_error = 0;
3277
3278 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3279 case IPS_CMD_TIMEOUT:
3280 errcode = DID_TIME_OUT;
3281 break;
3282
3283 case IPS_INVAL_OPCO:
3284 case IPS_INVAL_CMD_BLK:
3285 case IPS_INVAL_PARM_BLK:
3286 case IPS_LD_ERROR:
3287 case IPS_CMD_CMPLT_WERROR:
3288 break;
3289
3290 case IPS_PHYS_DRV_ERROR:
3291 switch (scb->extended_status) {
3292 case IPS_ERR_SEL_TO:
3293 if (scb->bus)
3294 errcode = DID_NO_CONNECT;
3295
3296 break;
3297
3298 case IPS_ERR_OU_RUN:
3299 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3300 (scb->cmd.dcdb.op_code ==
3301 IPS_CMD_EXTENDED_DCDB_SG)) {
3302 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3303 transfer_len = tapeDCDB->transfer_length;
3304 } else {
3305 transfer_len =
3306 (uint32_t) scb->dcdb.transfer_length;
3307 }
3308
3309 if ((scb->bus) && (transfer_len < scb->data_len)) {
3310 /* Underrun - set default to no error */
3311 errcode = DID_OK;
3312
3313 /* Restrict access to physical DASD */
Jack Hammera5b3c862006-01-31 13:17:55 -0500[diff] [blame]3314 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]3315 ips_scmd_buf_read(scb->scsi_cmd,
Jack Hammera5b3c862006-01-31 13:17:55 -0500[diff] [blame]3316 &inquiryData, sizeof (inquiryData));
3317 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3318 errcode = DID_TIME_OUT;
3319 break;
3320 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3321 }
3322 } else
3323 errcode = DID_ERROR;
3324
3325 break;
3326
3327 case IPS_ERR_RECOVERY:
3328 /* don't fail recovered errors */
3329 if (scb->bus)
3330 errcode = DID_OK;
3331
3332 break;
3333
3334 case IPS_ERR_HOST_RESET:
3335 case IPS_ERR_DEV_RESET:
3336 errcode = DID_RESET;
3337 break;
3338
3339 case IPS_ERR_CKCOND:
3340 if (scb->bus) {
3341 if ((scb->cmd.dcdb.op_code ==
3342 IPS_CMD_EXTENDED_DCDB)
3343 || (scb->cmd.dcdb.op_code ==
3344 IPS_CMD_EXTENDED_DCDB_SG)) {
3345 tapeDCDB =
3346 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3347 memcpy(scb->scsi_cmd->sense_buffer,
3348 tapeDCDB->sense_info,
FUJITA Tomonorib80ca4f2008-01-13 15:46:13 +0900[diff] [blame]3349 SCSI_SENSE_BUFFERSIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3350 } else {
3351 memcpy(scb->scsi_cmd->sense_buffer,
3352 scb->dcdb.sense_info,
FUJITA Tomonorib80ca4f2008-01-13 15:46:13 +0900[diff] [blame]3353 SCSI_SENSE_BUFFERSIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3354 }
3355 device_error = 2; /* check condition */
3356 }
3357
3358 errcode = DID_OK;
3359
3360 break;
3361
3362 default:
3363 errcode = DID_ERROR;
3364 break;
3365
3366 } /* end switch */
3367 } /* end switch */
3368
3369 scb->scsi_cmd->result = device_error | (errcode << 16);
3370
3371 return (1);
3372}
3373
3374/****************************************************************************/
3375/* */
3376/* Routine Name: ips_send_wait */
3377/* */
3378/* Routine Description: */
3379/* */
3380/* Send a command to the controller and wait for it to return */
3381/* */
3382/* The FFDC Time Stamp use this function for the callback, but doesn't */
3383/* actually need to wait. */
3384/****************************************************************************/
3385static int
3386ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3387{
3388 int ret;
3389
3390 METHOD_TRACE("ips_send_wait", 1);
3391
3392 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3393 ha->waitflag = TRUE;
3394 ha->cmd_in_progress = scb->cdb[0];
3395 }
3396 scb->callback = ipsintr_blocking;
3397 ret = ips_send_cmd(ha, scb);
3398
3399 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3400 return (ret);
3401
3402 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3403 ret = ips_wait(ha, timeout, intr);
3404
3405 return (ret);
3406}
3407
3408/****************************************************************************/
3409/* */
3410/* Routine Name: ips_scmd_buf_write */
3411/* */
3412/* Routine Description: */
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]3413/* Write data to struct scsi_cmnd request_buffer at proper offsets */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3414/****************************************************************************/
3415static void
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]3416ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3417{
FUJITA Tomonori6690bae2008-03-09 13:44:33 +0900[diff] [blame]3418 unsigned long flags;
Jack Hammera3632fa2005-10-25 14:13:03 -0400[diff] [blame]3419
FUJITA Tomonori6690bae2008-03-09 13:44:33 +0900[diff] [blame]3420 local_irq_save(flags);
3421 scsi_sg_copy_from_buffer(scmd, data, count);
3422 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3423}
3424
3425/****************************************************************************/
3426/* */
3427/* Routine Name: ips_scmd_buf_read */
3428/* */
3429/* Routine Description: */
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]3430/* Copy data from a struct scsi_cmnd to a new, linear buffer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3431/****************************************************************************/
3432static void
Henne1516b552006-10-02 14:56:23 +0200[diff] [blame]3433ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3434{
FUJITA Tomonori6690bae2008-03-09 13:44:33 +0900[diff] [blame]3435 unsigned long flags;
Jack Hammera3632fa2005-10-25 14:13:03 -0400[diff] [blame]3436
FUJITA Tomonori6690bae2008-03-09 13:44:33 +0900[diff] [blame]3437 local_irq_save(flags);
3438 scsi_sg_copy_to_buffer(scmd, data, count);
3439 local_irq_restore(flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3440}
3441
3442/****************************************************************************/
3443/* */
3444/* Routine Name: ips_send_cmd */
3445/* */
3446/* Routine Description: */
3447/* */
3448/* Map SCSI commands to ServeRAID commands for logical drives */
3449/* */
3450/****************************************************************************/
3451static int
3452ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3453{
3454 int ret;
3455 char *sp;
3456 int device_error;
3457 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3458 int TimeOut;
3459
3460 METHOD_TRACE("ips_send_cmd", 1);
3461
3462 ret = IPS_SUCCESS;
3463
3464 if (!scb->scsi_cmd) {
3465 /* internal command */
3466
3467 if (scb->bus > 0) {
3468 /* Controller commands can't be issued */
3469 /* to real devices -- fail them */
3470 if ((ha->waitflag == TRUE) &&
3471 (ha->cmd_in_progress == scb->cdb[0])) {
3472 ha->waitflag = FALSE;
3473 }
3474
3475 return (1);
3476 }
3477 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3478 /* command to logical bus -- interpret */
3479 ret = IPS_SUCCESS_IMM;
3480
3481 switch (scb->scsi_cmd->cmnd[0]) {
3482 case ALLOW_MEDIUM_REMOVAL:
3483 case REZERO_UNIT:
3484 case ERASE:
3485 case WRITE_FILEMARKS:
3486 case SPACE:
3487 scb->scsi_cmd->result = DID_ERROR << 16;
3488 break;
3489
3490 case START_STOP:
3491 scb->scsi_cmd->result = DID_OK << 16;
Gustavo A. R. Silva5d25ff72018-10-16 11:12:23 +0200[diff] [blame]3492 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3493
3494 case TEST_UNIT_READY:
3495 case INQUIRY:
3496 if (scb->target_id == IPS_ADAPTER_ID) {
3497 /*
3498 * Either we have a TUR
3499 * or we have a SCSI inquiry
3500 */
3501 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3502 scb->scsi_cmd->result = DID_OK << 16;
3503
3504 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3505 IPS_SCSI_INQ_DATA inquiry;
3506
3507 memset(&inquiry, 0,
3508 sizeof (IPS_SCSI_INQ_DATA));
3509
3510 inquiry.DeviceType =
3511 IPS_SCSI_INQ_TYPE_PROCESSOR;
3512 inquiry.DeviceTypeQualifier =
3513 IPS_SCSI_INQ_LU_CONNECTED;
3514 inquiry.Version = IPS_SCSI_INQ_REV2;
3515 inquiry.ResponseDataFormat =
3516 IPS_SCSI_INQ_RD_REV2;
3517 inquiry.AdditionalLength = 31;
3518 inquiry.Flags[0] =
3519 IPS_SCSI_INQ_Address16;
3520 inquiry.Flags[1] =
3521 IPS_SCSI_INQ_WBus16 |
3522 IPS_SCSI_INQ_Sync;
Lee Jones00e24562020-07-23 13:24:19 +0100[diff] [blame]3523 memcpy(inquiry.VendorId, "IBM ",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3524 8);
Lee Jones00e24562020-07-23 13:24:19 +0100[diff] [blame]3525 memcpy(inquiry.ProductId,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3526 "SERVERAID ", 16);
Lee Jones00e24562020-07-23 13:24:19 +0100[diff] [blame]3527 memcpy(inquiry.ProductRevisionLevel,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3528 "1.00", 4);
3529
3530 ips_scmd_buf_write(scb->scsi_cmd,
3531 &inquiry,
3532 sizeof (inquiry));
3533
3534 scb->scsi_cmd->result = DID_OK << 16;
3535 }
3536 } else {
3537 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3538 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3539 scb->cmd.logical_info.reserved = 0;
3540 scb->cmd.logical_info.reserved2 = 0;
3541 scb->data_len = sizeof (IPS_LD_INFO);
3542 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3543 scb->flags = 0;
3544 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3545 ret = IPS_SUCCESS;
3546 }
3547
3548 break;
3549
3550 case REQUEST_SENSE:
3551 ips_reqsen(ha, scb);
3552 scb->scsi_cmd->result = DID_OK << 16;
3553 break;
3554
3555 case READ_6:
3556 case WRITE_6:
3557 if (!scb->sg_len) {
3558 scb->cmd.basic_io.op_code =
3559 (scb->scsi_cmd->cmnd[0] ==
3560 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3561 scb->cmd.basic_io.enhanced_sg = 0;
3562 scb->cmd.basic_io.sg_addr =
3563 cpu_to_le32(scb->data_busaddr);
3564 } else {
3565 scb->cmd.basic_io.op_code =
3566 (scb->scsi_cmd->cmnd[0] ==
3567 READ_6) ? IPS_CMD_READ_SG :
3568 IPS_CMD_WRITE_SG;
3569 scb->cmd.basic_io.enhanced_sg =
3570 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3571 scb->cmd.basic_io.sg_addr =
3572 cpu_to_le32(scb->sg_busaddr);
3573 }
3574
3575 scb->cmd.basic_io.segment_4G = 0;
3576 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3577 scb->cmd.basic_io.log_drv = scb->target_id;
3578 scb->cmd.basic_io.sg_count = scb->sg_len;
3579
3580 if (scb->cmd.basic_io.lba)
Marcin Slusarz36b8dd12008-03-28 14:48:35 -0700[diff] [blame]3581 le32_add_cpu(&scb->cmd.basic_io.lba,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3582 le16_to_cpu(scb->cmd.basic_io.
3583 sector_count));
3584 else
3585 scb->cmd.basic_io.lba =
3586 (((scb->scsi_cmd->
3587 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3588 cmnd[2] << 8) |
3589 (scb->scsi_cmd->cmnd[3]));
3590
3591 scb->cmd.basic_io.sector_count =
3592 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3593
3594 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3595 scb->cmd.basic_io.sector_count =
3596 cpu_to_le16(256);
3597
3598 ret = IPS_SUCCESS;
3599 break;
3600
3601 case READ_10:
3602 case WRITE_10:
3603 if (!scb->sg_len) {
3604 scb->cmd.basic_io.op_code =
3605 (scb->scsi_cmd->cmnd[0] ==
3606 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3607 scb->cmd.basic_io.enhanced_sg = 0;
3608 scb->cmd.basic_io.sg_addr =
3609 cpu_to_le32(scb->data_busaddr);
3610 } else {
3611 scb->cmd.basic_io.op_code =
3612 (scb->scsi_cmd->cmnd[0] ==
3613 READ_10) ? IPS_CMD_READ_SG :
3614 IPS_CMD_WRITE_SG;
3615 scb->cmd.basic_io.enhanced_sg =
3616 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3617 scb->cmd.basic_io.sg_addr =
3618 cpu_to_le32(scb->sg_busaddr);
3619 }
3620
3621 scb->cmd.basic_io.segment_4G = 0;
3622 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3623 scb->cmd.basic_io.log_drv = scb->target_id;
3624 scb->cmd.basic_io.sg_count = scb->sg_len;
3625
3626 if (scb->cmd.basic_io.lba)
Marcin Slusarz36b8dd12008-03-28 14:48:35 -0700[diff] [blame]3627 le32_add_cpu(&scb->cmd.basic_io.lba,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3628 le16_to_cpu(scb->cmd.basic_io.
3629 sector_count));
3630 else
3631 scb->cmd.basic_io.lba =
3632 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3633 scsi_cmd->
3634 cmnd[3]
3635 << 16) |
3636 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3637 scsi_cmd->cmnd[5]);
3638
3639 scb->cmd.basic_io.sector_count =
3640 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3641
3642 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3643 /*
3644 * This is a null condition
3645 * we don't have to do anything
3646 * so just return
3647 */
3648 scb->scsi_cmd->result = DID_OK << 16;
3649 } else
3650 ret = IPS_SUCCESS;
3651
3652 break;
3653
3654 case RESERVE:
3655 case RELEASE:
3656 scb->scsi_cmd->result = DID_OK << 16;
3657 break;
3658
3659 case MODE_SENSE:
3660 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3661 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3662 scb->cmd.basic_io.segment_4G = 0;
3663 scb->cmd.basic_io.enhanced_sg = 0;
3664 scb->data_len = sizeof (*ha->enq);
3665 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3666 ret = IPS_SUCCESS;
3667 break;
3668
3669 case READ_CAPACITY:
3670 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3671 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3672 scb->cmd.logical_info.reserved = 0;
3673 scb->cmd.logical_info.reserved2 = 0;
3674 scb->cmd.logical_info.reserved3 = 0;
3675 scb->data_len = sizeof (IPS_LD_INFO);
3676 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3677 scb->flags = 0;
3678 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3679 ret = IPS_SUCCESS;
3680 break;
3681
3682 case SEND_DIAGNOSTIC:
3683 case REASSIGN_BLOCKS:
3684 case FORMAT_UNIT:
3685 case SEEK_10:
3686 case VERIFY:
3687 case READ_DEFECT_DATA:
3688 case READ_BUFFER:
3689 case WRITE_BUFFER:
3690 scb->scsi_cmd->result = DID_OK << 16;
3691 break;
3692
3693 default:
3694 /* Set the Return Info to appear like the Command was */
3695 /* attempted, a Check Condition occurred, and Sense */
3696 /* Data indicating an Invalid CDB OpCode is returned. */
3697 sp = (char *) scb->scsi_cmd->sense_buffer;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3698
3699 sp[0] = 0x70; /* Error Code */
3700 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3701 sp[7] = 0x0A; /* Additional Sense Length */
3702 sp[12] = 0x20; /* ASC = Invalid OpCode */
3703 sp[13] = 0x00; /* ASCQ */
3704
3705 device_error = 2; /* Indicate Check Condition */
3706 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3707 break;
3708 } /* end switch */
3709 }
3710 /* end if */
3711 if (ret == IPS_SUCCESS_IMM)
3712 return (ret);
3713
3714 /* setup DCDB */
3715 if (scb->bus > 0) {
3716
3717 /* If we already know the Device is Not there, no need to attempt a Command */
3718 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3719 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3720 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3721 return (IPS_SUCCESS_IMM);
3722 }
3723
3724 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3725 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3726 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3727 (unsigned long) &scb->
3728 dcdb -
3729 (unsigned long) scb);
3730 scb->cmd.dcdb.reserved = 0;
3731 scb->cmd.dcdb.reserved2 = 0;
3732 scb->cmd.dcdb.reserved3 = 0;
3733 scb->cmd.dcdb.segment_4G = 0;
3734 scb->cmd.dcdb.enhanced_sg = 0;
3735
Jens Axboe242f9dc2008-09-14 05:55:09 -0700[diff] [blame]3736 TimeOut = scb->scsi_cmd->request->timeout;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3737
3738 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3739 if (!scb->sg_len) {
3740 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3741 } else {
3742 scb->cmd.dcdb.op_code =
3743 IPS_CMD_EXTENDED_DCDB_SG;
3744 scb->cmd.dcdb.enhanced_sg =
3745 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3746 }
3747
3748 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3749 tapeDCDB->device_address =
3750 ((scb->bus - 1) << 4) | scb->target_id;
3751 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3752 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
3753
3754 if (TimeOut) {
3755 if (TimeOut < (10 * HZ))
3756 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3757 else if (TimeOut < (60 * HZ))
3758 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3759 else if (TimeOut < (1200 * HZ))
3760 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3761 }
3762
3763 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3764 tapeDCDB->reserved_for_LUN = 0;
3765 tapeDCDB->transfer_length = scb->data_len;
3766 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3767 tapeDCDB->buffer_pointer =
3768 cpu_to_le32(scb->sg_busaddr);
3769 else
3770 tapeDCDB->buffer_pointer =
3771 cpu_to_le32(scb->data_busaddr);
3772 tapeDCDB->sg_count = scb->sg_len;
3773 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3774 tapeDCDB->scsi_status = 0;
3775 tapeDCDB->reserved = 0;
3776 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3777 scb->scsi_cmd->cmd_len);
3778 } else {
3779 if (!scb->sg_len) {
3780 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3781 } else {
3782 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3783 scb->cmd.dcdb.enhanced_sg =
3784 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3785 }
3786
3787 scb->dcdb.device_address =
3788 ((scb->bus - 1) << 4) | scb->target_id;
3789 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3790
3791 if (TimeOut) {
3792 if (TimeOut < (10 * HZ))
3793 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3794 else if (TimeOut < (60 * HZ))
3795 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3796 else if (TimeOut < (1200 * HZ))
3797 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3798 }
3799
3800 scb->dcdb.transfer_length = scb->data_len;
3801 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3802 scb->dcdb.transfer_length = 0;
3803 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3804 scb->dcdb.buffer_pointer =
3805 cpu_to_le32(scb->sg_busaddr);
3806 else
3807 scb->dcdb.buffer_pointer =
3808 cpu_to_le32(scb->data_busaddr);
3809 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3810 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3811 scb->dcdb.sg_count = scb->sg_len;
3812 scb->dcdb.reserved = 0;
3813 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3814 scb->scsi_cmd->cmd_len);
3815 scb->dcdb.scsi_status = 0;
3816 scb->dcdb.reserved2[0] = 0;
3817 scb->dcdb.reserved2[1] = 0;
3818 scb->dcdb.reserved2[2] = 0;
3819 }
3820 }
3821
3822 return ((*ha->func.issue) (ha, scb));
3823}
3824
3825/****************************************************************************/
3826/* */
3827/* Routine Name: ips_chk_status */
3828/* */
3829/* Routine Description: */
3830/* */
3831/* Check the status of commands to logical drives */
3832/* Assumed to be called with the HA lock */
3833/****************************************************************************/
3834static void
3835ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3836{
3837 ips_scb_t *scb;
3838 ips_stat_t *sp;
3839 uint8_t basic_status;
3840 uint8_t ext_status;
3841 int errcode;
Jack Hammera5b3c862006-01-31 13:17:55 -0500[diff] [blame]3842 IPS_SCSI_INQ_DATA inquiryData;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3843
3844 METHOD_TRACE("ips_chkstatus", 1);
3845
3846 scb = &ha->scbs[pstatus->fields.command_id];
3847 scb->basic_status = basic_status =
3848 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3849 scb->extended_status = ext_status = pstatus->fields.extended_status;
3850
3851 sp = &ha->sp;
3852 sp->residue_len = 0;
3853 sp->scb_addr = (void *) scb;
3854
3855 /* Remove the item from the active queue */
3856 ips_removeq_scb(&ha->scb_activelist, scb);
3857
3858 if (!scb->scsi_cmd)
3859 /* internal commands are handled in do_ipsintr */
3860 return;
3861
3862 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3863 ips_name,
3864 ha->host_num,
3865 scb->cdb[0],
3866 scb->cmd.basic_io.command_id,
3867 scb->bus, scb->target_id, scb->lun);
3868
3869 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3870 /* passthru - just returns the raw result */
3871 return;
3872
3873 errcode = DID_OK;
3874
3875 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3876 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3877
3878 if (scb->bus == 0) {
3879 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3880 IPS_CMD_RECOVERED_ERROR) {
3881 DEBUG_VAR(1,
3882 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3883 ips_name, ha->host_num,
3884 scb->cmd.basic_io.op_code,
3885 basic_status, ext_status);
3886 }
3887
3888 switch (scb->scsi_cmd->cmnd[0]) {
3889 case ALLOW_MEDIUM_REMOVAL:
3890 case REZERO_UNIT:
3891 case ERASE:
3892 case WRITE_FILEMARKS:
3893 case SPACE:
3894 errcode = DID_ERROR;
3895 break;
3896
3897 case START_STOP:
3898 break;
3899
3900 case TEST_UNIT_READY:
3901 if (!ips_online(ha, scb)) {
3902 errcode = DID_TIME_OUT;
3903 }
3904 break;
3905
3906 case INQUIRY:
3907 if (ips_online(ha, scb)) {
3908 ips_inquiry(ha, scb);
3909 } else {
3910 errcode = DID_TIME_OUT;
3911 }
3912 break;
3913
3914 case REQUEST_SENSE:
3915 ips_reqsen(ha, scb);
3916 break;
3917
3918 case READ_6:
3919 case WRITE_6:
3920 case READ_10:
3921 case WRITE_10:
3922 case RESERVE:
3923 case RELEASE:
3924 break;
3925
3926 case MODE_SENSE:
3927 if (!ips_online(ha, scb)
3928 || !ips_msense(ha, scb)) {
3929 errcode = DID_ERROR;
3930 }
3931 break;
3932
3933 case READ_CAPACITY:
3934 if (ips_online(ha, scb))
3935 ips_rdcap(ha, scb);
3936 else {
3937 errcode = DID_TIME_OUT;
3938 }
3939 break;
3940
3941 case SEND_DIAGNOSTIC:
3942 case REASSIGN_BLOCKS:
3943 break;
3944
3945 case FORMAT_UNIT:
3946 errcode = DID_ERROR;
3947 break;
3948
3949 case SEEK_10:
3950 case VERIFY:
3951 case READ_DEFECT_DATA:
3952 case READ_BUFFER:
3953 case WRITE_BUFFER:
3954 break;
3955
3956 default:
3957 errcode = DID_ERROR;
3958 } /* end switch */
3959
3960 scb->scsi_cmd->result = errcode << 16;
3961 } else { /* bus == 0 */
3962 /* restrict access to physical drives */
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]3963 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3964 ips_scmd_buf_read(scb->scsi_cmd,
Jack Hammera5b3c862006-01-31 13:17:55 -0500[diff] [blame]3965 &inquiryData, sizeof (inquiryData));
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]3966 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
Jack Hammera5b3c862006-01-31 13:17:55 -0500[diff] [blame]3967 scb->scsi_cmd->result = DID_TIME_OUT << 16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3968 }
3969 } /* else */
3970 } else { /* recovered error / success */
3971 if (scb->bus == 0) {
3972 DEBUG_VAR(1,
3973 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3974 ips_name, ha->host_num,
3975 scb->cmd.basic_io.op_code, basic_status,
3976 ext_status);
3977 }
3978
3979 ips_map_status(ha, scb, sp);
3980 } /* else */
3981}
3982
3983/****************************************************************************/
3984/* */
3985/* Routine Name: ips_online */
3986/* */
3987/* Routine Description: */
3988/* */
3989/* Determine if a logical drive is online */
3990/* */
3991/****************************************************************************/
3992static int
3993ips_online(ips_ha_t * ha, ips_scb_t * scb)
3994{
3995 METHOD_TRACE("ips_online", 1);
3996
3997 if (scb->target_id >= IPS_MAX_LD)
3998 return (0);
3999
4000 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4001 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4002 return (0);
4003 }
4004
4005 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4006 IPS_LD_OFFLINE
4007 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4008 IPS_LD_FREE
4009 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4010 IPS_LD_CRS
4011 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4012 IPS_LD_SYS)
4013 return (1);
4014 else
4015 return (0);
4016}
4017
4018/****************************************************************************/
4019/* */
4020/* Routine Name: ips_inquiry */
4021/* */
4022/* Routine Description: */
4023/* */
4024/* Simulate an inquiry command to a logical drive */
4025/* */
4026/****************************************************************************/
4027static int
4028ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4029{
4030 IPS_SCSI_INQ_DATA inquiry;
4031
4032 METHOD_TRACE("ips_inquiry", 1);
4033
4034 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4035
4036 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4037 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4038 inquiry.Version = IPS_SCSI_INQ_REV2;
4039 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4040 inquiry.AdditionalLength = 31;
4041 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4042 inquiry.Flags[1] =
4043 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
Lee Jones00e24562020-07-23 13:24:19 +0100[diff] [blame]4044 memcpy(inquiry.VendorId, "IBM ", 8);
4045 memcpy(inquiry.ProductId, "SERVERAID ", 16);
4046 memcpy(inquiry.ProductRevisionLevel, "1.00", 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4047
4048 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4049
4050 return (1);
4051}
4052
4053/****************************************************************************/
4054/* */
4055/* Routine Name: ips_rdcap */
4056/* */
4057/* Routine Description: */
4058/* */
4059/* Simulate a read capacity command to a logical drive */
4060/* */
4061/****************************************************************************/
4062static int
4063ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4064{
4065 IPS_SCSI_CAPACITY cap;
4066
4067 METHOD_TRACE("ips_rdcap", 1);
4068
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]4069 if (scsi_bufflen(scb->scsi_cmd) < 8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4070 return (0);
4071
4072 cap.lba =
4073 cpu_to_be32(le32_to_cpu
4074 (ha->logical_drive_info->
4075 drive_info[scb->target_id].sector_count) - 1);
4076 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4077
4078 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4079
4080 return (1);
4081}
4082
4083/****************************************************************************/
4084/* */
4085/* Routine Name: ips_msense */
4086/* */
4087/* Routine Description: */
4088/* */
4089/* Simulate a mode sense command to a logical drive */
4090/* */
4091/****************************************************************************/
4092static int
4093ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4094{
4095 uint16_t heads;
4096 uint16_t sectors;
4097 uint32_t cylinders;
4098 IPS_SCSI_MODE_PAGE_DATA mdata;
4099
4100 METHOD_TRACE("ips_msense", 1);
4101
4102 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4103 (ha->enq->ucMiscFlag & 0x8) == 0) {
4104 heads = IPS_NORM_HEADS;
4105 sectors = IPS_NORM_SECTORS;
4106 } else {
4107 heads = IPS_COMP_HEADS;
4108 sectors = IPS_COMP_SECTORS;
4109 }
4110
4111 cylinders =
4112 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4113 1) / (heads * sectors);
4114
4115 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4116
4117 mdata.hdr.BlockDescLength = 8;
4118
4119 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4120 case 0x03: /* page 3 */
4121 mdata.pdata.pg3.PageCode = 3;
4122 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4123 mdata.hdr.DataLength =
4124 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4125 mdata.pdata.pg3.TracksPerZone = 0;
4126 mdata.pdata.pg3.AltSectorsPerZone = 0;
4127 mdata.pdata.pg3.AltTracksPerZone = 0;
4128 mdata.pdata.pg3.AltTracksPerVolume = 0;
4129 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4130 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4131 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4132 mdata.pdata.pg3.TrackSkew = 0;
4133 mdata.pdata.pg3.CylinderSkew = 0;
4134 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4135 break;
4136
4137 case 0x4:
4138 mdata.pdata.pg4.PageCode = 4;
4139 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4140 mdata.hdr.DataLength =
4141 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4142 mdata.pdata.pg4.CylindersHigh =
4143 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4144 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4145 mdata.pdata.pg4.Heads = heads;
4146 mdata.pdata.pg4.WritePrecompHigh = 0;
4147 mdata.pdata.pg4.WritePrecompLow = 0;
4148 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4149 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4150 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4151 mdata.pdata.pg4.LandingZoneHigh = 0;
4152 mdata.pdata.pg4.LandingZoneLow = 0;
4153 mdata.pdata.pg4.flags = 0;
4154 mdata.pdata.pg4.RotationalOffset = 0;
4155 mdata.pdata.pg4.MediumRotationRate = 0;
4156 break;
4157 case 0x8:
4158 mdata.pdata.pg8.PageCode = 8;
4159 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4160 mdata.hdr.DataLength =
4161 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4162 /* everything else is left set to 0 */
4163 break;
4164
4165 default:
4166 return (0);
4167 } /* end switch */
4168
4169 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4170
4171 return (1);
4172}
4173
4174/****************************************************************************/
4175/* */
4176/* Routine Name: ips_reqsen */
4177/* */
4178/* Routine Description: */
4179/* */
4180/* Simulate a request sense command to a logical drive */
4181/* */
4182/****************************************************************************/
4183static int
4184ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4185{
4186 IPS_SCSI_REQSEN reqsen;
4187
4188 METHOD_TRACE("ips_reqsen", 1);
4189
4190 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4191
4192 reqsen.ResponseCode =
4193 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4194 reqsen.AdditionalLength = 10;
4195 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4196 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4197
4198 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4199
4200 return (1);
4201}
4202
4203/****************************************************************************/
4204/* */
4205/* Routine Name: ips_free */
4206/* */
4207/* Routine Description: */
4208/* */
4209/* Free any allocated space for this controller */
4210/* */
4211/****************************************************************************/
4212static void
4213ips_free(ips_ha_t * ha)
4214{
4215
4216 METHOD_TRACE("ips_free", 1);
4217
4218 if (ha) {
4219 if (ha->enq) {
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4220 dma_free_coherent(&ha->pcidev->dev, sizeof(IPS_ENQ),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4221 ha->enq, ha->enq_busaddr);
4222 ha->enq = NULL;
4223 }
4224
Jesper Juhlc9475cb2005-11-07 01:01:26 -0800[diff] [blame]4225 kfree(ha->conf);
4226 ha->conf = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4227
4228 if (ha->adapt) {
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4229 dma_free_coherent(&ha->pcidev->dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4230 sizeof (IPS_ADAPTER) +
4231 sizeof (IPS_IO_CMD), ha->adapt,
4232 ha->adapt->hw_status_start);
4233 ha->adapt = NULL;
4234 }
4235
4236 if (ha->logical_drive_info) {
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4237 dma_free_coherent(&ha->pcidev->dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4238 sizeof (IPS_LD_INFO),
4239 ha->logical_drive_info,
4240 ha->logical_drive_info_dma_addr);
4241 ha->logical_drive_info = NULL;
4242 }
4243
Jesper Juhlc9475cb2005-11-07 01:01:26 -0800[diff] [blame]4244 kfree(ha->nvram);
4245 ha->nvram = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4246
Jesper Juhlc9475cb2005-11-07 01:01:26 -0800[diff] [blame]4247 kfree(ha->subsys);
4248 ha->subsys = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4249
4250 if (ha->ioctl_data) {
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4251 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4252 ha->ioctl_data, ha->ioctl_busaddr);
4253 ha->ioctl_data = NULL;
4254 ha->ioctl_datasize = 0;
4255 ha->ioctl_len = 0;
4256 }
4257 ips_deallocatescbs(ha, ha->max_cmds);
4258
4259 /* free memory mapped (if applicable) */
4260 if (ha->mem_ptr) {
4261 iounmap(ha->ioremap_ptr);
4262 ha->ioremap_ptr = NULL;
4263 ha->mem_ptr = NULL;
4264 }
4265
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4266 ha->mem_addr = 0;
4267
4268 }
4269}
4270
4271/****************************************************************************/
4272/* */
4273/* Routine Name: ips_deallocatescbs */
4274/* */
4275/* Routine Description: */
4276/* */
4277/* Free the command blocks */
4278/* */
4279/****************************************************************************/
4280static int
4281ips_deallocatescbs(ips_ha_t * ha, int cmds)
4282{
4283 if (ha->scbs) {
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4284 dma_free_coherent(&ha->pcidev->dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4285 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4286 ha->scbs->sg_list.list,
4287 ha->scbs->sg_busaddr);
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4288 dma_free_coherent(&ha->pcidev->dev, sizeof (ips_scb_t) * cmds,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4289 ha->scbs, ha->scbs->scb_busaddr);
4290 ha->scbs = NULL;
4291 } /* end if */
4292 return 1;
4293}
4294
4295/****************************************************************************/
4296/* */
4297/* Routine Name: ips_allocatescbs */
4298/* */
4299/* Routine Description: */
4300/* */
4301/* Allocate the command blocks */
4302/* */
4303/****************************************************************************/
4304static int
4305ips_allocatescbs(ips_ha_t * ha)
4306{
4307 ips_scb_t *scb_p;
4308 IPS_SG_LIST ips_sg;
4309 int i;
4310 dma_addr_t command_dma, sg_dma;
4311
4312 METHOD_TRACE("ips_allocatescbs", 1);
4313
4314 /* Allocate memory for the SCBs */
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4315 ha->scbs = dma_alloc_coherent(&ha->pcidev->dev,
4316 ha->max_cmds * sizeof (ips_scb_t),
4317 &command_dma, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4318 if (ha->scbs == NULL)
4319 return 0;
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4320 ips_sg.list = dma_alloc_coherent(&ha->pcidev->dev,
4321 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * ha->max_cmds,
4322 &sg_dma, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4323 if (ips_sg.list == NULL) {
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4324 dma_free_coherent(&ha->pcidev->dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4325 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4326 command_dma);
4327 return 0;
4328 }
4329
4330 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4331
4332 for (i = 0; i < ha->max_cmds; i++) {
4333 scb_p = &ha->scbs[i];
4334 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4335 /* set up S/G list */
4336 if (IPS_USE_ENH_SGLIST(ha)) {
4337 scb_p->sg_list.enh_list =
4338 ips_sg.enh_list + i * IPS_MAX_SG;
4339 scb_p->sg_busaddr =
4340 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4341 } else {
4342 scb_p->sg_list.std_list =
4343 ips_sg.std_list + i * IPS_MAX_SG;
4344 scb_p->sg_busaddr =
4345 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4346 }
4347
4348 /* add to the free list */
4349 if (i < ha->max_cmds - 1) {
4350 scb_p->q_next = ha->scb_freelist;
4351 ha->scb_freelist = scb_p;
4352 }
4353 }
4354
4355 /* success */
4356 return (1);
4357}
4358
4359/****************************************************************************/
4360/* */
4361/* Routine Name: ips_init_scb */
4362/* */
4363/* Routine Description: */
4364/* */
4365/* Initialize a CCB to default values */
4366/* */
4367/****************************************************************************/
4368static void
4369ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4370{
4371 IPS_SG_LIST sg_list;
4372 uint32_t cmd_busaddr, sg_busaddr;
4373 METHOD_TRACE("ips_init_scb", 1);
4374
4375 if (scb == NULL)
4376 return;
4377
4378 sg_list.list = scb->sg_list.list;
4379 cmd_busaddr = scb->scb_busaddr;
4380 sg_busaddr = scb->sg_busaddr;
4381 /* zero fill */
4382 memset(scb, 0, sizeof (ips_scb_t));
4383 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4384
4385 /* Initialize dummy command bucket */
4386 ha->dummy->op_code = 0xFF;
4387 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4388 + sizeof (IPS_ADAPTER));
4389 ha->dummy->command_id = IPS_MAX_CMDS;
4390
4391 /* set bus address of scb */
4392 scb->scb_busaddr = cmd_busaddr;
4393 scb->sg_busaddr = sg_busaddr;
4394 scb->sg_list.list = sg_list.list;
4395
4396 /* Neptune Fix */
4397 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4398 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4399 + sizeof (IPS_ADAPTER));
4400}
4401
4402/****************************************************************************/
4403/* */
4404/* Routine Name: ips_get_scb */
4405/* */
4406/* Routine Description: */
4407/* */
4408/* Initialize a CCB to default values */
4409/* */
Justin P. Mattock42b2aa82011-11-28 20:31:00 -0800[diff] [blame]4410/* ASSUMED to be called from within a lock */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4411/* */
4412/****************************************************************************/
4413static ips_scb_t *
4414ips_getscb(ips_ha_t * ha)
4415{
4416 ips_scb_t *scb;
4417
4418 METHOD_TRACE("ips_getscb", 1);
4419
4420 if ((scb = ha->scb_freelist) == NULL) {
4421
4422 return (NULL);
4423 }
4424
4425 ha->scb_freelist = scb->q_next;
4426 scb->flags = 0;
4427 scb->q_next = NULL;
4428
4429 ips_init_scb(ha, scb);
4430
4431 return (scb);
4432}
4433
4434/****************************************************************************/
4435/* */
4436/* Routine Name: ips_free_scb */
4437/* */
4438/* Routine Description: */
4439/* */
4440/* Return an unused CCB back to the free list */
4441/* */
4442/* ASSUMED to be called from within a lock */
4443/* */
4444/****************************************************************************/
4445static void
4446ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4447{
4448
4449 METHOD_TRACE("ips_freescb", 1);
4450 if (scb->flags & IPS_SCB_MAP_SG)
FUJITA Tomonori2f4cf912007-06-13 23:27:09 +0900[diff] [blame]4451 scsi_dma_unmap(scb->scsi_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4452 else if (scb->flags & IPS_SCB_MAP_SINGLE)
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4453 dma_unmap_single(&ha->pcidev->dev, scb->data_busaddr,
4454 scb->data_len, IPS_DMA_DIR(scb));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4455
4456 /* check to make sure this is not our "special" scb */
4457 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4458 scb->q_next = ha->scb_freelist;
4459 ha->scb_freelist = scb;
4460 }
4461}
4462
4463/****************************************************************************/
4464/* */
4465/* Routine Name: ips_isinit_copperhead */
4466/* */
4467/* Routine Description: */
4468/* */
4469/* Is controller initialized ? */
4470/* */
4471/****************************************************************************/
4472static int
4473ips_isinit_copperhead(ips_ha_t * ha)
4474{
4475 uint8_t scpr;
4476 uint8_t isr;
4477
4478 METHOD_TRACE("ips_isinit_copperhead", 1);
4479
4480 isr = inb(ha->io_addr + IPS_REG_HISR);
4481 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4482
4483 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4484 return (0);
4485 else
4486 return (1);
4487}
4488
4489/****************************************************************************/
4490/* */
4491/* Routine Name: ips_isinit_copperhead_memio */
4492/* */
4493/* Routine Description: */
4494/* */
4495/* Is controller initialized ? */
4496/* */
4497/****************************************************************************/
4498static int
4499ips_isinit_copperhead_memio(ips_ha_t * ha)
4500{
4501 uint8_t isr = 0;
4502 uint8_t scpr;
4503
4504 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4505
4506 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4507 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4508
4509 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4510 return (0);
4511 else
4512 return (1);
4513}
4514
4515/****************************************************************************/
4516/* */
4517/* Routine Name: ips_isinit_morpheus */
4518/* */
4519/* Routine Description: */
4520/* */
4521/* Is controller initialized ? */
4522/* */
4523/****************************************************************************/
4524static int
4525ips_isinit_morpheus(ips_ha_t * ha)
4526{
4527 uint32_t post;
4528 uint32_t bits;
4529
4530 METHOD_TRACE("ips_is_init_morpheus", 1);
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]4531
4532 if (ips_isintr_morpheus(ha))
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4533 ips_flush_and_reset(ha);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4534
4535 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4536 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4537
4538 if (post == 0)
4539 return (0);
4540 else if (bits & 0x3)
4541 return (0);
4542 else
4543 return (1);
4544}
4545
4546/****************************************************************************/
4547/* */
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4548/* Routine Name: ips_flush_and_reset */
4549/* */
4550/* Routine Description: */
4551/* */
4552/* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */
4553/* state ( was trying to INIT and an interrupt was already pending ) ... */
4554/* */
4555/****************************************************************************/
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]4556static void
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4557ips_flush_and_reset(ips_ha_t *ha)
4558{
4559 ips_scb_t *scb;
4560 int ret;
4561 int time;
4562 int done;
4563 dma_addr_t command_dma;
4564
4565 /* Create a usuable SCB */
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4566 scb = dma_alloc_coherent(&ha->pcidev->dev, sizeof(ips_scb_t),
4567 &command_dma, GFP_KERNEL);
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4568 if (scb) {
4569 memset(scb, 0, sizeof(ips_scb_t));
4570 ips_init_scb(ha, scb);
4571 scb->scb_busaddr = command_dma;
4572
4573 scb->timeout = ips_cmd_timeout;
4574 scb->cdb[0] = IPS_CMD_FLUSH;
4575
4576 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4577 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */
4578 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4579 scb->cmd.flush_cache.reserved = 0;
4580 scb->cmd.flush_cache.reserved2 = 0;
4581 scb->cmd.flush_cache.reserved3 = 0;
4582 scb->cmd.flush_cache.reserved4 = 0;
4583
4584 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4585
4586 if (ret == IPS_SUCCESS) {
4587 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4588 done = 0;
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]4589
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4590 while ((time > 0) && (!done)) {
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]4591 done = ips_poll_for_flush_complete(ha);
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4592 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4593 udelay(1000);
4594 time--;
4595 }
4596 }
4597 }
4598
4599 /* Now RESET and INIT the adapter */
4600 (*ha->func.reset) (ha);
4601
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]4602 dma_free_coherent(&ha->pcidev->dev, sizeof(ips_scb_t), scb, command_dma);
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4603 return;
4604}
4605
4606/****************************************************************************/
4607/* */
4608/* Routine Name: ips_poll_for_flush_complete */
4609/* */
4610/* Routine Description: */
4611/* */
4612/* Poll for the Flush Command issued by ips_flush_and_reset() to complete */
4613/* All other responses are just taken off the queue and ignored */
4614/* */
4615/****************************************************************************/
4616static int
4617ips_poll_for_flush_complete(ips_ha_t * ha)
4618{
4619 IPS_STATUS cstatus;
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]4620
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4621 while (TRUE) {
4622 cstatus.value = (*ha->func.statupd) (ha);
4623
4624 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4625 break;
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]4626
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4627 /* Success is when we see the Flush Command ID */
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]4628 if (cstatus.fields.command_id == IPS_MAX_CMDS)
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4629 return 1;
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]4630 }
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4631
4632 return 0;
James Bottomley0ee957c2005-11-04 23:22:55 -0600[diff] [blame]4633}
Jack Hammeree807c22005-08-29 10:44:34 -0400[diff] [blame]4634
4635/****************************************************************************/
4636/* */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4637/* Routine Name: ips_enable_int_copperhead */
4638/* */
4639/* Routine Description: */
4640/* Turn on interrupts */
4641/* */
4642/****************************************************************************/
4643static void
4644ips_enable_int_copperhead(ips_ha_t * ha)
4645{
4646 METHOD_TRACE("ips_enable_int_copperhead", 1);
4647
4648 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4649 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4650}
4651
4652/****************************************************************************/
4653/* */
4654/* Routine Name: ips_enable_int_copperhead_memio */
4655/* */
4656/* Routine Description: */
4657/* Turn on interrupts */
4658/* */
4659/****************************************************************************/
4660static void
4661ips_enable_int_copperhead_memio(ips_ha_t * ha)
4662{
4663 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4664
4665 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4666 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4667}
4668
4669/****************************************************************************/
4670/* */
4671/* Routine Name: ips_enable_int_morpheus */
4672/* */
4673/* Routine Description: */
4674/* Turn on interrupts */
4675/* */
4676/****************************************************************************/
4677static void
4678ips_enable_int_morpheus(ips_ha_t * ha)
4679{
4680 uint32_t Oimr;
4681
4682 METHOD_TRACE("ips_enable_int_morpheus", 1);
4683
4684 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4685 Oimr &= ~0x08;
4686 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4687 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4688}
4689
4690/****************************************************************************/
4691/* */
4692/* Routine Name: ips_init_copperhead */
4693/* */
4694/* Routine Description: */
4695/* */
4696/* Initialize a copperhead controller */
4697/* */
4698/****************************************************************************/
4699static int
4700ips_init_copperhead(ips_ha_t * ha)
4701{
4702 uint8_t Isr;
4703 uint8_t Cbsp;
4704 uint8_t PostByte[IPS_MAX_POST_BYTES];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4705 int i, j;
4706
4707 METHOD_TRACE("ips_init_copperhead", 1);
4708
4709 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4710 for (j = 0; j < 45; j++) {
4711 Isr = inb(ha->io_addr + IPS_REG_HISR);
4712 if (Isr & IPS_BIT_GHI)
4713 break;
4714
4715 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]4716 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4717 }
4718
4719 if (j >= 45)
4720 /* error occurred */
4721 return (0);
4722
4723 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4724 outb(Isr, ha->io_addr + IPS_REG_HISR);
4725 }
4726
4727 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4728 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4729 "reset controller fails (post status %x %x).\n",
4730 PostByte[0], PostByte[1]);
4731
4732 return (0);
4733 }
4734
4735 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4736 for (j = 0; j < 240; j++) {
4737 Isr = inb(ha->io_addr + IPS_REG_HISR);
4738 if (Isr & IPS_BIT_GHI)
4739 break;
4740
4741 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]4742 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4743 }
4744
4745 if (j >= 240)
4746 /* error occurred */
4747 return (0);
4748
Lee Jonesffe17572020-07-23 13:24:18 +0100[diff] [blame]4749 inb(ha->io_addr + IPS_REG_ISPR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4750 outb(Isr, ha->io_addr + IPS_REG_HISR);
4751 }
4752
4753 for (i = 0; i < 240; i++) {
4754 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4755
4756 if ((Cbsp & IPS_BIT_OP) == 0)
4757 break;
4758
4759 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]4760 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4761 }
4762
4763 if (i >= 240)
4764 /* reset failed */
4765 return (0);
4766
4767 /* setup CCCR */
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]4768 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4769
4770 /* Enable busmastering */
4771 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4772
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]4773 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4774 /* fix for anaconda64 */
4775 outl(0, ha->io_addr + IPS_REG_NDAE);
4776
4777 /* Enable interrupts */
4778 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4779
4780 return (1);
4781}
4782
4783/****************************************************************************/
4784/* */
4785/* Routine Name: ips_init_copperhead_memio */
4786/* */
4787/* Routine Description: */
4788/* */
4789/* Initialize a copperhead controller with memory mapped I/O */
4790/* */
4791/****************************************************************************/
4792static int
4793ips_init_copperhead_memio(ips_ha_t * ha)
4794{
4795 uint8_t Isr = 0;
4796 uint8_t Cbsp;
4797 uint8_t PostByte[IPS_MAX_POST_BYTES];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4798 int i, j;
4799
4800 METHOD_TRACE("ips_init_copperhead_memio", 1);
4801
4802 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4803 for (j = 0; j < 45; j++) {
4804 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4805 if (Isr & IPS_BIT_GHI)
4806 break;
4807
4808 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]4809 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4810 }
4811
4812 if (j >= 45)
4813 /* error occurred */
4814 return (0);
4815
4816 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4817 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4818 }
4819
4820 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4821 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4822 "reset controller fails (post status %x %x).\n",
4823 PostByte[0], PostByte[1]);
4824
4825 return (0);
4826 }
4827
4828 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4829 for (j = 0; j < 240; j++) {
4830 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4831 if (Isr & IPS_BIT_GHI)
4832 break;
4833
4834 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]4835 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4836 }
4837
4838 if (j >= 240)
4839 /* error occurred */
4840 return (0);
4841
Lee Jonesffe17572020-07-23 13:24:18 +0100[diff] [blame]4842 readb(ha->mem_ptr + IPS_REG_ISPR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4843 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4844 }
4845
4846 for (i = 0; i < 240; i++) {
4847 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4848
4849 if ((Cbsp & IPS_BIT_OP) == 0)
4850 break;
4851
4852 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]4853 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4854 }
4855
4856 if (i >= 240)
4857 /* error occurred */
4858 return (0);
4859
4860 /* setup CCCR */
4861 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4862
4863 /* Enable busmastering */
4864 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4865
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]4866 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4867 /* fix for anaconda64 */
4868 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4869
4870 /* Enable interrupts */
4871 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4872
4873 /* if we get here then everything went OK */
4874 return (1);
4875}
4876
4877/****************************************************************************/
4878/* */
4879/* Routine Name: ips_init_morpheus */
4880/* */
4881/* Routine Description: */
4882/* */
4883/* Initialize a morpheus controller */
4884/* */
4885/****************************************************************************/
4886static int
4887ips_init_morpheus(ips_ha_t * ha)
4888{
4889 uint32_t Post;
4890 uint32_t Config;
4891 uint32_t Isr;
4892 uint32_t Oimr;
4893 int i;
4894
4895 METHOD_TRACE("ips_init_morpheus", 1);
4896
4897 /* Wait up to 45 secs for Post */
4898 for (i = 0; i < 45; i++) {
4899 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4900
4901 if (Isr & IPS_BIT_I960_MSG0I)
4902 break;
4903
4904 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]4905 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4906 }
4907
4908 if (i >= 45) {
4909 /* error occurred */
4910 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4911 "timeout waiting for post.\n");
4912
4913 return (0);
4914 }
4915
4916 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4917
4918 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
4919 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4920 "Flashing Battery PIC, Please wait ...\n");
4921
4922 /* Clear the interrupt bit */
4923 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4924 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4925
4926 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
4927 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4928 if (Post != 0x4F00)
4929 break;
4930 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]4931 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4932 }
4933
4934 if (i >= 120) {
4935 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4936 "timeout waiting for Battery PIC Flash\n");
4937 return (0);
4938 }
4939
4940 }
4941
4942 /* Clear the interrupt bit */
4943 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4944 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4945
4946 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
4947 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4948 "reset controller fails (post status %x).\n", Post);
4949
4950 return (0);
4951 }
4952
4953 /* Wait up to 240 secs for config bytes */
4954 for (i = 0; i < 240; i++) {
4955 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4956
4957 if (Isr & IPS_BIT_I960_MSG1I)
4958 break;
4959
4960 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]4961 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]4962 }
4963
4964 if (i >= 240) {
4965 /* error occurred */
4966 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4967 "timeout waiting for config.\n");
4968
4969 return (0);
4970 }
4971
4972 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4973
4974 /* Clear interrupt bit */
4975 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
4976 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4977
4978 /* Turn on the interrupts */
4979 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4980 Oimr &= ~0x8;
4981 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4982
4983 /* if we get here then everything went OK */
4984
4985 /* Since we did a RESET, an EraseStripeLock may be needed */
4986 if (Post == 0xEF10) {
4987 if ((Config == 0x000F) || (Config == 0x0009))
4988 ha->requires_esl = 1;
4989 }
4990
4991 return (1);
4992}
4993
4994/****************************************************************************/
4995/* */
4996/* Routine Name: ips_reset_copperhead */
4997/* */
4998/* Routine Description: */
4999/* */
5000/* Reset the controller */
5001/* */
5002/****************************************************************************/
5003static int
5004ips_reset_copperhead(ips_ha_t * ha)
5005{
5006 int reset_counter;
5007
5008 METHOD_TRACE("ips_reset_copperhead", 1);
5009
5010 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]5011 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5012
5013 reset_counter = 0;
5014
5015 while (reset_counter < 2) {
5016 reset_counter++;
5017
5018 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5019
5020 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]5021 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5022
5023 outb(0, ha->io_addr + IPS_REG_SCPR);
5024
5025 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]5026 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5027
5028 if ((*ha->func.init) (ha))
5029 break;
5030 else if (reset_counter >= 2) {
5031
5032 return (0);
5033 }
5034 }
5035
5036 return (1);
5037}
5038
5039/****************************************************************************/
5040/* */
5041/* Routine Name: ips_reset_copperhead_memio */
5042/* */
5043/* Routine Description: */
5044/* */
5045/* Reset the controller */
5046/* */
5047/****************************************************************************/
5048static int
5049ips_reset_copperhead_memio(ips_ha_t * ha)
5050{
5051 int reset_counter;
5052
5053 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5054
5055 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]5056 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5057
5058 reset_counter = 0;
5059
5060 while (reset_counter < 2) {
5061 reset_counter++;
5062
5063 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5064
5065 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]5066 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5067
5068 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5069
5070 /* Delay for 1 Second */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]5071 MDELAY(IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5072
5073 if ((*ha->func.init) (ha))
5074 break;
5075 else if (reset_counter >= 2) {
5076
5077 return (0);
5078 }
5079 }
5080
5081 return (1);
5082}
5083
5084/****************************************************************************/
5085/* */
5086/* Routine Name: ips_reset_morpheus */
5087/* */
5088/* Routine Description: */
5089/* */
5090/* Reset the controller */
5091/* */
5092/****************************************************************************/
5093static int
5094ips_reset_morpheus(ips_ha_t * ha)
5095{
5096 int reset_counter;
5097 uint8_t junk;
5098
5099 METHOD_TRACE("ips_reset_morpheus", 1);
5100
5101 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]5102 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5103
5104 reset_counter = 0;
5105
5106 while (reset_counter < 2) {
5107 reset_counter++;
5108
5109 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5110
5111 /* Delay for 5 Seconds */
Andrew Mortonbf471342006-11-08 19:56:24 -0800[diff] [blame]5112 MDELAY(5 * IPS_ONE_SEC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5113
5114 /* Do a PCI config read to wait for adapter */
5115 pci_read_config_byte(ha->pcidev, 4, &junk);
5116
5117 if ((*ha->func.init) (ha))
5118 break;
5119 else if (reset_counter >= 2) {
5120
5121 return (0);
5122 }
5123 }
5124
5125 return (1);
5126}
5127
5128/****************************************************************************/
5129/* */
5130/* Routine Name: ips_statinit */
5131/* */
5132/* Routine Description: */
5133/* */
5134/* Initialize the status queues on the controller */
5135/* */
5136/****************************************************************************/
5137static void
5138ips_statinit(ips_ha_t * ha)
5139{
5140 uint32_t phys_status_start;
5141
5142 METHOD_TRACE("ips_statinit", 1);
5143
5144 ha->adapt->p_status_start = ha->adapt->status;
5145 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5146 ha->adapt->p_status_tail = ha->adapt->status;
5147
5148 phys_status_start = ha->adapt->hw_status_start;
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]5149 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5150 outl(phys_status_start + IPS_STATUS_Q_SIZE,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5151 ha->io_addr + IPS_REG_SQER);
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]5152 outl(phys_status_start + IPS_STATUS_SIZE,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5153 ha->io_addr + IPS_REG_SQHR);
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]5154 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5155
5156 ha->adapt->hw_status_tail = phys_status_start;
5157}
5158
5159/****************************************************************************/
5160/* */
5161/* Routine Name: ips_statinit_memio */
5162/* */
5163/* Routine Description: */
5164/* */
5165/* Initialize the status queues on the controller */
5166/* */
5167/****************************************************************************/
5168static void
5169ips_statinit_memio(ips_ha_t * ha)
5170{
5171 uint32_t phys_status_start;
5172
5173 METHOD_TRACE("ips_statinit_memio", 1);
5174
5175 ha->adapt->p_status_start = ha->adapt->status;
5176 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5177 ha->adapt->p_status_tail = ha->adapt->status;
5178
5179 phys_status_start = ha->adapt->hw_status_start;
5180 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5181 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5182 ha->mem_ptr + IPS_REG_SQER);
5183 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5184 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5185
5186 ha->adapt->hw_status_tail = phys_status_start;
5187}
5188
5189/****************************************************************************/
5190/* */
5191/* Routine Name: ips_statupd_copperhead */
5192/* */
5193/* Routine Description: */
5194/* */
5195/* Remove an element from the status queue */
5196/* */
5197/****************************************************************************/
5198static uint32_t
5199ips_statupd_copperhead(ips_ha_t * ha)
5200{
5201 METHOD_TRACE("ips_statupd_copperhead", 1);
5202
5203 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5204 ha->adapt->p_status_tail++;
5205 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5206 } else {
5207 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5208 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5209 }
5210
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]5211 outl(ha->adapt->hw_status_tail,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5212 ha->io_addr + IPS_REG_SQTR);
5213
5214 return (ha->adapt->p_status_tail->value);
5215}
5216
5217/****************************************************************************/
5218/* */
5219/* Routine Name: ips_statupd_copperhead_memio */
5220/* */
5221/* Routine Description: */
5222/* */
5223/* Remove an element from the status queue */
5224/* */
5225/****************************************************************************/
5226static uint32_t
5227ips_statupd_copperhead_memio(ips_ha_t * ha)
5228{
5229 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5230
5231 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5232 ha->adapt->p_status_tail++;
5233 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5234 } else {
5235 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5236 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5237 }
5238
5239 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5240
5241 return (ha->adapt->p_status_tail->value);
5242}
5243
5244/****************************************************************************/
5245/* */
5246/* Routine Name: ips_statupd_morpheus */
5247/* */
5248/* Routine Description: */
5249/* */
5250/* Remove an element from the status queue */
5251/* */
5252/****************************************************************************/
5253static uint32_t
5254ips_statupd_morpheus(ips_ha_t * ha)
5255{
5256 uint32_t val;
5257
5258 METHOD_TRACE("ips_statupd_morpheus", 1);
5259
5260 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5261
5262 return (val);
5263}
5264
5265/****************************************************************************/
5266/* */
5267/* Routine Name: ips_issue_copperhead */
5268/* */
5269/* Routine Description: */
5270/* */
5271/* Send a command down to the controller */
5272/* */
5273/****************************************************************************/
5274static int
5275ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5276{
5277 uint32_t TimeOut;
5278 uint32_t val;
5279
5280 METHOD_TRACE("ips_issue_copperhead", 1);
5281
5282 if (scb->scsi_cmd) {
5283 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5284 ips_name,
5285 ha->host_num,
5286 scb->cdb[0],
5287 scb->cmd.basic_io.command_id,
5288 scb->bus, scb->target_id, scb->lun);
5289 } else {
5290 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5291 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5292 }
5293
5294 TimeOut = 0;
5295
5296 while ((val =
5297 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5298 udelay(1000);
5299
5300 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5301 if (!(val & IPS_BIT_START_STOP))
5302 break;
5303
5304 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5305 "ips_issue val [0x%x].\n", val);
5306 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5307 "ips_issue semaphore chk timeout.\n");
5308
5309 return (IPS_FAILURE);
5310 } /* end if */
5311 } /* end while */
5312
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]5313 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5314 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5315
5316 return (IPS_SUCCESS);
5317}
5318
5319/****************************************************************************/
5320/* */
5321/* Routine Name: ips_issue_copperhead_memio */
5322/* */
5323/* Routine Description: */
5324/* */
5325/* Send a command down to the controller */
5326/* */
5327/****************************************************************************/
5328static int
5329ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5330{
5331 uint32_t TimeOut;
5332 uint32_t val;
5333
5334 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5335
5336 if (scb->scsi_cmd) {
5337 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5338 ips_name,
5339 ha->host_num,
5340 scb->cdb[0],
5341 scb->cmd.basic_io.command_id,
5342 scb->bus, scb->target_id, scb->lun);
5343 } else {
5344 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5345 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5346 }
5347
5348 TimeOut = 0;
5349
5350 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5351 udelay(1000);
5352
5353 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5354 if (!(val & IPS_BIT_START_STOP))
5355 break;
5356
5357 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5358 "ips_issue val [0x%x].\n", val);
5359 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5360 "ips_issue semaphore chk timeout.\n");
5361
5362 return (IPS_FAILURE);
5363 } /* end if */
5364 } /* end while */
5365
5366 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5367 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5368
5369 return (IPS_SUCCESS);
5370}
5371
5372/****************************************************************************/
5373/* */
5374/* Routine Name: ips_issue_i2o */
5375/* */
5376/* Routine Description: */
5377/* */
5378/* Send a command down to the controller */
5379/* */
5380/****************************************************************************/
5381static int
5382ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5383{
5384
5385 METHOD_TRACE("ips_issue_i2o", 1);
5386
5387 if (scb->scsi_cmd) {
5388 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5389 ips_name,
5390 ha->host_num,
5391 scb->cdb[0],
5392 scb->cmd.basic_io.command_id,
5393 scb->bus, scb->target_id, scb->lun);
5394 } else {
5395 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5396 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5397 }
5398
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]5399 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5400
5401 return (IPS_SUCCESS);
5402}
5403
5404/****************************************************************************/
5405/* */
5406/* Routine Name: ips_issue_i2o_memio */
5407/* */
5408/* Routine Description: */
5409/* */
5410/* Send a command down to the controller */
5411/* */
5412/****************************************************************************/
5413static int
5414ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5415{
5416
5417 METHOD_TRACE("ips_issue_i2o_memio", 1);
5418
5419 if (scb->scsi_cmd) {
5420 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5421 ips_name,
5422 ha->host_num,
5423 scb->cdb[0],
5424 scb->cmd.basic_io.command_id,
5425 scb->bus, scb->target_id, scb->lun);
5426 } else {
5427 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5428 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5429 }
5430
5431 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5432
5433 return (IPS_SUCCESS);
5434}
5435
5436/****************************************************************************/
5437/* */
5438/* Routine Name: ips_isintr_copperhead */
5439/* */
5440/* Routine Description: */
5441/* */
5442/* Test to see if an interrupt is for us */
5443/* */
5444/****************************************************************************/
5445static int
5446ips_isintr_copperhead(ips_ha_t * ha)
5447{
5448 uint8_t Isr;
5449
5450 METHOD_TRACE("ips_isintr_copperhead", 2);
5451
5452 Isr = inb(ha->io_addr + IPS_REG_HISR);
5453
5454 if (Isr == 0xFF)
5455 /* ?!?! Nothing really there */
5456 return (0);
5457
5458 if (Isr & IPS_BIT_SCE)
5459 return (1);
5460 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5461 /* status queue overflow or GHI */
5462 /* just clear the interrupt */
5463 outb(Isr, ha->io_addr + IPS_REG_HISR);
5464 }
5465
5466 return (0);
5467}
5468
5469/****************************************************************************/
5470/* */
5471/* Routine Name: ips_isintr_copperhead_memio */
5472/* */
5473/* Routine Description: */
5474/* */
5475/* Test to see if an interrupt is for us */
5476/* */
5477/****************************************************************************/
5478static int
5479ips_isintr_copperhead_memio(ips_ha_t * ha)
5480{
5481 uint8_t Isr;
5482
5483 METHOD_TRACE("ips_isintr_memio", 2);
5484
5485 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5486
5487 if (Isr == 0xFF)
5488 /* ?!?! Nothing really there */
5489 return (0);
5490
5491 if (Isr & IPS_BIT_SCE)
5492 return (1);
5493 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5494 /* status queue overflow or GHI */
5495 /* just clear the interrupt */
5496 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5497 }
5498
5499 return (0);
5500}
5501
5502/****************************************************************************/
5503/* */
5504/* Routine Name: ips_isintr_morpheus */
5505/* */
5506/* Routine Description: */
5507/* */
5508/* Test to see if an interrupt is for us */
5509/* */
5510/****************************************************************************/
5511static int
5512ips_isintr_morpheus(ips_ha_t * ha)
5513{
5514 uint32_t Isr;
5515
5516 METHOD_TRACE("ips_isintr_morpheus", 2);
5517
5518 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5519
5520 if (Isr & IPS_BIT_I2O_OPQI)
5521 return (1);
5522 else
5523 return (0);
5524}
5525
5526/****************************************************************************/
5527/* */
5528/* Routine Name: ips_wait */
5529/* */
5530/* Routine Description: */
5531/* */
5532/* Wait for a command to complete */
5533/* */
5534/****************************************************************************/
5535static int
5536ips_wait(ips_ha_t * ha, int time, int intr)
5537{
5538 int ret;
5539 int done;
5540
5541 METHOD_TRACE("ips_wait", 1);
5542
5543 ret = IPS_FAILURE;
5544 done = FALSE;
5545
5546 time *= IPS_ONE_SEC; /* convert seconds */
5547
5548 while ((time > 0) && (!done)) {
5549 if (intr == IPS_INTR_ON) {
5550 if (ha->waitflag == FALSE) {
5551 ret = IPS_SUCCESS;
5552 done = TRUE;
5553 break;
5554 }
5555 } else if (intr == IPS_INTR_IORL) {
5556 if (ha->waitflag == FALSE) {
5557 /*
5558 * controller generated an interrupt to
5559 * acknowledge completion of the command
5560 * and ips_intr() has serviced the interrupt.
5561 */
5562 ret = IPS_SUCCESS;
5563 done = TRUE;
5564 break;
5565 }
5566
5567 /*
5568 * NOTE: we already have the io_request_lock so
5569 * even if we get an interrupt it won't get serviced
5570 * until after we finish.
5571 */
5572
5573 (*ha->func.intr) (ha);
5574 }
5575
5576 /* This looks like a very evil loop, but it only does this during start-up */
5577 udelay(1000);
5578 time--;
5579 }
5580
5581 return (ret);
5582}
5583
5584/****************************************************************************/
5585/* */
5586/* Routine Name: ips_write_driver_status */
5587/* */
5588/* Routine Description: */
5589/* */
5590/* Write OS/Driver version to Page 5 of the nvram on the controller */
5591/* */
5592/****************************************************************************/
5593static int
5594ips_write_driver_status(ips_ha_t * ha, int intr)
5595{
5596 METHOD_TRACE("ips_write_driver_status", 1);
5597
5598 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5599 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5600 "unable to read NVRAM page 5.\n");
5601
5602 return (0);
5603 }
5604
5605 /* check to make sure the page has a valid */
5606 /* signature */
5607 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5608 DEBUG_VAR(1,
5609 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5610 ips_name, ha->host_num, ha->nvram->signature);
5611 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5612 }
5613
5614 DEBUG_VAR(2,
5615 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5616 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5617 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5618 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5619 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5620 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5621 ha->nvram->bios_low[3]);
5622
5623 ips_get_bios_version(ha, intr);
5624
5625 /* change values (as needed) */
5626 ha->nvram->operating_system = IPS_OS_LINUX;
5627 ha->nvram->adapter_type = ha->ad_type;
Lee Jones00e24562020-07-23 13:24:19 +0100[diff] [blame]5628 memcpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5629 memcpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5630 memcpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5631 memcpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5632
Jack Hammera60768e2005-11-03 09:46:00 -0500[diff] [blame]5633 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5634
5635 /* now update the page */
5636 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5637 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5638 "unable to write NVRAM page 5.\n");
5639
5640 return (0);
5641 }
5642
5643 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5644 ha->slot_num = ha->nvram->adapter_slot;
5645
5646 return (1);
5647}
5648
5649/****************************************************************************/
5650/* */
5651/* Routine Name: ips_read_adapter_status */
5652/* */
5653/* Routine Description: */
5654/* */
5655/* Do an Inquiry command to the adapter */
5656/* */
5657/****************************************************************************/
5658static int
5659ips_read_adapter_status(ips_ha_t * ha, int intr)
5660{
5661 ips_scb_t *scb;
5662 int ret;
5663
5664 METHOD_TRACE("ips_read_adapter_status", 1);
5665
5666 scb = &ha->scbs[ha->max_cmds - 1];
5667
5668 ips_init_scb(ha, scb);
5669
5670 scb->timeout = ips_cmd_timeout;
5671 scb->cdb[0] = IPS_CMD_ENQUIRY;
5672
5673 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5674 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5675 scb->cmd.basic_io.sg_count = 0;
5676 scb->cmd.basic_io.lba = 0;
5677 scb->cmd.basic_io.sector_count = 0;
5678 scb->cmd.basic_io.log_drv = 0;
5679 scb->data_len = sizeof (*ha->enq);
5680 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5681
5682 /* send command */
5683 if (((ret =
5684 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5685 || (ret == IPS_SUCCESS_IMM)
5686 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5687 return (0);
5688
5689 return (1);
5690}
5691
5692/****************************************************************************/
5693/* */
5694/* Routine Name: ips_read_subsystem_parameters */
5695/* */
5696/* Routine Description: */
5697/* */
5698/* Read subsystem parameters from the adapter */
5699/* */
5700/****************************************************************************/
5701static int
5702ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5703{
5704 ips_scb_t *scb;
5705 int ret;
5706
5707 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5708
5709 scb = &ha->scbs[ha->max_cmds - 1];
5710
5711 ips_init_scb(ha, scb);
5712
5713 scb->timeout = ips_cmd_timeout;
5714 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5715
5716 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5717 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5718 scb->cmd.basic_io.sg_count = 0;
5719 scb->cmd.basic_io.lba = 0;
5720 scb->cmd.basic_io.sector_count = 0;
5721 scb->cmd.basic_io.log_drv = 0;
5722 scb->data_len = sizeof (*ha->subsys);
5723 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5724
5725 /* send command */
5726 if (((ret =
5727 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5728 || (ret == IPS_SUCCESS_IMM)
5729 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5730 return (0);
5731
5732 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5733 return (1);
5734}
5735
5736/****************************************************************************/
5737/* */
5738/* Routine Name: ips_read_config */
5739/* */
5740/* Routine Description: */
5741/* */
5742/* Read the configuration on the adapter */
5743/* */
5744/****************************************************************************/
5745static int
5746ips_read_config(ips_ha_t * ha, int intr)
5747{
5748 ips_scb_t *scb;
5749 int i;
5750 int ret;
5751
5752 METHOD_TRACE("ips_read_config", 1);
5753
5754 /* set defaults for initiator IDs */
5755 for (i = 0; i < 4; i++)
5756 ha->conf->init_id[i] = 7;
5757
5758 scb = &ha->scbs[ha->max_cmds - 1];
5759
5760 ips_init_scb(ha, scb);
5761
5762 scb->timeout = ips_cmd_timeout;
5763 scb->cdb[0] = IPS_CMD_READ_CONF;
5764
5765 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5766 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5767 scb->data_len = sizeof (*ha->conf);
5768 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5769
5770 /* send command */
5771 if (((ret =
5772 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5773 || (ret == IPS_SUCCESS_IMM)
5774 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5775
5776 memset(ha->conf, 0, sizeof (IPS_CONF));
5777
5778 /* reset initiator IDs */
5779 for (i = 0; i < 4; i++)
5780 ha->conf->init_id[i] = 7;
5781
5782 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5783 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5784 IPS_CMD_CMPLT_WERROR)
5785 return (1);
5786
5787 return (0);
5788 }
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]5789
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5790 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5791 return (1);
5792}
5793
5794/****************************************************************************/
5795/* */
5796/* Routine Name: ips_readwrite_page5 */
5797/* */
5798/* Routine Description: */
5799/* */
5800/* Read nvram page 5 from the adapter */
5801/* */
5802/****************************************************************************/
5803static int
5804ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5805{
5806 ips_scb_t *scb;
5807 int ret;
5808
5809 METHOD_TRACE("ips_readwrite_page5", 1);
5810
5811 scb = &ha->scbs[ha->max_cmds - 1];
5812
5813 ips_init_scb(ha, scb);
5814
5815 scb->timeout = ips_cmd_timeout;
5816 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5817
5818 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5819 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5820 scb->cmd.nvram.page = 5;
5821 scb->cmd.nvram.write = write;
5822 scb->cmd.nvram.reserved = 0;
5823 scb->cmd.nvram.reserved2 = 0;
5824 scb->data_len = sizeof (*ha->nvram);
5825 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5826 if (write)
5827 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
Jeff Garzik2f277d62007-12-13 16:14:08 -0800[diff] [blame]5828
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5829 /* issue the command */
5830 if (((ret =
5831 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5832 || (ret == IPS_SUCCESS_IMM)
5833 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5834
5835 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5836
5837 return (0);
5838 }
5839 if (!write)
5840 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5841 return (1);
5842}
5843
5844/****************************************************************************/
5845/* */
5846/* Routine Name: ips_clear_adapter */
5847/* */
5848/* Routine Description: */
5849/* */
5850/* Clear the stripe lock tables */
5851/* */
5852/****************************************************************************/
5853static int
5854ips_clear_adapter(ips_ha_t * ha, int intr)
5855{
5856 ips_scb_t *scb;
5857 int ret;
5858
5859 METHOD_TRACE("ips_clear_adapter", 1);
5860
5861 scb = &ha->scbs[ha->max_cmds - 1];
5862
5863 ips_init_scb(ha, scb);
5864
5865 scb->timeout = ips_reset_timeout;
5866 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5867
5868 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5869 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5870 scb->cmd.config_sync.channel = 0;
5871 scb->cmd.config_sync.source_target = IPS_POCL;
5872 scb->cmd.config_sync.reserved = 0;
5873 scb->cmd.config_sync.reserved2 = 0;
5874 scb->cmd.config_sync.reserved3 = 0;
5875
5876 /* issue command */
5877 if (((ret =
5878 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5879 || (ret == IPS_SUCCESS_IMM)
5880 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5881 return (0);
5882
5883 /* send unlock stripe command */
5884 ips_init_scb(ha, scb);
5885
5886 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5887 scb->timeout = ips_reset_timeout;
5888
5889 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5890 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5891 scb->cmd.unlock_stripe.log_drv = 0;
5892 scb->cmd.unlock_stripe.control = IPS_CSL;
5893 scb->cmd.unlock_stripe.reserved = 0;
5894 scb->cmd.unlock_stripe.reserved2 = 0;
5895 scb->cmd.unlock_stripe.reserved3 = 0;
5896
5897 /* issue command */
5898 if (((ret =
5899 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5900 || (ret == IPS_SUCCESS_IMM)
5901 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5902 return (0);
5903
5904 return (1);
5905}
5906
5907/****************************************************************************/
5908/* */
5909/* Routine Name: ips_ffdc_reset */
5910/* */
5911/* Routine Description: */
5912/* */
5913/* FFDC: write reset info */
5914/* */
5915/****************************************************************************/
5916static void
5917ips_ffdc_reset(ips_ha_t * ha, int intr)
5918{
5919 ips_scb_t *scb;
5920
5921 METHOD_TRACE("ips_ffdc_reset", 1);
5922
5923 scb = &ha->scbs[ha->max_cmds - 1];
5924
5925 ips_init_scb(ha, scb);
5926
5927 scb->timeout = ips_cmd_timeout;
5928 scb->cdb[0] = IPS_CMD_FFDC;
5929 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5930 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5931 scb->cmd.ffdc.reset_count = ha->reset_count;
5932 scb->cmd.ffdc.reset_type = 0x80;
5933
5934 /* convert time to what the card wants */
5935 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5936
5937 /* issue command */
5938 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
5939}
5940
5941/****************************************************************************/
5942/* */
5943/* Routine Name: ips_ffdc_time */
5944/* */
5945/* Routine Description: */
5946/* */
5947/* FFDC: write time info */
5948/* */
5949/****************************************************************************/
5950static void
5951ips_ffdc_time(ips_ha_t * ha)
5952{
5953 ips_scb_t *scb;
5954
5955 METHOD_TRACE("ips_ffdc_time", 1);
5956
5957 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
5958
5959 scb = &ha->scbs[ha->max_cmds - 1];
5960
5961 ips_init_scb(ha, scb);
5962
5963 scb->timeout = ips_cmd_timeout;
5964 scb->cdb[0] = IPS_CMD_FFDC;
5965 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5966 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5967 scb->cmd.ffdc.reset_count = 0;
5968 scb->cmd.ffdc.reset_type = 0;
5969
5970 /* convert time to what the card wants */
5971 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5972
5973 /* issue command */
5974 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
5975}
5976
5977/****************************************************************************/
5978/* */
5979/* Routine Name: ips_fix_ffdc_time */
5980/* */
5981/* Routine Description: */
5982/* Adjust time_t to what the card wants */
5983/* */
5984/****************************************************************************/
5985static void
Arnd Bergmannf990bee2018-04-20 18:04:40 +0200[diff] [blame]5986ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time64_t current_time)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5987{
Arnd Bergmannf990bee2018-04-20 18:04:40 +0200[diff] [blame]5988 struct tm tm;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5989
5990 METHOD_TRACE("ips_fix_ffdc_time", 1);
5991
Arnd Bergmannf990bee2018-04-20 18:04:40 +0200[diff] [blame]5992 time64_to_tm(current_time, 0, &tm);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5993
Arnd Bergmannf990bee2018-04-20 18:04:40 +0200[diff] [blame]5994 scb->cmd.ffdc.hour = tm.tm_hour;
5995 scb->cmd.ffdc.minute = tm.tm_min;
5996 scb->cmd.ffdc.second = tm.tm_sec;
5997 scb->cmd.ffdc.yearH = (tm.tm_year + 1900) / 100;
5998 scb->cmd.ffdc.yearL = tm.tm_year % 100;
5999 scb->cmd.ffdc.month = tm.tm_mon + 1;
6000 scb->cmd.ffdc.day = tm.tm_mday;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6001}
6002
6003/****************************************************************************
6004 * BIOS Flash Routines *
6005 ****************************************************************************/
6006
6007/****************************************************************************/
6008/* */
6009/* Routine Name: ips_erase_bios */
6010/* */
6011/* Routine Description: */
6012/* Erase the BIOS on the adapter */
6013/* */
6014/****************************************************************************/
6015static int
6016ips_erase_bios(ips_ha_t * ha)
6017{
6018 int timeout;
6019 uint8_t status = 0;
6020
6021 METHOD_TRACE("ips_erase_bios", 1);
6022
6023 status = 0;
6024
6025 /* Clear the status register */
6026 outl(0, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6027 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6028 udelay(25); /* 25 us */
6029
6030 outb(0x50, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6031 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6032 udelay(25); /* 25 us */
6033
6034 /* Erase Setup */
6035 outb(0x20, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6036 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6037 udelay(25); /* 25 us */
6038
6039 /* Erase Confirm */
6040 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6041 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6042 udelay(25); /* 25 us */
6043
6044 /* Erase Status */
6045 outb(0x70, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6046 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6047 udelay(25); /* 25 us */
6048
6049 timeout = 80000; /* 80 seconds */
6050
6051 while (timeout > 0) {
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6052 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6053 outl(0, ha->io_addr + IPS_REG_FLAP);
6054 udelay(25); /* 25 us */
6055 }
6056
6057 status = inb(ha->io_addr + IPS_REG_FLDP);
6058
6059 if (status & 0x80)
6060 break;
6061
6062 MDELAY(1);
6063 timeout--;
6064 }
6065
6066 /* check for timeout */
6067 if (timeout <= 0) {
6068 /* timeout */
6069
6070 /* try to suspend the erase */
6071 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6072 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6073 udelay(25); /* 25 us */
6074
6075 /* wait for 10 seconds */
6076 timeout = 10000;
6077 while (timeout > 0) {
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6078 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6079 outl(0, ha->io_addr + IPS_REG_FLAP);
6080 udelay(25); /* 25 us */
6081 }
6082
6083 status = inb(ha->io_addr + IPS_REG_FLDP);
6084
6085 if (status & 0xC0)
6086 break;
6087
6088 MDELAY(1);
6089 timeout--;
6090 }
6091
6092 return (1);
6093 }
6094
6095 /* check for valid VPP */
6096 if (status & 0x08)
6097 /* VPP failure */
6098 return (1);
6099
Andreas Mohrd6e05ed2006-06-26 18:35:02 +0200[diff] [blame]6100 /* check for successful flash */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6101 if (status & 0x30)
6102 /* sequence error */
6103 return (1);
6104
6105 /* Otherwise, we were successful */
6106 /* clear status */
6107 outb(0x50, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6108 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6109 udelay(25); /* 25 us */
6110
6111 /* enable reads */
6112 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6113 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6114 udelay(25); /* 25 us */
6115
6116 return (0);
6117}
6118
6119/****************************************************************************/
6120/* */
6121/* Routine Name: ips_erase_bios_memio */
6122/* */
6123/* Routine Description: */
6124/* Erase the BIOS on the adapter */
6125/* */
6126/****************************************************************************/
6127static int
6128ips_erase_bios_memio(ips_ha_t * ha)
6129{
6130 int timeout;
6131 uint8_t status;
6132
6133 METHOD_TRACE("ips_erase_bios_memio", 1);
6134
6135 status = 0;
6136
6137 /* Clear the status register */
6138 writel(0, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6139 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6140 udelay(25); /* 25 us */
6141
6142 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6143 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6144 udelay(25); /* 25 us */
6145
6146 /* Erase Setup */
6147 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6148 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6149 udelay(25); /* 25 us */
6150
6151 /* Erase Confirm */
6152 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6153 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6154 udelay(25); /* 25 us */
6155
6156 /* Erase Status */
6157 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6158 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6159 udelay(25); /* 25 us */
6160
6161 timeout = 80000; /* 80 seconds */
6162
6163 while (timeout > 0) {
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6164 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6165 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6166 udelay(25); /* 25 us */
6167 }
6168
6169 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6170
6171 if (status & 0x80)
6172 break;
6173
6174 MDELAY(1);
6175 timeout--;
6176 }
6177
6178 /* check for timeout */
6179 if (timeout <= 0) {
6180 /* timeout */
6181
6182 /* try to suspend the erase */
6183 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6184 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6185 udelay(25); /* 25 us */
6186
6187 /* wait for 10 seconds */
6188 timeout = 10000;
6189 while (timeout > 0) {
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6190 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6191 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6192 udelay(25); /* 25 us */
6193 }
6194
6195 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6196
6197 if (status & 0xC0)
6198 break;
6199
6200 MDELAY(1);
6201 timeout--;
6202 }
6203
6204 return (1);
6205 }
6206
6207 /* check for valid VPP */
6208 if (status & 0x08)
6209 /* VPP failure */
6210 return (1);
6211
Andreas Mohrd6e05ed2006-06-26 18:35:02 +0200[diff] [blame]6212 /* check for successful flash */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6213 if (status & 0x30)
6214 /* sequence error */
6215 return (1);
6216
6217 /* Otherwise, we were successful */
6218 /* clear status */
6219 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6220 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6221 udelay(25); /* 25 us */
6222
6223 /* enable reads */
6224 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6225 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6226 udelay(25); /* 25 us */
6227
6228 return (0);
6229}
6230
6231/****************************************************************************/
6232/* */
6233/* Routine Name: ips_program_bios */
6234/* */
6235/* Routine Description: */
6236/* Program the BIOS on the adapter */
6237/* */
6238/****************************************************************************/
6239static int
6240ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6241 uint32_t offset)
6242{
6243 int i;
6244 int timeout;
6245 uint8_t status = 0;
6246
6247 METHOD_TRACE("ips_program_bios", 1);
6248
6249 status = 0;
6250
6251 for (i = 0; i < buffersize; i++) {
6252 /* write a byte */
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]6253 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6254 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6255 udelay(25); /* 25 us */
6256
6257 outb(0x40, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6258 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6259 udelay(25); /* 25 us */
6260
6261 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6262 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6263 udelay(25); /* 25 us */
6264
6265 /* wait up to one second */
6266 timeout = 1000;
6267 while (timeout > 0) {
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6268 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6269 outl(0, ha->io_addr + IPS_REG_FLAP);
6270 udelay(25); /* 25 us */
6271 }
6272
6273 status = inb(ha->io_addr + IPS_REG_FLDP);
6274
6275 if (status & 0x80)
6276 break;
6277
6278 MDELAY(1);
6279 timeout--;
6280 }
6281
6282 if (timeout == 0) {
6283 /* timeout error */
6284 outl(0, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6285 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6286 udelay(25); /* 25 us */
6287
6288 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6289 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6290 udelay(25); /* 25 us */
6291
6292 return (1);
6293 }
6294
6295 /* check the status */
6296 if (status & 0x18) {
6297 /* programming error */
6298 outl(0, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6299 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6300 udelay(25); /* 25 us */
6301
6302 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6303 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6304 udelay(25); /* 25 us */
6305
6306 return (1);
6307 }
6308 } /* end for */
6309
6310 /* Enable reading */
6311 outl(0, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6312 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6313 udelay(25); /* 25 us */
6314
6315 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6316 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6317 udelay(25); /* 25 us */
6318
6319 return (0);
6320}
6321
6322/****************************************************************************/
6323/* */
6324/* Routine Name: ips_program_bios_memio */
6325/* */
6326/* Routine Description: */
6327/* Program the BIOS on the adapter */
6328/* */
6329/****************************************************************************/
6330static int
6331ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6332 uint32_t offset)
6333{
6334 int i;
6335 int timeout;
6336 uint8_t status = 0;
6337
6338 METHOD_TRACE("ips_program_bios_memio", 1);
6339
6340 status = 0;
6341
6342 for (i = 0; i < buffersize; i++) {
6343 /* write a byte */
6344 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6345 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6346 udelay(25); /* 25 us */
6347
6348 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6349 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6350 udelay(25); /* 25 us */
6351
6352 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6353 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6354 udelay(25); /* 25 us */
6355
6356 /* wait up to one second */
6357 timeout = 1000;
6358 while (timeout > 0) {
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6359 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6360 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6361 udelay(25); /* 25 us */
6362 }
6363
6364 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6365
6366 if (status & 0x80)
6367 break;
6368
6369 MDELAY(1);
6370 timeout--;
6371 }
6372
6373 if (timeout == 0) {
6374 /* timeout error */
6375 writel(0, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6376 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6377 udelay(25); /* 25 us */
6378
6379 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6380 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6381 udelay(25); /* 25 us */
6382
6383 return (1);
6384 }
6385
6386 /* check the status */
6387 if (status & 0x18) {
6388 /* programming error */
6389 writel(0, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6390 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6391 udelay(25); /* 25 us */
6392
6393 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6394 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6395 udelay(25); /* 25 us */
6396
6397 return (1);
6398 }
6399 } /* end for */
6400
6401 /* Enable reading */
6402 writel(0, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6403 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6404 udelay(25); /* 25 us */
6405
6406 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6407 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6408 udelay(25); /* 25 us */
6409
6410 return (0);
6411}
6412
6413/****************************************************************************/
6414/* */
6415/* Routine Name: ips_verify_bios */
6416/* */
6417/* Routine Description: */
6418/* Verify the BIOS on the adapter */
6419/* */
6420/****************************************************************************/
6421static int
6422ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6423 uint32_t offset)
6424{
6425 uint8_t checksum;
6426 int i;
6427
6428 METHOD_TRACE("ips_verify_bios", 1);
6429
6430 /* test 1st byte */
6431 outl(0, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6432 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6433 udelay(25); /* 25 us */
6434
6435 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6436 return (1);
6437
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]6438 outl(1, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6439 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6440 udelay(25); /* 25 us */
6441 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6442 return (1);
6443
6444 checksum = 0xff;
6445 for (i = 2; i < buffersize; i++) {
6446
James Bottomleydb3cc202008-04-03 12:28:20 -0500[diff] [blame]6447 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6448 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6449 udelay(25); /* 25 us */
6450
6451 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6452 }
6453
6454 if (checksum != 0)
6455 /* failure */
6456 return (1);
6457 else
6458 /* success */
6459 return (0);
6460}
6461
6462/****************************************************************************/
6463/* */
6464/* Routine Name: ips_verify_bios_memio */
6465/* */
6466/* Routine Description: */
6467/* Verify the BIOS on the adapter */
6468/* */
6469/****************************************************************************/
6470static int
6471ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6472 uint32_t offset)
6473{
6474 uint8_t checksum;
6475 int i;
6476
6477 METHOD_TRACE("ips_verify_bios_memio", 1);
6478
6479 /* test 1st byte */
6480 writel(0, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6481 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6482 udelay(25); /* 25 us */
6483
6484 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6485 return (1);
6486
6487 writel(1, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6488 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6489 udelay(25); /* 25 us */
6490 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6491 return (1);
6492
6493 checksum = 0xff;
6494 for (i = 2; i < buffersize; i++) {
6495
6496 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6497 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6498 udelay(25); /* 25 us */
6499
6500 checksum =
6501 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6502 }
6503
6504 if (checksum != 0)
6505 /* failure */
6506 return (1);
6507 else
6508 /* success */
6509 return (0);
6510}
6511
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6512/****************************************************************************/
6513/* */
6514/* Routine Name: ips_abort_init */
6515/* */
6516/* Routine Description: */
6517/* cleanup routine for a failed adapter initialization */
6518/****************************************************************************/
6519static int
6520ips_abort_init(ips_ha_t * ha, int index)
6521{
6522 ha->active = 0;
6523 ips_free(ha);
6524 ips_ha[index] = NULL;
6525 ips_sh[index] = NULL;
6526 return -1;
6527}
6528
6529/****************************************************************************/
6530/* */
6531/* Routine Name: ips_shift_controllers */
6532/* */
6533/* Routine Description: */
6534/* helper function for ordering adapters */
6535/****************************************************************************/
6536static void
6537ips_shift_controllers(int lowindex, int highindex)
6538{
6539 ips_ha_t *ha_sav = ips_ha[highindex];
6540 struct Scsi_Host *sh_sav = ips_sh[highindex];
6541 int i;
6542
6543 for (i = highindex; i > lowindex; i--) {
6544 ips_ha[i] = ips_ha[i - 1];
6545 ips_sh[i] = ips_sh[i - 1];
6546 ips_ha[i]->host_num = i;
6547 }
6548 ha_sav->host_num = lowindex;
6549 ips_ha[lowindex] = ha_sav;
6550 ips_sh[lowindex] = sh_sav;
6551}
6552
6553/****************************************************************************/
6554/* */
6555/* Routine Name: ips_order_controllers */
6556/* */
6557/* Routine Description: */
6558/* place controllers is the "proper" boot order */
6559/****************************************************************************/
6560static void
6561ips_order_controllers(void)
6562{
6563 int i, j, tmp, position = 0;
6564 IPS_NVRAM_P5 *nvram;
6565 if (!ips_ha[0])
6566 return;
6567 nvram = ips_ha[0]->nvram;
6568
6569 if (nvram->adapter_order[0]) {
6570 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6571 for (j = position; j < ips_num_controllers; j++) {
6572 switch (ips_ha[j]->ad_type) {
6573 case IPS_ADTYPE_SERVERAID6M:
6574 case IPS_ADTYPE_SERVERAID7M:
6575 if (nvram->adapter_order[i] == 'M') {
6576 ips_shift_controllers(position,
6577 j);
6578 position++;
6579 }
6580 break;
6581 case IPS_ADTYPE_SERVERAID4L:
6582 case IPS_ADTYPE_SERVERAID4M:
6583 case IPS_ADTYPE_SERVERAID4MX:
6584 case IPS_ADTYPE_SERVERAID4LX:
6585 if (nvram->adapter_order[i] == 'N') {
6586 ips_shift_controllers(position,
6587 j);
6588 position++;
6589 }
6590 break;
6591 case IPS_ADTYPE_SERVERAID6I:
6592 case IPS_ADTYPE_SERVERAID5I2:
6593 case IPS_ADTYPE_SERVERAID5I1:
6594 case IPS_ADTYPE_SERVERAID7k:
6595 if (nvram->adapter_order[i] == 'S') {
6596 ips_shift_controllers(position,
6597 j);
6598 position++;
6599 }
6600 break;
6601 case IPS_ADTYPE_SERVERAID:
6602 case IPS_ADTYPE_SERVERAID2:
6603 case IPS_ADTYPE_NAVAJO:
6604 case IPS_ADTYPE_KIOWA:
6605 case IPS_ADTYPE_SERVERAID3L:
6606 case IPS_ADTYPE_SERVERAID3:
6607 case IPS_ADTYPE_SERVERAID4H:
6608 if (nvram->adapter_order[i] == 'A') {
6609 ips_shift_controllers(position,
6610 j);
6611 position++;
6612 }
6613 break;
6614 default:
6615 break;
6616 }
6617 }
6618 }
6619 /* if adapter_order[0], then ordering is complete */
6620 return;
6621 }
6622 /* old bios, use older ordering */
6623 tmp = 0;
6624 for (i = position; i < ips_num_controllers; i++) {
6625 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6626 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6627 ips_shift_controllers(position, i);
6628 position++;
6629 tmp = 1;
6630 }
6631 }
6632 /* if there were no 5I cards, then don't do any extra ordering */
6633 if (!tmp)
6634 return;
6635 for (i = position; i < ips_num_controllers; i++) {
6636 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6637 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6638 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6639 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6640 ips_shift_controllers(position, i);
6641 position++;
6642 }
6643 }
6644
6645 return;
6646}
6647
6648/****************************************************************************/
6649/* */
6650/* Routine Name: ips_register_scsi */
6651/* */
6652/* Routine Description: */
6653/* perform any registration and setup with the scsi layer */
6654/****************************************************************************/
6655static int
6656ips_register_scsi(int index)
6657{
6658 struct Scsi_Host *sh;
6659 ips_ha_t *ha, *oldha = ips_ha[index];
6660 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6661 if (!sh) {
6662 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6663 "Unable to register controller with SCSI subsystem\n");
6664 return -1;
6665 }
6666 ha = IPS_HA(sh);
6667 memcpy(ha, oldha, sizeof (ips_ha_t));
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6668 free_irq(oldha->pcidev->irq, oldha);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6669 /* Install the interrupt handler with the new ha */
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]6670 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6671 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6672 "Unable to install interrupt handler\n");
Jeff Garzik2551a132007-12-13 16:14:10 -0800[diff] [blame]6673 goto err_out_sh;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6674 }
6675
6676 kfree(oldha);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6677
6678 /* Store away needed values for later use */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6679 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6680 sh->sg_tablesize = sh->hostt->sg_tablesize;
6681 sh->can_queue = sh->hostt->can_queue;
6682 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6683 sh->max_sectors = 128;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6684
6685 sh->max_id = ha->ntargets;
6686 sh->max_lun = ha->nlun;
6687 sh->max_channel = ha->nbus - 1;
6688 sh->can_queue = ha->max_cmds - 1;
6689
Jeff Garzik2551a132007-12-13 16:14:10 -0800[diff] [blame]6690 if (scsi_add_host(sh, &ha->pcidev->dev))
6691 goto err_out;
6692
6693 ips_sh[index] = sh;
6694 ips_ha[index] = ha;
6695
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]6696 scsi_scan_host(sh);
6697
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6698 return 0;
Jeff Garzik2551a132007-12-13 16:14:10 -0800[diff] [blame]6699
6700err_out:
6701 free_irq(ha->pcidev->irq, ha);
6702err_out_sh:
6703 scsi_host_put(sh);
6704 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6705}
6706
6707/*---------------------------------------------------------------------------*/
6708/* Routine Name: ips_remove_device */
6709/* */
6710/* Routine Description: */
6711/* Remove one Adapter ( Hot Plugging ) */
6712/*---------------------------------------------------------------------------*/
Greg Kroah-Hartman6f039792012-12-21 13:08:55 -0800[diff] [blame]6713static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6714ips_remove_device(struct pci_dev *pci_dev)
6715{
Jeff Garzik21e1a5f2007-12-13 16:14:09 -0800[diff] [blame]6716 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6717
Jeff Garzik21e1a5f2007-12-13 16:14:09 -0800[diff] [blame]6718 pci_set_drvdata(pci_dev, NULL);
6719
6720 ips_release(sh);
6721
6722 pci_release_regions(pci_dev);
6723 pci_disable_device(pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6724}
6725
6726/****************************************************************************/
6727/* */
6728/* Routine Name: ips_module_init */
6729/* */
6730/* Routine Description: */
6731/* function called on module load */
6732/****************************************************************************/
6733static int __init
6734ips_module_init(void)
6735{
James Bottomleye03c2da2015-05-19 11:38:17 -0700[diff] [blame]6736#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
6737 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n");
6738 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
6739#endif
6740
Alan Cox02a0fa62006-09-25 23:45:51 +0100[diff] [blame]6741 if (pci_register_driver(&ips_pci_driver) < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6742 return -ENODEV;
6743 ips_driver_template.module = THIS_MODULE;
6744 ips_order_controllers();
Adrian Bunkc6a6c812007-05-23 14:41:46 -0700[diff] [blame]6745 if (!ips_detect(&ips_driver_template)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6746 pci_unregister_driver(&ips_pci_driver);
6747 return -ENODEV;
6748 }
6749 register_reboot_notifier(&ips_notifier);
6750 return 0;
6751}
6752
6753/****************************************************************************/
6754/* */
6755/* Routine Name: ips_module_exit */
6756/* */
6757/* Routine Description: */
6758/* function called on module unload */
6759/****************************************************************************/
6760static void __exit
6761ips_module_exit(void)
6762{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6763 pci_unregister_driver(&ips_pci_driver);
6764 unregister_reboot_notifier(&ips_notifier);
6765}
6766
6767module_init(ips_module_init);
6768module_exit(ips_module_exit);
6769
6770/*---------------------------------------------------------------------------*/
6771/* Routine Name: ips_insert_device */
6772/* */
6773/* Routine Description: */
6774/* Add One Adapter ( Hot Plug ) */
6775/* */
6776/* Return Value: */
6777/* 0 if Successful, else non-zero */
6778/*---------------------------------------------------------------------------*/
Greg Kroah-Hartman6f039792012-12-21 13:08:55 -0800[diff] [blame]6779static int
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6780ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6781{
Jeff Garzik21e1a5f2007-12-13 16:14:09 -0800[diff] [blame]6782 int index = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6783 int rc;
6784
6785 METHOD_TRACE("ips_insert_device", 1);
Jeff Garzik21e1a5f2007-12-13 16:14:09 -0800[diff] [blame]6786 rc = pci_enable_device(pci_dev);
6787 if (rc)
6788 return rc;
6789
6790 rc = pci_request_regions(pci_dev, "ips");
6791 if (rc)
6792 goto err_out;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6793
6794 rc = ips_init_phase1(pci_dev, &index);
6795 if (rc == SUCCESS)
6796 rc = ips_init_phase2(index);
6797
6798 if (ips_hotplug)
6799 if (ips_register_scsi(index)) {
6800 ips_free(ips_ha[index]);
6801 rc = -1;
6802 }
6803
6804 if (rc == SUCCESS)
6805 ips_num_controllers++;
6806
6807 ips_next_controller = ips_num_controllers;
Jeff Garzik21e1a5f2007-12-13 16:14:09 -0800[diff] [blame]6808
6809 if (rc < 0) {
6810 rc = -ENODEV;
6811 goto err_out_regions;
6812 }
6813
6814 pci_set_drvdata(pci_dev, ips_sh[index]);
6815 return 0;
6816
6817err_out_regions:
6818 pci_release_regions(pci_dev);
6819err_out:
6820 pci_disable_device(pci_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6821 return rc;
6822}
6823
6824/*---------------------------------------------------------------------------*/
6825/* Routine Name: ips_init_phase1 */
6826/* */
6827/* Routine Description: */
6828/* Adapter Initialization */
6829/* */
6830/* Return Value: */
6831/* 0 if Successful, else non-zero */
6832/*---------------------------------------------------------------------------*/
6833static int
6834ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6835{
6836 ips_ha_t *ha;
6837 uint32_t io_addr;
6838 uint32_t mem_addr;
6839 uint32_t io_len;
6840 uint32_t mem_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6841 int j;
6842 int index;
6843 dma_addr_t dma_address;
6844 char __iomem *ioremap_ptr;
6845 char __iomem *mem_ptr;
6846 uint32_t IsDead;
6847
6848 METHOD_TRACE("ips_init_phase1", 1);
6849 index = IPS_MAX_ADAPTERS;
6850 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
Jeff Garzik21e1a5f2007-12-13 16:14:09 -0800[diff] [blame]6851 if (ips_ha[j] == NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6852 index = j;
6853 break;
6854 }
6855 }
6856
6857 if (index >= IPS_MAX_ADAPTERS)
6858 return -1;
6859
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6860 /* Init MEM/IO addresses to 0 */
6861 mem_addr = 0;
6862 io_addr = 0;
6863 mem_len = 0;
6864 io_len = 0;
6865
6866 for (j = 0; j < 2; j++) {
6867 if (!pci_resource_start(pci_dev, j))
6868 break;
6869
6870 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6871 io_addr = pci_resource_start(pci_dev, j);
6872 io_len = pci_resource_len(pci_dev, j);
6873 } else {
6874 mem_addr = pci_resource_start(pci_dev, j);
6875 mem_len = pci_resource_len(pci_dev, j);
6876 }
6877 }
6878
6879 /* setup memory mapped area (if applicable) */
6880 if (mem_addr) {
6881 uint32_t base;
6882 uint32_t offs;
6883
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6884 base = mem_addr & PAGE_MASK;
6885 offs = mem_addr - base;
6886 ioremap_ptr = ioremap(base, PAGE_SIZE);
Jeff Garzik21e1a5f2007-12-13 16:14:09 -0800[diff] [blame]6887 if (!ioremap_ptr)
6888 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6889 mem_ptr = ioremap_ptr + offs;
6890 } else {
6891 ioremap_ptr = NULL;
6892 mem_ptr = NULL;
6893 }
6894
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6895 /* found a controller */
Yoann Padioleaudd00cc42007-07-19 01:49:03 -0700[diff] [blame]6896 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6897 if (ha == NULL) {
6898 IPS_PRINTK(KERN_WARNING, pci_dev,
6899 "Unable to allocate temporary ha struct\n");
6900 return -1;
6901 }
6902
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6903 ips_sh[index] = NULL;
6904 ips_ha[index] = ha;
6905 ha->active = 1;
6906
6907 /* Store info in HA structure */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6908 ha->io_addr = io_addr;
6909 ha->io_len = io_len;
6910 ha->mem_addr = mem_addr;
6911 ha->mem_len = mem_len;
6912 ha->mem_ptr = mem_ptr;
6913 ha->ioremap_ptr = ioremap_ptr;
6914 ha->host_num = (uint32_t) index;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6915 ha->slot_num = PCI_SLOT(pci_dev->devfn);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6916 ha->pcidev = pci_dev;
6917
6918 /*
6919 * Set the pci_dev's dma_mask. Not all adapters support 64bit
6920 * addressing so don't enable it if the adapter can't support
6921 * it! Also, don't use 64bit addressing if dma addresses
6922 * are guaranteed to be < 4G.
6923 */
Christoph Hellwig88693b32018-10-18 15:03:34 +0200[diff] [blame]6924 if (sizeof(dma_addr_t) > 4 && IPS_HAS_ENH_SGLIST(ha) &&
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]6925 !dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(64))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6926 (ha)->flags |= IPS_HA_ENH_SG;
6927 } else {
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]6928 if (dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(32)) != 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6929 printk(KERN_WARNING "Unable to set DMA Mask\n");
6930 return ips_abort_init(ha, index);
6931 }
6932 }
6933 if(ips_cd_boot && !ips_FlashData){
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]6934 ips_FlashData = dma_alloc_coherent(&pci_dev->dev,
6935 PAGE_SIZE << 7, &ips_flashbusaddr, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6936 }
6937
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]6938 ha->enq = dma_alloc_coherent(&pci_dev->dev, sizeof (IPS_ENQ),
6939 &ha->enq_busaddr, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6940 if (!ha->enq) {
6941 IPS_PRINTK(KERN_WARNING, pci_dev,
6942 "Unable to allocate host inquiry structure\n");
6943 return ips_abort_init(ha, index);
6944 }
6945
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]6946 ha->adapt = dma_alloc_coherent(&pci_dev->dev,
6947 sizeof (IPS_ADAPTER) + sizeof (IPS_IO_CMD),
6948 &dma_address, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6949 if (!ha->adapt) {
6950 IPS_PRINTK(KERN_WARNING, pci_dev,
6951 "Unable to allocate host adapt & dummy structures\n");
6952 return ips_abort_init(ha, index);
6953 }
6954 ha->adapt->hw_status_start = dma_address;
6955 ha->dummy = (void *) (ha->adapt + 1);
6956
6957
6958
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]6959 ha->logical_drive_info = dma_alloc_coherent(&pci_dev->dev,
6960 sizeof (IPS_LD_INFO), &dma_address, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]6961 if (!ha->logical_drive_info) {
6962 IPS_PRINTK(KERN_WARNING, pci_dev,
6963 "Unable to allocate logical drive info structure\n");
6964 return ips_abort_init(ha, index);
6965 }
6966 ha->logical_drive_info_dma_addr = dma_address;
6967
6968
6969 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
6970
6971 if (!ha->conf) {
6972 IPS_PRINTK(KERN_WARNING, pci_dev,
6973 "Unable to allocate host conf structure\n");
6974 return ips_abort_init(ha, index);
6975 }
6976
6977 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
6978
6979 if (!ha->nvram) {
6980 IPS_PRINTK(KERN_WARNING, pci_dev,
6981 "Unable to allocate host NVRAM structure\n");
6982 return ips_abort_init(ha, index);
6983 }
6984
6985 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
6986
6987 if (!ha->subsys) {
6988 IPS_PRINTK(KERN_WARNING, pci_dev,
6989 "Unable to allocate host subsystem structure\n");
6990 return ips_abort_init(ha, index);
6991 }
6992
6993 /* the ioctl buffer is now used during adapter initialization, so its
6994 * successful allocation is now required */
6995 if (ips_ioctlsize < PAGE_SIZE)
6996 ips_ioctlsize = PAGE_SIZE;
6997
Christoph Hellwig32e76962018-10-11 10:15:35 +0200[diff] [blame]6998 ha->ioctl_data = dma_alloc_coherent(&pci_dev->dev, ips_ioctlsize,
6999 &ha->ioctl_busaddr, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]7000 ha->ioctl_len = ips_ioctlsize;
7001 if (!ha->ioctl_data) {
7002 IPS_PRINTK(KERN_WARNING, pci_dev,
7003 "Unable to allocate IOCTL data\n");
7004 return ips_abort_init(ha, index);
7005 }
7006
7007 /*
7008 * Setup Functions
7009 */
7010 ips_setup_funclist(ha);
7011
7012 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7013 /* If Morpheus appears dead, reset it */
7014 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7015 if (IsDead == 0xDEADBEEF) {
7016 ips_reset_morpheus(ha);
7017 }
7018 }
7019
7020 /*
7021 * Initialize the card if it isn't already
7022 */
7023
7024 if (!(*ha->func.isinit) (ha)) {
7025 if (!(*ha->func.init) (ha)) {
7026 /*
7027 * Initialization failed
7028 */
7029 IPS_PRINTK(KERN_WARNING, pci_dev,
7030 "Unable to initialize controller\n");
7031 return ips_abort_init(ha, index);
7032 }
7033 }
7034
7035 *indexPtr = index;
7036 return SUCCESS;
7037}
7038
7039/*---------------------------------------------------------------------------*/
7040/* Routine Name: ips_init_phase2 */
7041/* */
7042/* Routine Description: */
7043/* Adapter Initialization Phase 2 */
7044/* */
7045/* Return Value: */
7046/* 0 if Successful, else non-zero */
7047/*---------------------------------------------------------------------------*/
7048static int
7049ips_init_phase2(int index)
7050{
7051 ips_ha_t *ha;
7052
7053 ha = ips_ha[index];
7054
7055 METHOD_TRACE("ips_init_phase2", 1);
7056 if (!ha->active) {
7057 ips_ha[index] = NULL;
7058 return -1;
7059 }
7060
7061 /* Install the interrupt handler */
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]7062 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]7063 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7064 "Unable to install interrupt handler\n");
7065 return ips_abort_init(ha, index);
7066 }
7067
7068 /*
7069 * Allocate a temporary SCB for initialization
7070 */
7071 ha->max_cmds = 1;
7072 if (!ips_allocatescbs(ha)) {
7073 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7074 "Unable to allocate a CCB\n");
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]7075 free_irq(ha->pcidev->irq, ha);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]7076 return ips_abort_init(ha, index);
7077 }
7078
7079 if (!ips_hainit(ha)) {
7080 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7081 "Unable to initialize controller\n");
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]7082 free_irq(ha->pcidev->irq, ha);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]7083 return ips_abort_init(ha, index);
7084 }
7085 /* Free the temporary SCB */
7086 ips_deallocatescbs(ha, 1);
7087
7088 /* allocate CCBs */
7089 if (!ips_allocatescbs(ha)) {
7090 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7091 "Unable to allocate CCBs\n");
Jeff Garzik8a694cc2007-12-13 16:14:07 -0800[diff] [blame]7092 free_irq(ha->pcidev->irq, ha);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]7093 return ips_abort_init(ha, index);
7094 }
7095
7096 return SUCCESS;
7097}
7098
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]7099MODULE_LICENSE("GPL");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]7100MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]7101MODULE_VERSION(IPS_VER_STRING);