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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 *
6 * Copyright (C) 2001 Ralf Baechle
Ralf Baechle70342282013-01-22 12:59:30 +01007 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
8 * Author: Maciej W. Rozycki <macro@mips.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
10 * This file define the irq handler for MIPS CPU interrupts.
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
12
13/*
14 * Almost all MIPS CPUs define 8 interrupt sources. They are typically
15 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
Paul Burton3838a542017-03-30 12:06:11 -070016 * device).
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 *
Paul Burton3838a542017-03-30 12:06:11 -070018 * The first two are software interrupts (i.e. not exposed as pins) which
19 * may be used for IPIs in multi-threaded single-core systems.
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 *
Paul Burton3838a542017-03-30 12:06:11 -070021 * The last one is usually the CPU timer interrupt if the counter register
22 * is present, or for old CPUs with an external FPU by convention it's the
23 * FPU exception interrupt.
Linus Torvalds1da177e2005-04-16 15:20:36 -070024 */
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
David Howellsca4d3e672010-10-07 14:08:54 +010028#include <linux/irq.h>
Joel Porquet41a83e062015-07-07 17:11:46 -040029#include <linux/irqchip.h>
Gabor Juhos0916b462013-01-31 12:20:43 +000030#include <linux/irqdomain.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
32#include <asm/irq_cpu.h>
33#include <asm/mipsregs.h>
Ralf Baechled03d0a52005-08-17 13:44:26 +000034#include <asm/mipsmtregs.h>
Andrew Brestickerf64e55d2014-09-18 14:47:10 -070035#include <asm/setup.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
Paul Burton131735a2017-03-30 12:06:10 -070037static struct irq_domain *irq_domain;
Paul Burton3838a542017-03-30 12:06:11 -070038static struct irq_domain *ipi_domain;
Paul Burton131735a2017-03-30 12:06:10 -070039
Thomas Gleixnera93951c2011-03-23 21:09:02 +000040static inline void unmask_mips_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070041{
Paul Burton131735a2017-03-30 12:06:10 -070042 set_c0_status(IE_SW0 << d->hwirq);
Ralf Baechle569f75b2005-07-13 18:20:33 +000043 irq_enable_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -070044}
45
Thomas Gleixnera93951c2011-03-23 21:09:02 +000046static inline void mask_mips_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -070047{
Paul Burton131735a2017-03-30 12:06:10 -070048 clear_c0_status(IE_SW0 << d->hwirq);
Ralf Baechle569f75b2005-07-13 18:20:33 +000049 irq_disable_hazard();
Linus Torvalds1da177e2005-04-16 15:20:36 -070050}
51
Ralf Baechle94dee172006-07-02 14:41:42 +010052static struct irq_chip mips_cpu_irq_controller = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +090053 .name = "MIPS",
Thomas Gleixnera93951c2011-03-23 21:09:02 +000054 .irq_ack = mask_mips_irq,
55 .irq_mask = mask_mips_irq,
56 .irq_mask_ack = mask_mips_irq,
57 .irq_unmask = unmask_mips_irq,
58 .irq_eoi = unmask_mips_irq,
Felix Fietkaua3e6c1e2015-01-15 19:05:28 +010059 .irq_disable = mask_mips_irq,
60 .irq_enable = unmask_mips_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070061};
62
Ralf Baechled03d0a52005-08-17 13:44:26 +000063/*
64 * Basically the same as above but taking care of all the MT stuff
65 */
66
Thomas Gleixnera93951c2011-03-23 21:09:02 +000067static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
Ralf Baechled03d0a52005-08-17 13:44:26 +000068{
69 unsigned int vpflags = dvpe();
70
Paul Burton131735a2017-03-30 12:06:10 -070071 clear_c0_cause(C_SW0 << d->hwirq);
Ralf Baechled03d0a52005-08-17 13:44:26 +000072 evpe(vpflags);
Thomas Gleixnera93951c2011-03-23 21:09:02 +000073 unmask_mips_irq(d);
Ralf Baechled03d0a52005-08-17 13:44:26 +000074 return 0;
75}
76
Ralf Baechled03d0a52005-08-17 13:44:26 +000077/*
78 * While we ack the interrupt interrupts are disabled and thus we don't need
79 * to deal with concurrency issues. Same for mips_cpu_irq_end.
80 */
Thomas Gleixnera93951c2011-03-23 21:09:02 +000081static void mips_mt_cpu_irq_ack(struct irq_data *d)
Ralf Baechled03d0a52005-08-17 13:44:26 +000082{
83 unsigned int vpflags = dvpe();
Paul Burton131735a2017-03-30 12:06:10 -070084 clear_c0_cause(C_SW0 << d->hwirq);
Ralf Baechled03d0a52005-08-17 13:44:26 +000085 evpe(vpflags);
Thomas Gleixnera93951c2011-03-23 21:09:02 +000086 mask_mips_irq(d);
Ralf Baechled03d0a52005-08-17 13:44:26 +000087}
88
Paul Burton3838a542017-03-30 12:06:11 -070089#ifdef CONFIG_GENERIC_IRQ_IPI
90
91static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu)
92{
93 irq_hw_number_t hwirq = irqd_to_hwirq(d);
94 unsigned long flags;
95 int vpflags;
96
97 local_irq_save(flags);
98
99 /* We can only send IPIs to VPEs within the local core */
Paul Burtonfe7a38c2017-08-12 19:49:37 -0700100 WARN_ON(!cpus_are_siblings(smp_processor_id(), cpu));
Paul Burton3838a542017-03-30 12:06:11 -0700101
102 vpflags = dvpe();
103 settc(cpu_vpe_id(&cpu_data[cpu]));
104 write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq));
105 evpe(vpflags);
106
107 local_irq_restore(flags);
108}
109
110#endif /* CONFIG_GENERIC_IRQ_IPI */
111
Ralf Baechle94dee172006-07-02 14:41:42 +0100112static struct irq_chip mips_mt_cpu_irq_controller = {
Atsushi Nemoto70d21cd2007-01-15 00:07:25 +0900113 .name = "MIPS",
Thomas Gleixnera93951c2011-03-23 21:09:02 +0000114 .irq_startup = mips_mt_cpu_irq_startup,
115 .irq_ack = mips_mt_cpu_irq_ack,
116 .irq_mask = mask_mips_irq,
117 .irq_mask_ack = mips_mt_cpu_irq_ack,
118 .irq_unmask = unmask_mips_irq,
119 .irq_eoi = unmask_mips_irq,
Felix Fietkaua3e6c1e2015-01-15 19:05:28 +0100120 .irq_disable = mask_mips_irq,
121 .irq_enable = unmask_mips_irq,
Paul Burton3838a542017-03-30 12:06:11 -0700122#ifdef CONFIG_GENERIC_IRQ_IPI
123 .ipi_send_single = mips_mt_send_ipi,
124#endif
Ralf Baechled03d0a52005-08-17 13:44:26 +0000125};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126
Andrew Bresticker85f7cda2014-09-18 14:47:09 -0700127asmlinkage void __weak plat_irq_dispatch(void)
128{
129 unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
130 int irq;
131
132 if (!pending) {
133 spurious_interrupt();
134 return;
135 }
136
137 pending >>= CAUSEB_IP;
138 while (pending) {
Marc Zyngier1fee9db2021-07-06 11:38:59 +0100139 struct irq_domain *d;
140
Andrew Bresticker85f7cda2014-09-18 14:47:09 -0700141 irq = fls(pending) - 1;
Paul Burton3838a542017-03-30 12:06:11 -0700142 if (IS_ENABLED(CONFIG_GENERIC_IRQ_IPI) && irq < 2)
Marc Zyngier1fee9db2021-07-06 11:38:59 +0100143 d = ipi_domain;
Paul Burton3838a542017-03-30 12:06:11 -0700144 else
Marc Zyngier1fee9db2021-07-06 11:38:59 +0100145 d = irq_domain;
146
147 do_domain_IRQ(d, irq);
Andrew Bresticker85f7cda2014-09-18 14:47:09 -0700148 pending &= ~BIT(irq);
149 }
150}
151
Gabor Juhos0916b462013-01-31 12:20:43 +0000152static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
153 irq_hw_number_t hw)
154{
Julia Lawall82faeff2017-07-15 22:07:41 +0200155 struct irq_chip *chip;
Gabor Juhos0916b462013-01-31 12:20:43 +0000156
157 if (hw < 2 && cpu_has_mipsmt) {
158 /* Software interrupts are used for MT/CMT IPI */
159 chip = &mips_mt_cpu_irq_controller;
160 } else {
161 chip = &mips_cpu_irq_controller;
162 }
163
Andrew Brestickerf64e55d2014-09-18 14:47:10 -0700164 if (cpu_has_vint)
165 set_vi_handler(hw, plat_irq_dispatch);
166
Gabor Juhos0916b462013-01-31 12:20:43 +0000167 irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
168
169 return 0;
170}
171
172static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
173 .map = mips_cpu_intc_map,
174 .xlate = irq_domain_xlate_onecell,
175};
176
Paul Burton3838a542017-03-30 12:06:11 -0700177#ifdef CONFIG_GENERIC_IRQ_IPI
178
179struct cpu_ipi_domain_state {
180 DECLARE_BITMAP(allocated, 2);
181};
182
183static int mips_cpu_ipi_alloc(struct irq_domain *domain, unsigned int virq,
184 unsigned int nr_irqs, void *arg)
185{
186 struct cpu_ipi_domain_state *state = domain->host_data;
187 unsigned int i, hwirq;
188 int ret;
189
190 for (i = 0; i < nr_irqs; i++) {
191 hwirq = find_first_zero_bit(state->allocated, 2);
192 if (hwirq == 2)
193 return -EBUSY;
194 bitmap_set(state->allocated, hwirq, 1);
195
196 ret = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq,
197 &mips_mt_cpu_irq_controller,
198 NULL);
199 if (ret)
200 return ret;
201
Mathias Kresin599b3062021-01-07 22:36:03 +0100202 ret = irq_domain_set_hwirq_and_chip(domain->parent, virq + i, hwirq,
203 &mips_mt_cpu_irq_controller,
204 NULL);
205
206 if (ret)
207 return ret;
208
Paul Burton3838a542017-03-30 12:06:11 -0700209 ret = irq_set_irq_type(virq + i, IRQ_TYPE_LEVEL_HIGH);
210 if (ret)
211 return ret;
212 }
213
214 return 0;
215}
216
217static int mips_cpu_ipi_match(struct irq_domain *d, struct device_node *node,
218 enum irq_domain_bus_token bus_token)
219{
220 bool is_ipi;
221
222 switch (bus_token) {
223 case DOMAIN_BUS_IPI:
224 is_ipi = d->bus_token == bus_token;
225 return (!node || (to_of_node(d->fwnode) == node)) && is_ipi;
226 default:
227 return 0;
228 }
229}
230
231static const struct irq_domain_ops mips_cpu_ipi_chip_ops = {
232 .alloc = mips_cpu_ipi_alloc,
233 .match = mips_cpu_ipi_match,
234};
235
236static void mips_cpu_register_ipi_domain(struct device_node *of_node)
237{
238 struct cpu_ipi_domain_state *ipi_domain_state;
239
240 ipi_domain_state = kzalloc(sizeof(*ipi_domain_state), GFP_KERNEL);
241 ipi_domain = irq_domain_add_hierarchy(irq_domain,
242 IRQ_DOMAIN_FLAG_IPI_SINGLE,
243 2, of_node,
244 &mips_cpu_ipi_chip_ops,
245 ipi_domain_state);
246 if (!ipi_domain)
247 panic("Failed to add MIPS CPU IPI domain");
Marc Zyngier96f0d932017-06-22 11:42:50 +0100248 irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
Paul Burton3838a542017-03-30 12:06:11 -0700249}
250
251#else /* !CONFIG_GENERIC_IRQ_IPI */
252
253static inline void mips_cpu_register_ipi_domain(struct device_node *of_node) {}
254
255#endif /* !CONFIG_GENERIC_IRQ_IPI */
256
Andrew Bresticker0f84c302014-09-18 14:47:07 -0700257static void __init __mips_cpu_irq_init(struct device_node *of_node)
Gabor Juhos0916b462013-01-31 12:20:43 +0000258{
Gabor Juhos0916b462013-01-31 12:20:43 +0000259 /* Mask interrupts. */
260 clear_c0_status(ST0_IM);
261 clear_c0_cause(CAUSEF_IP);
262
Paul Burton131735a2017-03-30 12:06:10 -0700263 irq_domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
264 &mips_cpu_intc_irq_domain_ops,
265 NULL);
266 if (!irq_domain)
Ralf Baechlef7777dc2013-09-18 16:05:26 +0200267 panic("Failed to add irqdomain for MIPS CPU");
Paul Burton3838a542017-03-30 12:06:11 -0700268
269 /*
270 * Only proceed to register the software interrupt IPI implementation
271 * for CPUs which implement the MIPS MT (multi-threading) ASE.
272 */
273 if (cpu_has_mipsmt)
274 mips_cpu_register_ipi_domain(of_node);
Andrew Bresticker0f84c302014-09-18 14:47:07 -0700275}
Gabor Juhos0916b462013-01-31 12:20:43 +0000276
Andrew Bresticker0f84c302014-09-18 14:47:07 -0700277void __init mips_cpu_irq_init(void)
278{
279 __mips_cpu_irq_init(NULL);
280}
281
Andrew Brestickerafe8dc22014-09-18 14:47:08 -0700282int __init mips_cpu_irq_of_init(struct device_node *of_node,
283 struct device_node *parent)
Andrew Bresticker0f84c302014-09-18 14:47:07 -0700284{
285 __mips_cpu_irq_init(of_node);
Gabor Juhos0916b462013-01-31 12:20:43 +0000286 return 0;
287}
Paul Burton892b8cf2015-05-24 16:11:16 +0100288IRQCHIP_DECLARE(cpu_intc, "mti,cpu-interrupt-controller", mips_cpu_irq_of_init);