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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
Hyok S. Choid090ddd2006-06-28 14:10:01 +01006 * hacked for non-paged-MM by Hyok S. Choi, 2003.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
Linus Torvalds1da177e2005-04-16 15:20:36 -070025 */
26#include <linux/linkage.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027#include <linux/init.h>
28#include <asm/assembler.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +020029#include <asm/asm-offsets.h>
Russell King5ec94072008-09-07 19:15:31 +010030#include <asm/hwcap.h>
Russell King74945c82006-03-16 14:44:36 +000031#include <asm/pgtable-hwdef.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070032#include <asm/pgtable.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033#include <asm/ptrace.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070034
Russell King00eb0f62006-07-03 12:36:07 +010035#include "proc-macros.S"
36
Linus Torvalds1da177e2005-04-16 15:20:36 -070037/*
38 * This is the maximum size of an area which will be invalidated
39 * using the single invalidate entry instructions. Anything larger
40 * than this, and we go for the whole cache.
41 *
42 * This value should be chosen such that we choose the cheapest
43 * alternative.
44 */
45#define MAX_AREA_SIZE 32768
46
47/*
48 * The size of one data cache line.
49 */
50#define CACHE_DLINESIZE 32
51
52/*
53 * The number of data cache segments.
54 */
55#define CACHE_DSEGMENTS 16
56
57/*
58 * The number of lines in a cache segment.
59 */
60#define CACHE_DENTRIES 64
61
62/*
63 * This is the size at which it becomes more efficient to
64 * clean the whole cache, rather than using the individual
Lucas De Marchi25985ed2011-03-30 22:57:33 -030065 * cache line maintenance instructions.
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 */
67#define CACHE_DLIMIT 32768
68
69 .text
70/*
71 * cpu_arm1020e_proc_init()
72 */
73ENTRY(cpu_arm1020e_proc_init)
Russell King6ebbf2c2014-06-30 16:29:12 +010074 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76/*
77 * cpu_arm1020e_proc_fin()
78 */
79ENTRY(cpu_arm1020e_proc_fin)
Linus Torvalds1da177e2005-04-16 15:20:36 -070080 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
81 bic r0, r0, #0x1000 @ ...i............
82 bic r0, r0, #0x000e @ ............wca.
83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
Russell King6ebbf2c2014-06-30 16:29:12 +010084 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -070085
86/*
87 * cpu_arm1020e_reset(loc)
88 *
89 * Perform a soft reset of the system. Put the CPU into the
90 * same state as it would be if it had been reset, and branch
91 * to what would be the reset vector.
92 *
93 * loc: location to jump to for soft reset
94 */
95 .align 5
Will Deacon1a4baaf2011-11-15 13:25:04 +000096 .pushsection .idmap.text, "ax"
Linus Torvalds1da177e2005-04-16 15:20:36 -070097ENTRY(cpu_arm1020e_reset)
98 mov ip, #0
99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
100 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100101#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100103#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
105 bic ip, ip, #0x000f @ ............wcam
106 bic ip, ip, #0x1100 @ ...i...s........
107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
Russell King6ebbf2c2014-06-30 16:29:12 +0100108 ret r0
Will Deacon1a4baaf2011-11-15 13:25:04 +0000109ENDPROC(cpu_arm1020e_reset)
110 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111
112/*
113 * cpu_arm1020e_do_idle()
114 */
115 .align 5
116ENTRY(cpu_arm1020e_do_idle)
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
Russell King6ebbf2c2014-06-30 16:29:12 +0100118 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
120/* ================================= CACHE ================================ */
121
122 .align 5
Mika Westerbergc8c90862010-10-28 11:27:40 +0100123
124/*
125 * flush_icache_all()
126 *
127 * Unconditionally clean and invalidate the entire icache.
128 */
129ENTRY(arm1020e_flush_icache_all)
130#ifndef CONFIG_CPU_ICACHE_DISABLE
131 mov r0, #0
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
133#endif
Russell King6ebbf2c2014-06-30 16:29:12 +0100134 ret lr
Mika Westerbergc8c90862010-10-28 11:27:40 +0100135ENDPROC(arm1020e_flush_icache_all)
136
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137/*
138 * flush_user_cache_all()
139 *
140 * Invalidate all cache entries in a particular address
141 * space.
142 */
143ENTRY(arm1020e_flush_user_cache_all)
144 /* FALLTHROUGH */
145/*
146 * flush_kern_cache_all()
147 *
148 * Clean and invalidate the entire cache.
149 */
150ENTRY(arm1020e_flush_kern_cache_all)
151 mov r2, #VM_EXEC
152 mov ip, #0
153__flush_whole_cache:
154#ifndef CONFIG_CPU_DCACHE_DISABLE
155 mcr p15, 0, ip, c7, c10, 4 @ drain WB
156 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
1571: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
1582: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
159 subs r3, r3, #1 << 26
160 bcs 2b @ entries 63 to 0
161 subs r1, r1, #1 << 5
162 bcs 1b @ segments 15 to 0
163#endif
164 tst r2, #VM_EXEC
165#ifndef CONFIG_CPU_ICACHE_DISABLE
166 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
167#endif
168 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
Russell King6ebbf2c2014-06-30 16:29:12 +0100169 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170
171/*
172 * flush_user_cache_range(start, end, flags)
173 *
174 * Invalidate a range of cache entries in the specified
175 * address space.
176 *
177 * - start - start address (inclusive)
178 * - end - end address (exclusive)
179 * - flags - vm_flags for this space
180 */
181ENTRY(arm1020e_flush_user_cache_range)
182 mov ip, #0
183 sub r3, r1, r0 @ calculate total size
184 cmp r3, #CACHE_DLIMIT
185 bhs __flush_whole_cache
186
187#ifndef CONFIG_CPU_DCACHE_DISABLE
1881: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
189 add r0, r0, #CACHE_DLINESIZE
190 cmp r0, r1
191 blo 1b
192#endif
193 tst r2, #VM_EXEC
194#ifndef CONFIG_CPU_ICACHE_DISABLE
195 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
196#endif
197 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
Russell King6ebbf2c2014-06-30 16:29:12 +0100198 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199
200/*
201 * coherent_kern_range(start, end)
202 *
203 * Ensure coherency between the Icache and the Dcache in the
204 * region described by start. If you have non-snooping
205 * Harvard caches, you need to implement this function.
206 *
207 * - start - virtual start address
208 * - end - virtual end address
209 */
210ENTRY(arm1020e_coherent_kern_range)
211 /* FALLTHROUGH */
212/*
213 * coherent_user_range(start, end)
214 *
215 * Ensure coherency between the Icache and the Dcache in the
216 * region described by start. If you have non-snooping
217 * Harvard caches, you need to implement this function.
218 *
219 * - start - virtual start address
220 * - end - virtual end address
221 */
222ENTRY(arm1020e_coherent_user_range)
223 mov ip, #0
224 bic r0, r0, #CACHE_DLINESIZE - 1
2251:
226#ifndef CONFIG_CPU_DCACHE_DISABLE
227 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
228#endif
229#ifndef CONFIG_CPU_ICACHE_DISABLE
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
231#endif
232 add r0, r0, #CACHE_DLINESIZE
233 cmp r0, r1
234 blo 1b
235 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Will Deaconc5102f52012-04-27 13:08:53 +0100236 mov r0, #0
Russell King6ebbf2c2014-06-30 16:29:12 +0100237 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238
239/*
Russell King2c9b9c82009-11-26 12:56:21 +0000240 * flush_kern_dcache_area(void *addr, size_t size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 *
242 * Ensure no D cache aliasing occurs, either with itself or
243 * the I cache
244 *
Russell King2c9b9c82009-11-26 12:56:21 +0000245 * - addr - kernel address
246 * - size - region size
Linus Torvalds1da177e2005-04-16 15:20:36 -0700247 */
Russell King2c9b9c82009-11-26 12:56:21 +0000248ENTRY(arm1020e_flush_kern_dcache_area)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249 mov ip, #0
250#ifndef CONFIG_CPU_DCACHE_DISABLE
Russell King2c9b9c82009-11-26 12:56:21 +0000251 add r1, r0, r1
Linus Torvalds1da177e2005-04-16 15:20:36 -07002521: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
253 add r0, r0, #CACHE_DLINESIZE
254 cmp r0, r1
255 blo 1b
256#endif
257 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Russell King6ebbf2c2014-06-30 16:29:12 +0100258 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259
260/*
261 * dma_inv_range(start, end)
262 *
263 * Invalidate (discard) the specified virtual address range.
264 * May not write back any entries. If 'start' or 'end'
265 * are not cache line aligned, those lines must be written
266 * back.
267 *
268 * - start - virtual start address
269 * - end - virtual end address
270 *
271 * (same as v4wb)
272 */
Russell King702b94b2009-11-26 16:24:19 +0000273arm1020e_dma_inv_range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274 mov ip, #0
275#ifndef CONFIG_CPU_DCACHE_DISABLE
276 tst r0, #CACHE_DLINESIZE - 1
277 bic r0, r0, #CACHE_DLINESIZE - 1
278 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
279 tst r1, #CACHE_DLINESIZE - 1
280 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
2811: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
282 add r0, r0, #CACHE_DLINESIZE
283 cmp r0, r1
284 blo 1b
285#endif
286 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Russell King6ebbf2c2014-06-30 16:29:12 +0100287 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288
289/*
290 * dma_clean_range(start, end)
291 *
292 * Clean the specified virtual address range.
293 *
294 * - start - virtual start address
295 * - end - virtual end address
296 *
297 * (same as v4wb)
298 */
Russell King702b94b2009-11-26 16:24:19 +0000299arm1020e_dma_clean_range:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300 mov ip, #0
301#ifndef CONFIG_CPU_DCACHE_DISABLE
302 bic r0, r0, #CACHE_DLINESIZE - 1
3031: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
304 add r0, r0, #CACHE_DLINESIZE
305 cmp r0, r1
306 blo 1b
307#endif
308 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Russell King6ebbf2c2014-06-30 16:29:12 +0100309 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310
311/*
312 * dma_flush_range(start, end)
313 *
314 * Clean and invalidate the specified virtual address range.
315 *
316 * - start - virtual start address
317 * - end - virtual end address
318 */
319ENTRY(arm1020e_dma_flush_range)
320 mov ip, #0
321#ifndef CONFIG_CPU_DCACHE_DISABLE
322 bic r0, r0, #CACHE_DLINESIZE - 1
3231: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
324 add r0, r0, #CACHE_DLINESIZE
325 cmp r0, r1
326 blo 1b
327#endif
328 mcr p15, 0, ip, c7, c10, 4 @ drain WB
Russell King6ebbf2c2014-06-30 16:29:12 +0100329 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330
Russell Kinga9c91472009-11-26 16:19:58 +0000331/*
332 * dma_map_area(start, size, dir)
333 * - start - kernel virtual start address
334 * - size - size of region
335 * - dir - DMA direction
336 */
337ENTRY(arm1020e_dma_map_area)
338 add r1, r1, r0
339 cmp r2, #DMA_TO_DEVICE
340 beq arm1020e_dma_clean_range
341 bcs arm1020e_dma_inv_range
342 b arm1020e_dma_flush_range
343ENDPROC(arm1020e_dma_map_area)
344
345/*
346 * dma_unmap_area(start, size, dir)
347 * - start - kernel virtual start address
348 * - size - size of region
349 * - dir - DMA direction
350 */
351ENTRY(arm1020e_dma_unmap_area)
Russell King6ebbf2c2014-06-30 16:29:12 +0100352 ret lr
Russell Kinga9c91472009-11-26 16:19:58 +0000353ENDPROC(arm1020e_dma_unmap_area)
354
Lorenzo Pieralisi031bd872012-09-06 18:35:13 +0530355 .globl arm1020e_flush_kern_cache_louis
356 .equ arm1020e_flush_kern_cache_louis, arm1020e_flush_kern_cache_all
357
Dave Martinfbaa8402011-06-23 17:17:00 +0100358 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
359 define_cache_functions arm1020e
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360
361 .align 5
362ENTRY(cpu_arm1020e_dcache_clean_area)
363#ifndef CONFIG_CPU_DCACHE_DISABLE
364 mov ip, #0
3651: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
366 add r0, r0, #CACHE_DLINESIZE
367 subs r1, r1, #CACHE_DLINESIZE
368 bhi 1b
369#endif
Russell King6ebbf2c2014-06-30 16:29:12 +0100370 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700371
372/* =============================== PageTable ============================== */
373
374/*
375 * cpu_arm1020e_switch_mm(pgd)
376 *
377 * Set the translation base pointer to be as described by pgd.
378 *
379 * pgd: new page tables
380 */
381 .align 5
382ENTRY(cpu_arm1020e_switch_mm)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100383#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384#ifndef CONFIG_CPU_DCACHE_DISABLE
385 mcr p15, 0, r3, c7, c10, 4
386 mov r1, #0xF @ 16 segments
3871: mov r3, #0x3F @ 64 entries
3882: mov ip, r3, LSL #26 @ shift up entry
389 orr ip, ip, r1, LSL #5 @ shift in/up index
390 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
391 mov ip, #0
392 subs r3, r3, #1
393 cmp r3, #0
394 bge 2b @ entries 3F to 0
395 subs r1, r1, #1
396 cmp r1, #0
397 bge 1b @ segments 15 to 0
398
399#endif
400 mov r1, #0
401#ifndef CONFIG_CPU_ICACHE_DISABLE
402 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
403#endif
404 mcr p15, 0, r1, c7, c10, 4 @ drain WB
405 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
406 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100407#endif
Russell King6ebbf2c2014-06-30 16:29:12 +0100408 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409
410/*
411 * cpu_arm1020e_set_pte(ptep, pte)
412 *
413 * Set a PTE and flush it out
414 */
415 .align 5
Russell Kingad1ae2f2006-12-13 14:34:43 +0000416ENTRY(cpu_arm1020e_set_pte_ext)
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100417#ifdef CONFIG_MMU
Russell Kingda091652008-09-06 17:19:08 +0100418 armv3_set_pte_ext
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419 mov r0, r0
420#ifndef CONFIG_CPU_DCACHE_DISABLE
421 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
422#endif
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100423#endif /* CONFIG_MMU */
Russell King6ebbf2c2014-06-30 16:29:12 +0100424 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425
Linus Torvalds1da177e2005-04-16 15:20:36 -0700426 .type __arm1020e_setup, #function
427__arm1020e_setup:
428 mov r0, #0
429 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
430 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100431#ifdef CONFIG_MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
Hyok S. Choid090ddd2006-06-28 14:10:01 +0100433#endif
Russell King22b190862006-06-29 15:09:57 +0100434 adr r5, arm1020e_crval
435 ldmia r5, {r5, r6}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436 mrc p15, 0, r0, c1, c0 @ get control register v4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437 bic r0, r0, r5
Russell King22b190862006-06-29 15:09:57 +0100438 orr r0, r0, r6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
440 orr r0, r0, #0x4000 @ .R.. .... .... ....
441#endif
Russell King6ebbf2c2014-06-30 16:29:12 +0100442 ret lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 .size __arm1020e_setup, . - __arm1020e_setup
444
445 /*
446 * R
447 * .RVI ZFRS BLDP WCAM
Catalin Marinasabaf48a2005-06-30 17:04:14 +0100448 * .011 1001 ..11 0101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449 */
Russell King22b190862006-06-29 15:09:57 +0100450 .type arm1020e_crval, #object
451arm1020e_crval:
452 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453
454 __INITDATA
Dave Martinfbaa8402011-06-23 17:17:00 +0100455 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
456 define_processor_functions arm1020e, dabort=v4t_early_abort, pabort=legacy_pabort
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457
458 .section ".rodata"
459
Dave Martinfbaa8402011-06-23 17:17:00 +0100460 string cpu_arch_name, "armv5te"
461 string cpu_elf_name, "v5"
462 string cpu_arm1020e_name, "ARM1020E"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463
464 .align
465
Ard Biesheuvelbf357062015-03-18 07:29:32 +0100466 .section ".proc.info.init", #alloc
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467
468 .type __arm1020e_proc_info,#object
469__arm1020e_proc_info:
470 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
471 .long 0xff0ffff0
472 .long PMD_TYPE_SECT | \
473 PMD_BIT4 | \
474 PMD_SECT_AP_WRITE | \
475 PMD_SECT_AP_READ
Russell King8799ee92006-06-29 18:24:21 +0100476 .long PMD_TYPE_SECT | \
477 PMD_BIT4 | \
478 PMD_SECT_AP_WRITE | \
479 PMD_SECT_AP_READ
Ard Biesheuvelbf357062015-03-18 07:29:32 +0100480 initfn __arm1020e_setup, __arm1020e_proc_info
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481 .long cpu_arch_name
482 .long cpu_elf_name
483 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
484 .long cpu_arm1020e_name
485 .long arm1020e_processor_functions
486 .long v4wbi_tlb_fns
487 .long v4wb_user_fns
488 .long arm1020e_cache_fns
489 .size __arm1020e_proc_info, . - __arm1020e_proc_info