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Changbin Dubbea90bb2019-05-08 23:21:35 +08001.. SPDX-License-Identifier: GPL-2.0
2
3===========================
4AMD64 Specific Boot Options
5===========================
6
7There are many others (usually documented in driver documentation), but
8only the AMD64 specific ones are listed here.
9
10Machine check
11=============
Mauro Carvalho Chehabcb1aaeb2019-06-07 15:54:32 -030012Please see Documentation/x86/x86_64/machinecheck.rst for sysfs runtime tunables.
Changbin Dubbea90bb2019-05-08 23:21:35 +080013
14 mce=off
15 Disable machine check
16 mce=no_cmci
17 Disable CMCI(Corrected Machine Check Interrupt) that
18 Intel processor supports. Usually this disablement is
19 not recommended, but it might be handy if your hardware
20 is misbehaving.
21 Note that you'll get more problems without CMCI than with
22 due to the shared banks, i.e. you might get duplicated
23 error logs.
24 mce=dont_log_ce
25 Don't make logs for corrected errors. All events reported
26 as corrected are silently cleared by OS.
27 This option will be useful if you have no interest in any
28 of corrected errors.
29 mce=ignore_ce
30 Disable features for corrected errors, e.g. polling timer
31 and CMCI. All events reported as corrected are not cleared
32 by OS and remained in its error banks.
33 Usually this disablement is not recommended, however if
34 there is an agent checking/clearing corrected errors
35 (e.g. BIOS or hardware monitoring applications), conflicting
36 with OS's error handling, and you cannot deactivate the agent,
37 then this option will be a help.
38 mce=no_lmce
39 Do not opt-in to Local MCE delivery. Use legacy method
40 to broadcast MCEs.
41 mce=bootlog
42 Enable logging of machine checks left over from booting.
43 Disabled by default on AMD Fam10h and older because some BIOS
44 leave bogus ones.
45 If your BIOS doesn't do that it's a good idea to enable though
46 to make sure you log even machine check events that result
47 in a reboot. On Intel systems it is enabled by default.
48 mce=nobootlog
49 Disable boot machine check logging.
50 mce=tolerancelevel[,monarchtimeout] (number,number)
51 tolerance levels:
52 0: always panic on uncorrected errors, log corrected errors
53 1: panic or SIGBUS on uncorrected errors, log corrected errors
54 2: SIGBUS or log uncorrected errors, log corrected errors
55 3: never panic or SIGBUS, log all errors (for testing only)
56 Default is 1
57 Can be also set using sysfs which is preferable.
58 monarchtimeout:
59 Sets the time in us to wait for other CPUs on machine checks. 0
60 to disable.
61 mce=bios_cmci_threshold
62 Don't overwrite the bios-set CMCI threshold. This boot option
63 prevents Linux from overwriting the CMCI threshold set by the
64 bios. Without this option, Linux always sets the CMCI
65 threshold to 1. Enabling this may make memory predictive failure
66 analysis less effective if the bios sets thresholds for memory
67 errors since we will not see details for all errors.
68 mce=recovery
69 Force-enable recoverable machine check code paths
70
71 nomce (for compatibility with i386)
72 same as mce=off
73
74 Everything else is in sysfs now.
75
76APICs
77=====
78
79 apic
80 Use IO-APIC. Default
81
82 noapic
83 Don't use the IO-APIC.
84
85 disableapic
86 Don't use the local APIC
87
88 nolapic
89 Don't use the local APIC (alias for i386 compatibility)
90
91 pirq=...
Mauro Carvalho Chehabcb1aaeb2019-06-07 15:54:32 -030092 See Documentation/x86/i386/IO-APIC.rst
Changbin Dubbea90bb2019-05-08 23:21:35 +080093
94 noapictimer
95 Don't set up the APIC timer
96
97 no_timer_check
98 Don't check the IO-APIC timer. This can work around
99 problems with incorrect timer initialization on some boards.
100
101 apicpmtimer
102 Do APIC timer calibration using the pmtimer. Implies
103 apicmaintimer. Useful when your PIT timer is totally broken.
104
105Timing
106======
107
108 notsc
109 Deprecated, use tsc=unstable instead.
110
111 nohpet
112 Don't use the HPET timer.
113
114Idle loop
115=========
116
117 idle=poll
118 Don't do power saving in the idle loop using HLT, but poll for rescheduling
119 event. This will make the CPUs eat a lot more power, but may be useful
120 to get slightly better performance in multiprocessor benchmarks. It also
121 makes some profiling using performance counters more accurate.
122 Please note that on systems with MONITOR/MWAIT support (like Intel EM64T
123 CPUs) this option has no performance advantage over the normal idle loop.
124 It may also interact badly with hyperthreading.
125
126Rebooting
127=========
128
Paul Gortmaker162a5282021-05-30 12:24:45 -0400129 reboot=b[ios] | t[riple] | k[bd] | a[cpi] | e[fi] | p[ci] [, [w]arm | [c]old]
Changbin Dubbea90bb2019-05-08 23:21:35 +0800130 bios
131 Use the CPU reboot vector for warm reset
132 warm
133 Don't set the cold reboot flag
134 cold
135 Set the cold reboot flag
136 triple
137 Force a triple fault (init)
138 kbd
139 Use the keyboard controller. cold reset (default)
140 acpi
141 Use the ACPI RESET_REG in the FADT. If ACPI is not configured or
142 the ACPI reset does not work, the reboot path attempts the reset
143 using the keyboard controller.
144 efi
145 Use efi reset_system runtime service. If EFI is not configured or
146 the EFI reset does not work, the reboot path attempts the reset using
147 the keyboard controller.
Paul Gortmaker162a5282021-05-30 12:24:45 -0400148 pci
149 Use a write to the PCI config space register 0xcf9 to trigger reboot.
Changbin Dubbea90bb2019-05-08 23:21:35 +0800150
151 Using warm reset will be much faster especially on big memory
152 systems because the BIOS will not go through the memory check.
153 Disadvantage is that not all hardware will be completely reinitialized
154 on reboot so there may be boot problems on some systems.
155
156 reboot=force
157 Don't stop other CPUs on reboot. This can make reboot more reliable
158 in some cases.
159
Paul Gortmaker12febc12021-05-30 12:24:46 -0400160 reboot=default
161 There are some built-in platform specific "quirks" - you may see:
162 "reboot: <name> series board detected. Selecting <type> for reboots."
163 In the case where you think the quirk is in error (e.g. you have
164 newer BIOS, or newer board) using this option will ignore the built-in
165 quirk table, and use the generic default reboot actions.
166
Changbin Dubbea90bb2019-05-08 23:21:35 +0800167Non Executable Mappings
168=======================
169
170 noexec=on|off
171 on
172 Enable(default)
173 off
174 Disable
175
176NUMA
177====
178
179 numa=off
180 Only set up a single NUMA node spanning all memory.
181
182 numa=noacpi
183 Don't parse the SRAT table for NUMA setup
184
Dan Williams3b0d3102020-10-13 16:49:02 -0700185 numa=nohmat
186 Don't parse the HMAT table for NUMA setup, or soft-reserved memory
187 partitioning.
188
Changbin Dubbea90bb2019-05-08 23:21:35 +0800189 numa=fake=<size>[MG]
190 If given as a memory unit, fills all system RAM with nodes of
191 size interleaved over physical nodes.
192
193 numa=fake=<N>
194 If given as an integer, fills all system RAM with N fake nodes
195 interleaved over physical nodes.
196
197 numa=fake=<N>U
198 If given as an integer followed by 'U', it will divide each
199 physical node into N emulated nodes.
200
201ACPI
202====
203
204 acpi=off
205 Don't enable ACPI
206 acpi=ht
207 Use ACPI boot table parsing, but don't enable ACPI interpreter
208 acpi=force
209 Force ACPI on (currently not needed)
210 acpi=strict
211 Disable out of spec ACPI workarounds.
212 acpi_sci={edge,level,high,low}
213 Set up ACPI SCI interrupt.
214 acpi=noirq
215 Don't route interrupts
216 acpi=nocmcff
217 Disable firmware first mode for corrected errors. This
218 disables parsing the HEST CMC error source to check if
219 firmware has set the FF flag. This may result in
220 duplicate corrected error reports.
221
222PCI
223===
224
225 pci=off
226 Don't use PCI
227 pci=conf1
228 Use conf1 access.
229 pci=conf2
230 Use conf2 access.
231 pci=rom
232 Assign ROMs.
233 pci=assign-busses
234 Assign busses
235 pci=irqmask=MASK
236 Set PCI interrupt mask to MASK
237 pci=lastbus=NUMBER
238 Scan up to NUMBER busses, no matter what the mptable says.
239 pci=noacpi
240 Don't use ACPI to set up PCI interrupt routing.
241
242IOMMU (input/output memory management unit)
243===========================================
244Multiple x86-64 PCI-DMA mapping implementations exist, for example:
245
Andy Shevchenko392e8792019-06-19 17:19:55 +0300246 1. <kernel/dma/direct.c>: use no hardware/software IOMMU at all
Changbin Dubbea90bb2019-05-08 23:21:35 +0800247 (e.g. because you have < 3 GB memory).
248 Kernel boot message: "PCI-DMA: Disabling IOMMU"
249
250 2. <arch/x86/kernel/amd_gart_64.c>: AMD GART based hardware IOMMU.
251 Kernel boot message: "PCI-DMA: using GART IOMMU"
252
253 3. <arch/x86_64/kernel/pci-swiotlb.c> : Software IOMMU implementation. Used
254 e.g. if there is no hardware IOMMU in the system and it is need because
255 you have >3GB memory or told the kernel to us it (iommu=soft))
256 Kernel boot message: "PCI-DMA: Using software bounce buffering
257 for IO (SWIOTLB)"
258
Changbin Dubbea90bb2019-05-08 23:21:35 +0800259::
260
261 iommu=[<size>][,noagp][,off][,force][,noforce]
262 [,memaper[=<order>]][,merge][,fullflush][,nomerge]
Hubert Jasudowicz0e5a89d2021-06-09 23:51:12 +0200263 [,noaperture]
Changbin Dubbea90bb2019-05-08 23:21:35 +0800264
265General iommu options:
266
267 off
268 Don't initialize and use any kind of IOMMU.
269 noforce
270 Don't force hardware IOMMU usage when it is not needed. (default).
271 force
272 Force the use of the hardware IOMMU even when it is
273 not actually needed (e.g. because < 3 GB memory).
274 soft
275 Use software bounce buffering (SWIOTLB) (default for
276 Intel machines). This can be used to prevent the usage
277 of an available hardware IOMMU.
278
279iommu options only relevant to the AMD GART hardware IOMMU:
280
281 <size>
282 Set the size of the remapping area in bytes.
283 allowed
284 Overwrite iommu off workarounds for specific chipsets.
285 fullflush
286 Flush IOMMU on each allocation (default).
287 nofullflush
288 Don't use IOMMU fullflush.
289 memaper[=<order>]
290 Allocate an own aperture over RAM with size 32MB<<order.
291 (default: order=1, i.e. 64MB)
292 merge
293 Do scatter-gather (SG) merging. Implies "force" (experimental).
294 nomerge
295 Don't do scatter-gather (SG) merging.
296 noaperture
297 Ask the IOMMU not to touch the aperture for AGP.
298 noagp
299 Don't initialize the AGP driver and use full aperture.
300 panic
301 Always panic when IOMMU overflows.
Changbin Dubbea90bb2019-05-08 23:21:35 +0800302
303iommu options only relevant to the software bounce buffering (SWIOTLB) IOMMU
304implementation:
305
306 swiotlb=<pages>[,force]
307 <pages>
308 Prereserve that many 128K pages for the software IO bounce buffering.
309 force
310 Force all IO through the software TLB.
311
Changbin Dubbea90bb2019-05-08 23:21:35 +0800312
313Miscellaneous
314=============
315
316 nogbpages
317 Do not use GB pages for kernel direct mappings.
318 gbpages
319 Use GB pages for kernel direct mappings.