blob: e66fc57ec35de277287f27aecd578b8aa29678ba [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Tero Kristo657fc112013-07-22 12:29:29 +03002/*
3 * Device Tree Source for OMAP36xx clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
Tero Kristo657fc112013-07-22 12:29:29 +03006 */
7&cm_clocks {
Tero Kristob5b53402016-04-04 18:16:06 +03008 dpll4_ck: dpll4_ck@d00 {
Tero Kristo657fc112013-07-22 12:29:29 +03009 #clock-cells = <0>;
10 compatible = "ti,omap3-dpll-per-j-type-clock";
11 clocks = <&sys_ck>, <&sys_ck>;
12 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
13 };
14
Tero Kristob5b53402016-04-04 18:16:06 +030015 dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
Tero Kristo657fc112013-07-22 12:29:29 +030016 #clock-cells = <0>;
17 compatible = "ti,hsdiv-gate-clock";
18 clocks = <&dpll4_m5x2_mul_ck>;
19 ti,bit-shift = <0x1e>;
20 reg = <0x0d00>;
21 ti,set-rate-parent;
22 ti,set-bit-to-disable;
23 };
24
Tero Kristob5b53402016-04-04 18:16:06 +030025 dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
Tero Kristo657fc112013-07-22 12:29:29 +030026 #clock-cells = <0>;
27 compatible = "ti,hsdiv-gate-clock";
28 clocks = <&dpll4_m2x2_mul_ck>;
29 ti,bit-shift = <0x1b>;
30 reg = <0x0d00>;
31 ti,set-bit-to-disable;
32 };
33
Tero Kristob5b53402016-04-04 18:16:06 +030034 dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
Tero Kristo657fc112013-07-22 12:29:29 +030035 #clock-cells = <0>;
36 compatible = "ti,hsdiv-gate-clock";
37 clocks = <&dpll3_m3x2_mul_ck>;
38 ti,bit-shift = <0xc>;
39 reg = <0x0d00>;
40 ti,set-bit-to-disable;
41 };
42
Tero Kristob5b53402016-04-04 18:16:06 +030043 dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
Tero Kristo657fc112013-07-22 12:29:29 +030044 #clock-cells = <0>;
45 compatible = "ti,hsdiv-gate-clock";
46 clocks = <&dpll4_m3x2_mul_ck>;
47 ti,bit-shift = <0x1c>;
48 reg = <0x0d00>;
49 ti,set-bit-to-disable;
50 };
51
Tero Kristob5b53402016-04-04 18:16:06 +030052 dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
Tero Kristo657fc112013-07-22 12:29:29 +030053 #clock-cells = <0>;
54 compatible = "ti,hsdiv-gate-clock";
55 clocks = <&dpll4_m6x2_mul_ck>;
56 ti,bit-shift = <0x1f>;
57 reg = <0x0d00>;
58 ti,set-bit-to-disable;
59 };
60
Tero Kristob5b53402016-04-04 18:16:06 +030061 uart4_fck: uart4_fck@1000 {
Tero Kristo657fc112013-07-22 12:29:29 +030062 #clock-cells = <0>;
63 compatible = "ti,wait-gate-clock";
64 clocks = <&per_48m_fck>;
65 reg = <0x1000>;
66 ti,bit-shift = <18>;
67 };
68};
69
Tomi Valkeinen64a900f2014-02-13 10:58:32 +020070&dpll4_m2x2_mul_ck {
71 clock-mult = <1>;
72};
73
74&dpll4_m3x2_mul_ck {
75 clock-mult = <1>;
76};
77
78&dpll4_m4x2_mul_ck {
Tomi Valkeinenc368dbe2014-02-13 11:14:58 +020079 ti,clock-mult = <1>;
Tomi Valkeinen64a900f2014-02-13 10:58:32 +020080};
81
82&dpll4_m5x2_mul_ck {
Laurent Pincharte21a4ea2014-04-21 12:41:46 +020083 ti,clock-mult = <1>;
Tomi Valkeinen64a900f2014-02-13 10:58:32 +020084};
85
86&dpll4_m6x2_mul_ck {
87 clock-mult = <1>;
88};
89
Tero Kristo657fc112013-07-22 12:29:29 +030090&cm_clockdomains {
91 dpll4_clkdm: dpll4_clkdm {
92 compatible = "ti,clockdomain";
93 clocks = <&dpll4_ck>;
94 };
95
96 per_clkdm: per_clkdm {
97 compatible = "ti,clockdomain";
98 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
99 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
100 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
101 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
102 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
103 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
104 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
105 <&mcbsp4_ick>, <&uart4_fck>;
106 };
107};