Thomas Gleixner | fcaf203 | 2019-05-27 08:55:08 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2011 Freescale Semiconductor, Inc. |
| 4 | * Copyright 2011 Linaro Ltd. |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
Fabio Estevam | aee54d3 | 2018-05-09 23:08:07 -0300 | [diff] [blame] | 8 | #include <dt-bindings/input/input.h> |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 9 | #include "imx53.dtsi" |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 10 | |
| 11 | / { |
| 12 | model = "Freescale i.MX53 Automotive Reference Design Board"; |
| 13 | compatible = "fsl,imx53-ard", "fsl,imx53"; |
| 14 | |
Marco Franchi | ad00e08 | 2018-01-24 11:22:14 -0200 | [diff] [blame] | 15 | memory@70000000 { |
Fabio Estevam | e8fd17b | 2018-11-05 19:14:46 -0200 | [diff] [blame] | 16 | device_type = "memory"; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 17 | reg = <0x70000000 0x40000000>; |
| 18 | }; |
| 19 | |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 20 | eim-cs1@f4000000 { |
| 21 | #address-cells = <1>; |
| 22 | #size-cells = <1>; |
| 23 | compatible = "fsl,eim-bus", "simple-bus"; |
| 24 | reg = <0xf4000000 0x3ff0000>; |
| 25 | ranges; |
| 26 | |
Geert Uytterhoeven | 1c14769 | 2021-05-20 15:58:36 +0200 | [diff] [blame] | 27 | ethernet@f4000000 { |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 28 | compatible = "smsc,lan9220", "smsc,lan9115"; |
| 29 | reg = <0xf4000000 0x2000000>; |
| 30 | phy-mode = "mii"; |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 31 | interrupt-parent = <&gpio2>; |
Shawn Guo | 65dee07 | 2012-08-02 22:08:26 +0800 | [diff] [blame] | 32 | interrupts = <31 0x8>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 33 | reg-io-width = <4>; |
Shawn Guo | 1eec0c5 | 2012-08-02 22:48:39 +0800 | [diff] [blame] | 34 | /* |
| 35 | * VDD33A and VDDVARIO of LAN9220 are supplied by |
| 36 | * SW4_3V3 of LTC3589. Before the regulator driver |
| 37 | * for this PMIC is available, we use a fixed dummy |
| 38 | * 3V3 regulator to get LAN9220 driver probing work. |
| 39 | */ |
| 40 | vdd33a-supply = <®_3p3v>; |
| 41 | vddvario-supply = <®_3p3v>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 42 | smsc,irq-push-pull; |
| 43 | }; |
| 44 | }; |
| 45 | |
Shawn Guo | 1eec0c5 | 2012-08-02 22:48:39 +0800 | [diff] [blame] | 46 | regulators { |
| 47 | compatible = "simple-bus"; |
Shawn Guo | 352d318 | 2014-02-07 23:18:30 +0800 | [diff] [blame] | 48 | #address-cells = <1>; |
| 49 | #size-cells = <0>; |
Shawn Guo | 1eec0c5 | 2012-08-02 22:48:39 +0800 | [diff] [blame] | 50 | |
Shawn Guo | 352d318 | 2014-02-07 23:18:30 +0800 | [diff] [blame] | 51 | reg_3p3v: regulator@0 { |
Shawn Guo | 1eec0c5 | 2012-08-02 22:48:39 +0800 | [diff] [blame] | 52 | compatible = "regulator-fixed"; |
Shawn Guo | 352d318 | 2014-02-07 23:18:30 +0800 | [diff] [blame] | 53 | reg = <0>; |
Shawn Guo | 1eec0c5 | 2012-08-02 22:48:39 +0800 | [diff] [blame] | 54 | regulator-name = "3P3V"; |
| 55 | regulator-min-microvolt = <3300000>; |
| 56 | regulator-max-microvolt = <3300000>; |
| 57 | regulator-always-on; |
| 58 | }; |
| 59 | }; |
| 60 | |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 61 | gpio-keys { |
| 62 | compatible = "gpio-keys"; |
| 63 | |
| 64 | home { |
| 65 | label = "Home"; |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 66 | gpios = <&gpio5 10 0>; |
Fabio Estevam | aee54d3 | 2018-05-09 23:08:07 -0300 | [diff] [blame] | 67 | linux,code = <KEY_HOME>; |
Sudeep Holla | 26cefdd | 2015-10-21 11:10:08 +0100 | [diff] [blame] | 68 | wakeup-source; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 69 | }; |
| 70 | |
| 71 | back { |
| 72 | label = "Back"; |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 73 | gpios = <&gpio5 11 0>; |
Fabio Estevam | aee54d3 | 2018-05-09 23:08:07 -0300 | [diff] [blame] | 74 | linux,code = <KEY_BACK>; |
Sudeep Holla | 26cefdd | 2015-10-21 11:10:08 +0100 | [diff] [blame] | 75 | wakeup-source; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 76 | }; |
| 77 | |
| 78 | program { |
| 79 | label = "Program"; |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 80 | gpios = <&gpio5 12 0>; |
Fabio Estevam | aee54d3 | 2018-05-09 23:08:07 -0300 | [diff] [blame] | 81 | linux,code = <KEY_PROGRAM >; |
Sudeep Holla | 26cefdd | 2015-10-21 11:10:08 +0100 | [diff] [blame] | 82 | wakeup-source; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 83 | }; |
| 84 | |
| 85 | volume-up { |
| 86 | label = "Volume Up"; |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 87 | gpios = <&gpio5 13 0>; |
Fabio Estevam | aee54d3 | 2018-05-09 23:08:07 -0300 | [diff] [blame] | 88 | linux,code = <KEY_VOLUMEUP>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 89 | }; |
| 90 | |
| 91 | volume-down { |
| 92 | label = "Volume Down"; |
Richard Zhao | 4d19186 | 2011-12-14 09:26:44 +0800 | [diff] [blame] | 93 | gpios = <&gpio4 0 0>; |
Fabio Estevam | aee54d3 | 2018-05-09 23:08:07 -0300 | [diff] [blame] | 94 | linux,code = <KEY_VOLUMEDOWN>; |
Shawn Guo | 73d2b4c | 2011-10-17 08:42:16 +0800 | [diff] [blame] | 95 | }; |
| 96 | }; |
| 97 | }; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 98 | |
| 99 | &esdhc1 { |
| 100 | pinctrl-names = "default"; |
Shawn Guo | 7ac0f70 | 2013-11-04 14:45:46 +0800 | [diff] [blame] | 101 | pinctrl-0 = <&pinctrl_esdhc1>; |
Dong Aisheng | 94d7694 | 2015-07-22 20:53:01 +0800 | [diff] [blame] | 102 | cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; |
| 103 | wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 104 | status = "okay"; |
| 105 | }; |
| 106 | |
| 107 | &iomuxc { |
| 108 | pinctrl-names = "default"; |
| 109 | pinctrl-0 = <&pinctrl_hog>; |
| 110 | |
Shawn Guo | 7ac0f70 | 2013-11-04 14:45:46 +0800 | [diff] [blame] | 111 | imx53-ard { |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 112 | pinctrl_hog: hoggrp { |
| 113 | fsl,pins = < |
Shawn Guo | e164153 | 2013-02-20 10:32:52 +0800 | [diff] [blame] | 114 | MX53_PAD_GPIO_1__GPIO1_1 0x80000000 |
| 115 | MX53_PAD_GPIO_9__GPIO1_9 0x80000000 |
| 116 | MX53_PAD_EIM_EB3__GPIO2_31 0x80000000 |
| 117 | MX53_PAD_GPIO_10__GPIO4_0 0x80000000 |
| 118 | MX53_PAD_DISP0_DAT16__GPIO5_10 0x80000000 |
| 119 | MX53_PAD_DISP0_DAT17__GPIO5_11 0x80000000 |
| 120 | MX53_PAD_DISP0_DAT18__GPIO5_12 0x80000000 |
| 121 | MX53_PAD_DISP0_DAT19__GPIO5_13 0x80000000 |
| 122 | MX53_PAD_EIM_D16__EMI_WEIM_D_16 0x80000000 |
| 123 | MX53_PAD_EIM_D17__EMI_WEIM_D_17 0x80000000 |
| 124 | MX53_PAD_EIM_D18__EMI_WEIM_D_18 0x80000000 |
| 125 | MX53_PAD_EIM_D19__EMI_WEIM_D_19 0x80000000 |
| 126 | MX53_PAD_EIM_D20__EMI_WEIM_D_20 0x80000000 |
| 127 | MX53_PAD_EIM_D21__EMI_WEIM_D_21 0x80000000 |
| 128 | MX53_PAD_EIM_D22__EMI_WEIM_D_22 0x80000000 |
| 129 | MX53_PAD_EIM_D23__EMI_WEIM_D_23 0x80000000 |
| 130 | MX53_PAD_EIM_D24__EMI_WEIM_D_24 0x80000000 |
| 131 | MX53_PAD_EIM_D25__EMI_WEIM_D_25 0x80000000 |
| 132 | MX53_PAD_EIM_D26__EMI_WEIM_D_26 0x80000000 |
| 133 | MX53_PAD_EIM_D27__EMI_WEIM_D_27 0x80000000 |
| 134 | MX53_PAD_EIM_D28__EMI_WEIM_D_28 0x80000000 |
| 135 | MX53_PAD_EIM_D29__EMI_WEIM_D_29 0x80000000 |
| 136 | MX53_PAD_EIM_D30__EMI_WEIM_D_30 0x80000000 |
| 137 | MX53_PAD_EIM_D31__EMI_WEIM_D_31 0x80000000 |
| 138 | MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0x80000000 |
| 139 | MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0x80000000 |
| 140 | MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0x80000000 |
| 141 | MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0x80000000 |
| 142 | MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0x80000000 |
| 143 | MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0x80000000 |
| 144 | MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0x80000000 |
| 145 | MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000 |
| 146 | MX53_PAD_EIM_RW__EMI_WEIM_RW 0x80000000 |
| 147 | MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 0x80000000 |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 148 | >; |
| 149 | }; |
Shawn Guo | 7ac0f70 | 2013-11-04 14:45:46 +0800 | [diff] [blame] | 150 | |
| 151 | pinctrl_esdhc1: esdhc1grp { |
| 152 | fsl,pins = < |
| 153 | MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 |
| 154 | MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 |
| 155 | MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 |
| 156 | MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 |
| 157 | MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 |
| 158 | MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 |
| 159 | MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 |
| 160 | MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 |
| 161 | MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 |
| 162 | MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 |
| 163 | >; |
| 164 | }; |
| 165 | |
| 166 | pinctrl_uart1: uart1grp { |
| 167 | fsl,pins = < |
| 168 | MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 |
| 169 | MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 |
| 170 | >; |
| 171 | }; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 172 | }; |
| 173 | }; |
| 174 | |
| 175 | &uart1 { |
| 176 | pinctrl-names = "default"; |
Shawn Guo | 7ac0f70 | 2013-11-04 14:45:46 +0800 | [diff] [blame] | 177 | pinctrl-0 = <&pinctrl_uart1>; |
Shawn Guo | be4ccfc | 2012-12-31 11:32:48 +0800 | [diff] [blame] | 178 | status = "okay"; |
| 179 | }; |