blob: 73257cf107d973b034b2e3e36076d558f44efe10 [file] [log] [blame]
Thomas Gleixnerf6cc69f2019-05-29 16:57:24 -07001// SPDX-License-Identifier: GPL-2.0-only
Jacob Pan2d281d82013-10-17 10:28:35 -07002/*
Zhang Rui33823882019-07-10 21:44:30 +08003 * Common code for Intel Running Average Power Limit (RAPL) support.
4 * Copyright (c) 2019, Intel Corporation.
Jacob Pan2d281d82013-10-17 10:28:35 -07005 */
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/list.h>
11#include <linux/types.h>
12#include <linux/device.h>
13#include <linux/slab.h>
14#include <linux/log2.h>
15#include <linux/bitmap.h>
16#include <linux/delay.h>
17#include <linux/sysfs.h>
18#include <linux/cpu.h>
19#include <linux/powercap.h>
Zhen Han52b36722018-01-10 08:38:23 +080020#include <linux/suspend.h>
Zhang Ruiff956822019-07-10 21:44:24 +080021#include <linux/intel_rapl.h>
Zhang Rui33823882019-07-10 21:44:30 +080022#include <linux/processor.h>
Zhang Ruiabcfaeb2019-07-10 21:44:34 +080023#include <linux/platform_device.h>
24
25#include <asm/iosf_mbi.h>
Jacob Pan2d281d82013-10-17 10:28:35 -070026#include <asm/cpu_device_id.h>
Dave Hansen62d16732016-06-02 17:19:36 -070027#include <asm/intel-family.h>
Jacob Pan2d281d82013-10-17 10:28:35 -070028
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -070029/* Local defines */
30#define MSR_PLATFORM_POWER_LIMIT 0x0000065C
31
Jacob Pan2d281d82013-10-17 10:28:35 -070032/* bitmasks for RAPL MSRs, used by primitive access functions */
33#define ENERGY_STATUS_MASK 0xffffffff
34
35#define POWER_LIMIT1_MASK 0x7FFF
36#define POWER_LIMIT1_ENABLE BIT(15)
37#define POWER_LIMIT1_CLAMP BIT(16)
38
39#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
40#define POWER_LIMIT2_ENABLE BIT_ULL(47)
41#define POWER_LIMIT2_CLAMP BIT_ULL(48)
Zhang Rui0c2dded2019-07-10 21:44:32 +080042#define POWER_HIGH_LOCK BIT_ULL(63)
43#define POWER_LOW_LOCK BIT(31)
Jacob Pan2d281d82013-10-17 10:28:35 -070044
45#define TIME_WINDOW1_MASK (0x7FULL<<17)
46#define TIME_WINDOW2_MASK (0x7FULL<<49)
47
48#define POWER_UNIT_OFFSET 0
49#define POWER_UNIT_MASK 0x0F
50
51#define ENERGY_UNIT_OFFSET 0x08
52#define ENERGY_UNIT_MASK 0x1F00
53
54#define TIME_UNIT_OFFSET 0x10
55#define TIME_UNIT_MASK 0xF0000
56
57#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
58#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
59#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
60#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
61
62#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
63#define PP_POLICY_MASK 0x1F
64
65/* Non HW constants */
Zhang Rui33823882019-07-10 21:44:30 +080066#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
Jacob Pan2d281d82013-10-17 10:28:35 -070067#define RAPL_PRIMITIVE_DUMMY BIT(2)
68
Jacob Pan2d281d82013-10-17 10:28:35 -070069#define TIME_WINDOW_MAX_MSEC 40000
70#define TIME_WINDOW_MIN_MSEC 250
Zhang Rui33823882019-07-10 21:44:30 +080071#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
Jacob Pan2d281d82013-10-17 10:28:35 -070072enum unit_type {
Zhang Rui33823882019-07-10 21:44:30 +080073 ARBITRARY_UNIT, /* no translation */
Jacob Pan2d281d82013-10-17 10:28:35 -070074 POWER_UNIT,
75 ENERGY_UNIT,
76 TIME_UNIT,
77};
78
Jacob Pan2d281d82013-10-17 10:28:35 -070079/* per domain data, some are optional */
Jacob Pan2d281d82013-10-17 10:28:35 -070080#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
81
Jacob Pan2d281d82013-10-17 10:28:35 -070082#define DOMAIN_STATE_INACTIVE BIT(0)
83#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
84#define DOMAIN_STATE_BIOS_LOCKED BIT(2)
85
Jacob Pan2d281d82013-10-17 10:28:35 -070086static const char pl1_name[] = "long_term";
87static const char pl2_name[] = "short_term";
88
Jacob Pan2d281d82013-10-17 10:28:35 -070089#define power_zone_to_rapl_domain(_zone) \
90 container_of(_zone, struct rapl_domain, power_zone)
91
Jacob Pan087e9cb2014-11-07 09:29:25 -080092struct rapl_defaults {
Ajay Thomas51b63402015-04-30 01:43:23 +053093 u8 floor_freq_reg_addr;
Jacob Pan087e9cb2014-11-07 09:29:25 -080094 int (*check_unit)(struct rapl_package *rp, int cpu);
95 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
96 u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
Zhang Rui33823882019-07-10 21:44:30 +080097 bool to_raw);
Jacob Pand474a4d2015-03-13 03:48:56 -070098 unsigned int dram_domain_energy_unit;
Jacob Pan087e9cb2014-11-07 09:29:25 -080099};
100static struct rapl_defaults *rapl_defaults;
101
Jacob Pan3c2c0842014-11-07 09:29:26 -0800102/* Sideband MBI registers */
Ajay Thomas51b63402015-04-30 01:43:23 +0530103#define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
104#define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
Jacob Pan3c2c0842014-11-07 09:29:26 -0800105
Jacob Pan2d281d82013-10-17 10:28:35 -0700106#define PACKAGE_PLN_INT_SAVED BIT(0)
107#define MAX_PRIM_NAME (32)
108
109/* per domain data. used to describe individual knobs such that access function
110 * can be consolidated into one instead of many inline functions.
111 */
112struct rapl_primitive_info {
113 const char *name;
114 u64 mask;
115 int shift;
Zhang Ruif7c4e0c2019-07-10 21:44:22 +0800116 enum rapl_domain_reg_id id;
Jacob Pan2d281d82013-10-17 10:28:35 -0700117 enum unit_type unit;
118 u32 flag;
119};
120
121#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
122 .name = #p, \
123 .mask = m, \
124 .shift = s, \
125 .id = i, \
126 .unit = u, \
127 .flag = f \
128 }
129
130static void rapl_init_domains(struct rapl_package *rp);
131static int rapl_read_data_raw(struct rapl_domain *rd,
Zhang Rui33823882019-07-10 21:44:30 +0800132 enum rapl_primitives prim,
133 bool xlate, u64 *data);
Jacob Pan2d281d82013-10-17 10:28:35 -0700134static int rapl_write_data_raw(struct rapl_domain *rd,
Zhang Rui33823882019-07-10 21:44:30 +0800135 enum rapl_primitives prim,
136 unsigned long long value);
Jacob Pan309557f2016-02-24 13:31:37 -0800137static u64 rapl_unit_xlate(struct rapl_domain *rd,
Zhang Rui33823882019-07-10 21:44:30 +0800138 enum unit_type type, u64 value, int to_raw);
Jacob Pan309557f2016-02-24 13:31:37 -0800139static void package_power_limit_irq_save(struct rapl_package *rp);
Jacob Pan2d281d82013-10-17 10:28:35 -0700140
Zhang Rui33823882019-07-10 21:44:30 +0800141static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
Jacob Pan2d281d82013-10-17 10:28:35 -0700142
Zhang Rui33823882019-07-10 21:44:30 +0800143static const char *const rapl_domain_names[] = {
Jacob Pan2d281d82013-10-17 10:28:35 -0700144 "package",
145 "core",
146 "uncore",
147 "dram",
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -0700148 "psys",
Jacob Pan2d281d82013-10-17 10:28:35 -0700149};
150
Zhang Rui33823882019-07-10 21:44:30 +0800151static int get_energy_counter(struct powercap_zone *power_zone,
152 u64 *energy_raw)
Jacob Pan2d281d82013-10-17 10:28:35 -0700153{
154 struct rapl_domain *rd;
155 u64 energy_now;
156
157 /* prevent CPU hotplug, make sure the RAPL domain does not go
158 * away while reading the counter.
159 */
160 get_online_cpus();
161 rd = power_zone_to_rapl_domain(power_zone);
162
163 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
164 *energy_raw = energy_now;
165 put_online_cpus();
166
167 return 0;
168 }
169 put_online_cpus();
170
171 return -EIO;
172}
173
174static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
175{
Jacob Pand474a4d2015-03-13 03:48:56 -0700176 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
177
Jacob Pan309557f2016-02-24 13:31:37 -0800178 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
Jacob Pan2d281d82013-10-17 10:28:35 -0700179 return 0;
180}
181
182static int release_zone(struct powercap_zone *power_zone)
183{
184 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
Jacob Pan309557f2016-02-24 13:31:37 -0800185 struct rapl_package *rp = rd->rp;
Jacob Pan2d281d82013-10-17 10:28:35 -0700186
187 /* package zone is the last zone of a package, we can free
188 * memory here since all children has been unregistered.
189 */
190 if (rd->id == RAPL_DOMAIN_PACKAGE) {
Jacob Pan2d281d82013-10-17 10:28:35 -0700191 kfree(rd);
192 rp->domains = NULL;
193 }
194
195 return 0;
196
197}
198
199static int find_nr_power_limit(struct rapl_domain *rd)
200{
Jacob Pane1399ba2016-05-31 13:41:29 -0700201 int i, nr_pl = 0;
Jacob Pan2d281d82013-10-17 10:28:35 -0700202
203 for (i = 0; i < NR_POWER_LIMITS; i++) {
Jacob Pane1399ba2016-05-31 13:41:29 -0700204 if (rd->rpl[i].name)
205 nr_pl++;
Jacob Pan2d281d82013-10-17 10:28:35 -0700206 }
207
Jacob Pane1399ba2016-05-31 13:41:29 -0700208 return nr_pl;
Jacob Pan2d281d82013-10-17 10:28:35 -0700209}
210
211static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
212{
213 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
Jacob Pan2d281d82013-10-17 10:28:35 -0700214
215 if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
216 return -EACCES;
Jacob Pan3c2c0842014-11-07 09:29:26 -0800217
Jacob Pan2d281d82013-10-17 10:28:35 -0700218 get_online_cpus();
Jacob Pan2d281d82013-10-17 10:28:35 -0700219 rapl_write_data_raw(rd, PL1_ENABLE, mode);
Ajay Thomas51b63402015-04-30 01:43:23 +0530220 if (rapl_defaults->set_floor_freq)
221 rapl_defaults->set_floor_freq(rd, mode);
Jacob Pan2d281d82013-10-17 10:28:35 -0700222 put_online_cpus();
223
224 return 0;
225}
226
227static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
228{
229 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
230 u64 val;
231
232 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
233 *mode = false;
234 return 0;
235 }
236 get_online_cpus();
237 if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
238 put_online_cpus();
239 return -EIO;
240 }
241 *mode = val;
242 put_online_cpus();
243
244 return 0;
245}
246
247/* per RAPL domain ops, in the order of rapl_domain_type */
Julia Lawall600c3952015-12-23 22:59:55 +0100248static const struct powercap_zone_ops zone_ops[] = {
Jacob Pan2d281d82013-10-17 10:28:35 -0700249 /* RAPL_DOMAIN_PACKAGE */
250 {
Zhang Rui33823882019-07-10 21:44:30 +0800251 .get_energy_uj = get_energy_counter,
252 .get_max_energy_range_uj = get_max_energy_counter,
253 .release = release_zone,
254 .set_enable = set_domain_enable,
255 .get_enable = get_domain_enable,
256 },
Jacob Pan2d281d82013-10-17 10:28:35 -0700257 /* RAPL_DOMAIN_PP0 */
258 {
Zhang Rui33823882019-07-10 21:44:30 +0800259 .get_energy_uj = get_energy_counter,
260 .get_max_energy_range_uj = get_max_energy_counter,
261 .release = release_zone,
262 .set_enable = set_domain_enable,
263 .get_enable = get_domain_enable,
264 },
Jacob Pan2d281d82013-10-17 10:28:35 -0700265 /* RAPL_DOMAIN_PP1 */
266 {
Zhang Rui33823882019-07-10 21:44:30 +0800267 .get_energy_uj = get_energy_counter,
268 .get_max_energy_range_uj = get_max_energy_counter,
269 .release = release_zone,
270 .set_enable = set_domain_enable,
271 .get_enable = get_domain_enable,
272 },
Jacob Pan2d281d82013-10-17 10:28:35 -0700273 /* RAPL_DOMAIN_DRAM */
274 {
Zhang Rui33823882019-07-10 21:44:30 +0800275 .get_energy_uj = get_energy_counter,
276 .get_max_energy_range_uj = get_max_energy_counter,
277 .release = release_zone,
278 .set_enable = set_domain_enable,
279 .get_enable = get_domain_enable,
280 },
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -0700281 /* RAPL_DOMAIN_PLATFORM */
282 {
Zhang Rui33823882019-07-10 21:44:30 +0800283 .get_energy_uj = get_energy_counter,
284 .get_max_energy_range_uj = get_max_energy_counter,
285 .release = release_zone,
286 .set_enable = set_domain_enable,
287 .get_enable = get_domain_enable,
288 },
Jacob Pan2d281d82013-10-17 10:28:35 -0700289};
290
Jacob Pane1399ba2016-05-31 13:41:29 -0700291/*
292 * Constraint index used by powercap can be different than power limit (PL)
Zhang Rui33823882019-07-10 21:44:30 +0800293 * index in that some PLs maybe missing due to non-existent MSRs. So we
Jacob Pane1399ba2016-05-31 13:41:29 -0700294 * need to convert here by finding the valid PLs only (name populated).
295 */
296static int contraint_to_pl(struct rapl_domain *rd, int cid)
297{
298 int i, j;
299
300 for (i = 0, j = 0; i < NR_POWER_LIMITS; i++) {
301 if ((rd->rpl[i].name) && j++ == cid) {
302 pr_debug("%s: index %d\n", __func__, i);
303 return i;
304 }
305 }
Jacob Pancb43f812016-11-28 13:53:11 -0800306 pr_err("Cannot find matching power limit for constraint %d\n", cid);
Jacob Pane1399ba2016-05-31 13:41:29 -0700307
308 return -EINVAL;
309}
310
311static int set_power_limit(struct powercap_zone *power_zone, int cid,
Zhang Rui33823882019-07-10 21:44:30 +0800312 u64 power_limit)
Jacob Pan2d281d82013-10-17 10:28:35 -0700313{
314 struct rapl_domain *rd;
315 struct rapl_package *rp;
316 int ret = 0;
Jacob Pane1399ba2016-05-31 13:41:29 -0700317 int id;
Jacob Pan2d281d82013-10-17 10:28:35 -0700318
319 get_online_cpus();
320 rd = power_zone_to_rapl_domain(power_zone);
Jacob Pane1399ba2016-05-31 13:41:29 -0700321 id = contraint_to_pl(rd, cid);
Jacob Pancb43f812016-11-28 13:53:11 -0800322 if (id < 0) {
323 ret = id;
324 goto set_exit;
325 }
Jacob Pane1399ba2016-05-31 13:41:29 -0700326
Jacob Pan309557f2016-02-24 13:31:37 -0800327 rp = rd->rp;
Jacob Pan2d281d82013-10-17 10:28:35 -0700328
329 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
Zhang Rui33823882019-07-10 21:44:30 +0800330 dev_warn(&power_zone->dev,
331 "%s locked by BIOS, monitoring only\n", rd->name);
Jacob Pan2d281d82013-10-17 10:28:35 -0700332 ret = -EACCES;
333 goto set_exit;
334 }
335
336 switch (rd->rpl[id].prim_id) {
337 case PL1_ENABLE:
338 rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
339 break;
340 case PL2_ENABLE:
341 rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
342 break;
343 default:
344 ret = -EINVAL;
345 }
346 if (!ret)
Jacob Pan309557f2016-02-24 13:31:37 -0800347 package_power_limit_irq_save(rp);
Jacob Pan2d281d82013-10-17 10:28:35 -0700348set_exit:
349 put_online_cpus();
350 return ret;
351}
352
Jacob Pane1399ba2016-05-31 13:41:29 -0700353static int get_current_power_limit(struct powercap_zone *power_zone, int cid,
Zhang Rui33823882019-07-10 21:44:30 +0800354 u64 *data)
Jacob Pan2d281d82013-10-17 10:28:35 -0700355{
356 struct rapl_domain *rd;
357 u64 val;
358 int prim;
359 int ret = 0;
Jacob Pane1399ba2016-05-31 13:41:29 -0700360 int id;
Jacob Pan2d281d82013-10-17 10:28:35 -0700361
362 get_online_cpus();
363 rd = power_zone_to_rapl_domain(power_zone);
Jacob Pane1399ba2016-05-31 13:41:29 -0700364 id = contraint_to_pl(rd, cid);
Jacob Pancb43f812016-11-28 13:53:11 -0800365 if (id < 0) {
366 ret = id;
367 goto get_exit;
368 }
369
Jacob Pan2d281d82013-10-17 10:28:35 -0700370 switch (rd->rpl[id].prim_id) {
371 case PL1_ENABLE:
372 prim = POWER_LIMIT1;
373 break;
374 case PL2_ENABLE:
375 prim = POWER_LIMIT2;
376 break;
377 default:
378 put_online_cpus();
379 return -EINVAL;
380 }
381 if (rapl_read_data_raw(rd, prim, true, &val))
382 ret = -EIO;
383 else
384 *data = val;
385
Jacob Pancb43f812016-11-28 13:53:11 -0800386get_exit:
Jacob Pan2d281d82013-10-17 10:28:35 -0700387 put_online_cpus();
388
389 return ret;
390}
391
Jacob Pane1399ba2016-05-31 13:41:29 -0700392static int set_time_window(struct powercap_zone *power_zone, int cid,
Zhang Rui33823882019-07-10 21:44:30 +0800393 u64 window)
Jacob Pan2d281d82013-10-17 10:28:35 -0700394{
395 struct rapl_domain *rd;
396 int ret = 0;
Jacob Pane1399ba2016-05-31 13:41:29 -0700397 int id;
Jacob Pan2d281d82013-10-17 10:28:35 -0700398
399 get_online_cpus();
400 rd = power_zone_to_rapl_domain(power_zone);
Jacob Pane1399ba2016-05-31 13:41:29 -0700401 id = contraint_to_pl(rd, cid);
Jacob Pancb43f812016-11-28 13:53:11 -0800402 if (id < 0) {
403 ret = id;
404 goto set_time_exit;
405 }
Jacob Pane1399ba2016-05-31 13:41:29 -0700406
Jacob Pan2d281d82013-10-17 10:28:35 -0700407 switch (rd->rpl[id].prim_id) {
408 case PL1_ENABLE:
409 rapl_write_data_raw(rd, TIME_WINDOW1, window);
410 break;
411 case PL2_ENABLE:
412 rapl_write_data_raw(rd, TIME_WINDOW2, window);
413 break;
414 default:
415 ret = -EINVAL;
416 }
Jacob Pancb43f812016-11-28 13:53:11 -0800417
418set_time_exit:
Jacob Pan2d281d82013-10-17 10:28:35 -0700419 put_online_cpus();
420 return ret;
421}
422
Zhang Rui33823882019-07-10 21:44:30 +0800423static int get_time_window(struct powercap_zone *power_zone, int cid,
424 u64 *data)
Jacob Pan2d281d82013-10-17 10:28:35 -0700425{
426 struct rapl_domain *rd;
427 u64 val;
428 int ret = 0;
Jacob Pane1399ba2016-05-31 13:41:29 -0700429 int id;
Jacob Pan2d281d82013-10-17 10:28:35 -0700430
431 get_online_cpus();
432 rd = power_zone_to_rapl_domain(power_zone);
Jacob Pane1399ba2016-05-31 13:41:29 -0700433 id = contraint_to_pl(rd, cid);
Jacob Pancb43f812016-11-28 13:53:11 -0800434 if (id < 0) {
435 ret = id;
436 goto get_time_exit;
437 }
Jacob Pane1399ba2016-05-31 13:41:29 -0700438
Jacob Pan2d281d82013-10-17 10:28:35 -0700439 switch (rd->rpl[id].prim_id) {
440 case PL1_ENABLE:
441 ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
442 break;
443 case PL2_ENABLE:
444 ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
445 break;
446 default:
447 put_online_cpus();
448 return -EINVAL;
449 }
450 if (!ret)
451 *data = val;
Jacob Pancb43f812016-11-28 13:53:11 -0800452
453get_time_exit:
Jacob Pan2d281d82013-10-17 10:28:35 -0700454 put_online_cpus();
455
456 return ret;
457}
458
Zhang Rui33823882019-07-10 21:44:30 +0800459static const char *get_constraint_name(struct powercap_zone *power_zone,
460 int cid)
Jacob Pan2d281d82013-10-17 10:28:35 -0700461{
Jacob Pan2d281d82013-10-17 10:28:35 -0700462 struct rapl_domain *rd;
Jacob Pane1399ba2016-05-31 13:41:29 -0700463 int id;
Jacob Pan2d281d82013-10-17 10:28:35 -0700464
465 rd = power_zone_to_rapl_domain(power_zone);
Jacob Pane1399ba2016-05-31 13:41:29 -0700466 id = contraint_to_pl(rd, cid);
467 if (id >= 0)
468 return rd->rpl[id].name;
Jacob Pan2d281d82013-10-17 10:28:35 -0700469
Jacob Pane1399ba2016-05-31 13:41:29 -0700470 return NULL;
Jacob Pan2d281d82013-10-17 10:28:35 -0700471}
472
Zhang Rui33823882019-07-10 21:44:30 +0800473static int get_max_power(struct powercap_zone *power_zone, int id, u64 *data)
Jacob Pan2d281d82013-10-17 10:28:35 -0700474{
475 struct rapl_domain *rd;
476 u64 val;
477 int prim;
478 int ret = 0;
479
480 get_online_cpus();
481 rd = power_zone_to_rapl_domain(power_zone);
482 switch (rd->rpl[id].prim_id) {
483 case PL1_ENABLE:
484 prim = THERMAL_SPEC_POWER;
485 break;
486 case PL2_ENABLE:
487 prim = MAX_POWER;
488 break;
489 default:
490 put_online_cpus();
491 return -EINVAL;
492 }
493 if (rapl_read_data_raw(rd, prim, true, &val))
494 ret = -EIO;
495 else
496 *data = val;
497
498 put_online_cpus();
499
500 return ret;
501}
502
Julia Lawall600c3952015-12-23 22:59:55 +0100503static const struct powercap_zone_constraint_ops constraint_ops = {
Jacob Pan2d281d82013-10-17 10:28:35 -0700504 .set_power_limit_uw = set_power_limit,
505 .get_power_limit_uw = get_current_power_limit,
506 .set_time_window_us = set_time_window,
507 .get_time_window_us = get_time_window,
508 .get_max_power_uw = get_max_power,
509 .get_name = get_constraint_name,
510};
511
512/* called after domain detection and package level data are set */
513static void rapl_init_domains(struct rapl_package *rp)
514{
Zhang Rui0c2dded2019-07-10 21:44:32 +0800515 enum rapl_domain_type i;
516 enum rapl_domain_reg_id j;
Jacob Pan2d281d82013-10-17 10:28:35 -0700517 struct rapl_domain *rd = rp->domains;
518
519 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
520 unsigned int mask = rp->domain_map & (1 << i);
Zhang Rui7fde2712019-07-10 21:44:26 +0800521
Zhang Rui0c2dded2019-07-10 21:44:32 +0800522 if (!mask)
523 continue;
Zhang Rui7fde2712019-07-10 21:44:26 +0800524
Zhang Rui0c2dded2019-07-10 21:44:32 +0800525 rd->rp = rp;
526 rd->name = rapl_domain_names[i];
527 rd->id = i;
528 rd->rpl[0].prim_id = PL1_ENABLE;
529 rd->rpl[0].name = pl1_name;
530 /* some domain may support two power limits */
531 if (rp->priv->limits[i] == 2) {
Jacob Pan2d281d82013-10-17 10:28:35 -0700532 rd->rpl[1].prim_id = PL2_ENABLE;
533 rd->rpl[1].name = pl2_name;
Zhang Rui0c2dded2019-07-10 21:44:32 +0800534 }
535
536 for (j = 0; j < RAPL_DOMAIN_REG_MAX; j++)
537 rd->regs[j] = rp->priv->regs[i][j];
538
539 if (i == RAPL_DOMAIN_DRAM) {
Jacob Pand474a4d2015-03-13 03:48:56 -0700540 rd->domain_energy_unit =
Zhang Rui33823882019-07-10 21:44:30 +0800541 rapl_defaults->dram_domain_energy_unit;
Jacob Pand474a4d2015-03-13 03:48:56 -0700542 if (rd->domain_energy_unit)
543 pr_info("DRAM domain energy unit %dpj\n",
544 rd->domain_energy_unit);
Jacob Pan2d281d82013-10-17 10:28:35 -0700545 }
Zhang Rui0c2dded2019-07-10 21:44:32 +0800546 rd++;
Jacob Pan2d281d82013-10-17 10:28:35 -0700547 }
548}
549
Jacob Pan309557f2016-02-24 13:31:37 -0800550static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
Zhang Rui33823882019-07-10 21:44:30 +0800551 u64 value, int to_raw)
Jacob Pan2d281d82013-10-17 10:28:35 -0700552{
Jacob Pan3c2c0842014-11-07 09:29:26 -0800553 u64 units = 1;
Jacob Pan309557f2016-02-24 13:31:37 -0800554 struct rapl_package *rp = rd->rp;
Jacob Pand474a4d2015-03-13 03:48:56 -0700555 u64 scale = 1;
Jacob Pan2d281d82013-10-17 10:28:35 -0700556
Jacob Pan2d281d82013-10-17 10:28:35 -0700557 switch (type) {
558 case POWER_UNIT:
Jacob Pan3c2c0842014-11-07 09:29:26 -0800559 units = rp->power_unit;
Jacob Pan2d281d82013-10-17 10:28:35 -0700560 break;
561 case ENERGY_UNIT:
Jacob Pand474a4d2015-03-13 03:48:56 -0700562 scale = ENERGY_UNIT_SCALE;
563 /* per domain unit takes precedence */
Jacob Pancb43f812016-11-28 13:53:11 -0800564 if (rd->domain_energy_unit)
Jacob Pand474a4d2015-03-13 03:48:56 -0700565 units = rd->domain_energy_unit;
566 else
567 units = rp->energy_unit;
Jacob Pan2d281d82013-10-17 10:28:35 -0700568 break;
569 case TIME_UNIT:
Jacob Pan3c2c0842014-11-07 09:29:26 -0800570 return rapl_defaults->compute_time_window(rp, value, to_raw);
Jacob Pan2d281d82013-10-17 10:28:35 -0700571 case ARBITRARY_UNIT:
572 default:
573 return value;
574 };
575
576 if (to_raw)
Jacob Pand474a4d2015-03-13 03:48:56 -0700577 return div64_u64(value, units) * scale;
Jacob Pan3c2c0842014-11-07 09:29:26 -0800578
579 value *= units;
580
Jacob Pand474a4d2015-03-13 03:48:56 -0700581 return div64_u64(value, scale);
Jacob Pan2d281d82013-10-17 10:28:35 -0700582}
583
584/* in the order of enum rapl_primitives */
585static struct rapl_primitive_info rpi[] = {
586 /* name, mask, shift, msr index, unit divisor */
587 PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
Zhang Rui33823882019-07-10 21:44:30 +0800588 RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700589 PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
Zhang Rui33823882019-07-10 21:44:30 +0800590 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700591 PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
Zhang Rui33823882019-07-10 21:44:30 +0800592 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
Zhang Rui0c2dded2019-07-10 21:44:32 +0800593 PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
Zhang Rui33823882019-07-10 21:44:30 +0800594 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700595 PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
Zhang Rui33823882019-07-10 21:44:30 +0800596 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700597 PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
Zhang Rui33823882019-07-10 21:44:30 +0800598 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700599 PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
Zhang Rui33823882019-07-10 21:44:30 +0800600 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700601 PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
Zhang Rui33823882019-07-10 21:44:30 +0800602 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700603 PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
Zhang Rui33823882019-07-10 21:44:30 +0800604 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700605 PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
Zhang Rui33823882019-07-10 21:44:30 +0800606 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700607 PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
Zhang Rui33823882019-07-10 21:44:30 +0800608 0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700609 PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
Zhang Rui33823882019-07-10 21:44:30 +0800610 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700611 PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
Zhang Rui33823882019-07-10 21:44:30 +0800612 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700613 PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
Zhang Rui33823882019-07-10 21:44:30 +0800614 RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700615 PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
Zhang Rui33823882019-07-10 21:44:30 +0800616 RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700617 PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
Zhang Rui33823882019-07-10 21:44:30 +0800618 RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
Jacob Pan2d281d82013-10-17 10:28:35 -0700619 /* non-hardware */
620 PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
Zhang Rui33823882019-07-10 21:44:30 +0800621 RAPL_PRIMITIVE_DERIVED),
Jacob Pan2d281d82013-10-17 10:28:35 -0700622 {NULL, 0, 0, 0},
623};
624
625/* Read primitive data based on its related struct rapl_primitive_info.
626 * if xlate flag is set, return translated data based on data units, i.e.
627 * time, energy, and power.
628 * RAPL MSRs are non-architectual and are laid out not consistently across
629 * domains. Here we use primitive info to allow writing consolidated access
630 * functions.
631 * For a given primitive, it is processed by MSR mask and shift. Unit conversion
632 * is pre-assigned based on RAPL unit MSRs read at init time.
633 * 63-------------------------- 31--------------------------- 0
634 * | xxxxx (mask) |
635 * | |<- shift ----------------|
636 * 63-------------------------- 31--------------------------- 0
637 */
638static int rapl_read_data_raw(struct rapl_domain *rd,
Zhang Rui33823882019-07-10 21:44:30 +0800639 enum rapl_primitives prim, bool xlate, u64 *data)
Jacob Pan2d281d82013-10-17 10:28:35 -0700640{
Zhang Ruibeea8df2019-07-10 21:44:27 +0800641 u64 value;
Jacob Pan2d281d82013-10-17 10:28:35 -0700642 struct rapl_primitive_info *rp = &rpi[prim];
Zhang Ruibeea8df2019-07-10 21:44:27 +0800643 struct reg_action ra;
Jacob Pan2d281d82013-10-17 10:28:35 -0700644 int cpu;
645
646 if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
647 return -EINVAL;
648
Zhang Ruibeea8df2019-07-10 21:44:27 +0800649 ra.reg = rd->regs[rp->id];
650 if (!ra.reg)
Jacob Pan2d281d82013-10-17 10:28:35 -0700651 return -EINVAL;
Jacob Pan323ee642016-02-24 13:31:38 -0800652
653 cpu = rd->rp->lead_cpu;
Jacob Pan2d281d82013-10-17 10:28:35 -0700654
Zhang Rui0c2dded2019-07-10 21:44:32 +0800655 /* domain with 2 limits has different bit */
656 if (prim == FW_LOCK && rd->rp->priv->limits[rd->id] == 2) {
657 rp->mask = POWER_HIGH_LOCK;
Jacob Pan2d281d82013-10-17 10:28:35 -0700658 rp->shift = 63;
659 }
660 /* non-hardware data are collected by the polling thread */
661 if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
662 *data = rd->rdd.primitives[prim];
663 return 0;
664 }
665
Zhang Ruibeea8df2019-07-10 21:44:27 +0800666 ra.mask = rp->mask;
667
668 if (rd->rp->priv->read_raw(cpu, &ra)) {
Zhang Ruid978e752019-07-10 21:44:31 +0800669 pr_debug("failed to read reg 0x%llx on cpu %d\n", ra.reg, cpu);
Jacob Pan2d281d82013-10-17 10:28:35 -0700670 return -EIO;
671 }
672
Zhang Ruibeea8df2019-07-10 21:44:27 +0800673 value = ra.value >> rp->shift;
674
Jacob Pan2d281d82013-10-17 10:28:35 -0700675 if (xlate)
Zhang Ruibeea8df2019-07-10 21:44:27 +0800676 *data = rapl_unit_xlate(rd, rp->unit, value, 0);
Jacob Pan2d281d82013-10-17 10:28:35 -0700677 else
Zhang Ruibeea8df2019-07-10 21:44:27 +0800678 *data = value;
Jacob Pan2d281d82013-10-17 10:28:35 -0700679
680 return 0;
681}
682
683/* Similar use of primitive info in the read counterpart */
684static int rapl_write_data_raw(struct rapl_domain *rd,
Zhang Rui33823882019-07-10 21:44:30 +0800685 enum rapl_primitives prim,
686 unsigned long long value)
Jacob Pan2d281d82013-10-17 10:28:35 -0700687{
Jacob Pan2d281d82013-10-17 10:28:35 -0700688 struct rapl_primitive_info *rp = &rpi[prim];
689 int cpu;
Jacob Panf14a1392016-02-24 13:31:36 -0800690 u64 bits;
Zhang Ruibeea8df2019-07-10 21:44:27 +0800691 struct reg_action ra;
Jacob Panf14a1392016-02-24 13:31:36 -0800692 int ret;
Jacob Pan2d281d82013-10-17 10:28:35 -0700693
Jacob Pan323ee642016-02-24 13:31:38 -0800694 cpu = rd->rp->lead_cpu;
Jacob Pan309557f2016-02-24 13:31:37 -0800695 bits = rapl_unit_xlate(rd, rp->unit, value, 1);
Adam Lessnauedbdabc2017-06-01 11:21:50 +0200696 bits <<= rp->shift;
697 bits &= rp->mask;
698
Zhang Ruibeea8df2019-07-10 21:44:27 +0800699 memset(&ra, 0, sizeof(ra));
Jacob Panf14a1392016-02-24 13:31:36 -0800700
Zhang Ruibeea8df2019-07-10 21:44:27 +0800701 ra.reg = rd->regs[rp->id];
702 ra.mask = rp->mask;
703 ra.value = bits;
Jacob Panf14a1392016-02-24 13:31:36 -0800704
Zhang Ruibeea8df2019-07-10 21:44:27 +0800705 ret = rd->rp->priv->write_raw(cpu, &ra);
Jacob Panf14a1392016-02-24 13:31:36 -0800706
707 return ret;
Jacob Pan2d281d82013-10-17 10:28:35 -0700708}
709
Jacob Pan3c2c0842014-11-07 09:29:26 -0800710/*
711 * Raw RAPL data stored in MSRs are in certain scales. We need to
712 * convert them into standard units based on the units reported in
713 * the RAPL unit MSRs. This is specific to CPUs as the method to
714 * calculate units differ on different CPUs.
715 * We convert the units to below format based on CPUs.
716 * i.e.
Jacob Pand474a4d2015-03-13 03:48:56 -0700717 * energy unit: picoJoules : Represented in picoJoules by default
Jacob Pan3c2c0842014-11-07 09:29:26 -0800718 * power unit : microWatts : Represented in milliWatts by default
719 * time unit : microseconds: Represented in seconds by default
720 */
721static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
Jacob Pan2d281d82013-10-17 10:28:35 -0700722{
Zhang Rui1193b162019-07-10 21:44:29 +0800723 struct reg_action ra;
Jacob Pan2d281d82013-10-17 10:28:35 -0700724 u32 value;
725
Zhang Rui1193b162019-07-10 21:44:29 +0800726 ra.reg = rp->priv->reg_unit;
727 ra.mask = ~0;
728 if (rp->priv->read_raw(cpu, &ra)) {
Zhang Ruid978e752019-07-10 21:44:31 +0800729 pr_err("Failed to read power unit REG 0x%llx on CPU %d, exit.\n",
Zhang Rui33823882019-07-10 21:44:30 +0800730 rp->priv->reg_unit, cpu);
Jacob Pan2d281d82013-10-17 10:28:35 -0700731 return -ENODEV;
732 }
733
Zhang Rui1193b162019-07-10 21:44:29 +0800734 value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
Jacob Pand474a4d2015-03-13 03:48:56 -0700735 rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
Jacob Pan2d281d82013-10-17 10:28:35 -0700736
Zhang Rui1193b162019-07-10 21:44:29 +0800737 value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
Jacob Pan3c2c0842014-11-07 09:29:26 -0800738 rp->power_unit = 1000000 / (1 << value);
Jacob Pan2d281d82013-10-17 10:28:35 -0700739
Zhang Rui1193b162019-07-10 21:44:29 +0800740 value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
Jacob Pan3c2c0842014-11-07 09:29:26 -0800741 rp->time_unit = 1000000 / (1 << value);
Jacob Pan2d281d82013-10-17 10:28:35 -0700742
Zhang Rui9ea76122019-05-13 13:58:53 -0400743 pr_debug("Core CPU %s energy=%dpJ, time=%dus, power=%duW\n",
Zhang Rui33823882019-07-10 21:44:30 +0800744 rp->name, rp->energy_unit, rp->time_unit, rp->power_unit);
Jacob Pan2d281d82013-10-17 10:28:35 -0700745
746 return 0;
747}
748
Jacob Pan3c2c0842014-11-07 09:29:26 -0800749static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
750{
Zhang Rui1193b162019-07-10 21:44:29 +0800751 struct reg_action ra;
Jacob Pan3c2c0842014-11-07 09:29:26 -0800752 u32 value;
753
Zhang Rui1193b162019-07-10 21:44:29 +0800754 ra.reg = rp->priv->reg_unit;
755 ra.mask = ~0;
756 if (rp->priv->read_raw(cpu, &ra)) {
Zhang Ruid978e752019-07-10 21:44:31 +0800757 pr_err("Failed to read power unit REG 0x%llx on CPU %d, exit.\n",
Zhang Rui33823882019-07-10 21:44:30 +0800758 rp->priv->reg_unit, cpu);
Jacob Pan3c2c0842014-11-07 09:29:26 -0800759 return -ENODEV;
760 }
Zhang Rui1193b162019-07-10 21:44:29 +0800761
762 value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
Jacob Pand474a4d2015-03-13 03:48:56 -0700763 rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
Jacob Pan3c2c0842014-11-07 09:29:26 -0800764
Zhang Rui1193b162019-07-10 21:44:29 +0800765 value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
Jacob Pan3c2c0842014-11-07 09:29:26 -0800766 rp->power_unit = (1 << value) * 1000;
767
Zhang Rui1193b162019-07-10 21:44:29 +0800768 value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
Jacob Pan3c2c0842014-11-07 09:29:26 -0800769 rp->time_unit = 1000000 / (1 << value);
770
Zhang Rui9ea76122019-05-13 13:58:53 -0400771 pr_debug("Atom %s energy=%dpJ, time=%dus, power=%duW\n",
Zhang Rui33823882019-07-10 21:44:30 +0800772 rp->name, rp->energy_unit, rp->time_unit, rp->power_unit);
Jacob Pan3c2c0842014-11-07 09:29:26 -0800773
774 return 0;
775}
776
Jacob Panf14a1392016-02-24 13:31:36 -0800777static void power_limit_irq_save_cpu(void *info)
778{
779 u32 l, h = 0;
780 struct rapl_package *rp = (struct rapl_package *)info;
781
782 /* save the state of PLN irq mask bit before disabling it */
783 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
784 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
785 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
786 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
787 }
788 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
789 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
790}
791
Jacob Pan2d281d82013-10-17 10:28:35 -0700792/* REVISIT:
793 * When package power limit is set artificially low by RAPL, LVT
794 * thermal interrupt for package power limit should be ignored
795 * since we are not really exceeding the real limit. The intention
796 * is to avoid excessive interrupts while we are trying to save power.
797 * A useful feature might be routing the package_power_limit interrupt
798 * to userspace via eventfd. once we have a usecase, this is simple
799 * to do by adding an atomic notifier.
800 */
801
Jacob Pan309557f2016-02-24 13:31:37 -0800802static void package_power_limit_irq_save(struct rapl_package *rp)
Jacob Pan2d281d82013-10-17 10:28:35 -0700803{
Jacob Pan2d281d82013-10-17 10:28:35 -0700804 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
805 return;
806
Jacob Pan323ee642016-02-24 13:31:38 -0800807 smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1);
Jacob Panf14a1392016-02-24 13:31:36 -0800808}
809
Thomas Gleixner58705062016-11-22 21:16:02 +0000810/*
811 * Restore per package power limit interrupt enable state. Called from cpu
812 * hotplug code on package removal.
813 */
814static void package_power_limit_irq_restore(struct rapl_package *rp)
Jacob Panf14a1392016-02-24 13:31:36 -0800815{
Thomas Gleixner58705062016-11-22 21:16:02 +0000816 u32 l, h;
817
818 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
819 return;
820
821 /* irq enable state not saved, nothing to restore */
822 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
823 return;
Jacob Panf14a1392016-02-24 13:31:36 -0800824
825 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
826
827 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
828 l |= PACKAGE_THERM_INT_PLN_ENABLE;
829 else
830 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
831
832 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
Jacob Pan2d281d82013-10-17 10:28:35 -0700833}
834
Jacob Pan3c2c0842014-11-07 09:29:26 -0800835static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
836{
837 int nr_powerlimit = find_nr_power_limit(rd);
838
839 /* always enable clamp such that p-state can go below OS requested
840 * range. power capping priority over guranteed frequency.
841 */
842 rapl_write_data_raw(rd, PL1_CLAMP, mode);
843
844 /* some domains have pl2 */
845 if (nr_powerlimit > 1) {
846 rapl_write_data_raw(rd, PL2_ENABLE, mode);
847 rapl_write_data_raw(rd, PL2_CLAMP, mode);
848 }
849}
850
851static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
852{
853 static u32 power_ctrl_orig_val;
854 u32 mdata;
855
Ajay Thomas51b63402015-04-30 01:43:23 +0530856 if (!rapl_defaults->floor_freq_reg_addr) {
857 pr_err("Invalid floor frequency config register\n");
858 return;
859 }
860
Jacob Pan3c2c0842014-11-07 09:29:26 -0800861 if (!power_ctrl_orig_val)
Andy Shevchenko4077a382015-11-11 19:59:29 +0200862 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
863 rapl_defaults->floor_freq_reg_addr,
864 &power_ctrl_orig_val);
Jacob Pan3c2c0842014-11-07 09:29:26 -0800865 mdata = power_ctrl_orig_val;
866 if (enable) {
867 mdata &= ~(0x7f << 8);
868 mdata |= 1 << 8;
869 }
Andy Shevchenko4077a382015-11-11 19:59:29 +0200870 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
871 rapl_defaults->floor_freq_reg_addr, mdata);
Jacob Pan3c2c0842014-11-07 09:29:26 -0800872}
873
874static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
Zhang Rui33823882019-07-10 21:44:30 +0800875 bool to_raw)
Jacob Pan3c2c0842014-11-07 09:29:26 -0800876{
Zhang Rui33823882019-07-10 21:44:30 +0800877 u64 f, y; /* fraction and exp. used for time unit */
Jacob Pan3c2c0842014-11-07 09:29:26 -0800878
879 /*
880 * Special processing based on 2^Y*(1+F/4), refer
881 * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
882 */
883 if (!to_raw) {
884 f = (value & 0x60) >> 5;
885 y = value & 0x1f;
886 value = (1 << y) * (4 + f) * rp->time_unit / 4;
887 } else {
888 do_div(value, rp->time_unit);
889 y = ilog2(value);
890 f = div64_u64(4 * (value - (1 << y)), 1 << y);
891 value = (y & 0x1f) | ((f & 0x3) << 5);
892 }
893 return value;
894}
895
896static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
Zhang Rui33823882019-07-10 21:44:30 +0800897 bool to_raw)
Jacob Pan3c2c0842014-11-07 09:29:26 -0800898{
899 /*
900 * Atom time unit encoding is straight forward val * time_unit,
901 * where time_unit is default to 1 sec. Never 0.
902 */
903 if (!to_raw)
904 return (value) ? value *= rp->time_unit : rp->time_unit;
Zhang Rui33823882019-07-10 21:44:30 +0800905
906 value = div64_u64(value, rp->time_unit);
Jacob Pan3c2c0842014-11-07 09:29:26 -0800907
908 return value;
909}
910
Jacob Pan087e9cb2014-11-07 09:29:25 -0800911static const struct rapl_defaults rapl_defaults_core = {
Ajay Thomas51b63402015-04-30 01:43:23 +0530912 .floor_freq_reg_addr = 0,
Jacob Pan3c2c0842014-11-07 09:29:26 -0800913 .check_unit = rapl_check_unit_core,
914 .set_floor_freq = set_floor_freq_default,
915 .compute_time_window = rapl_compute_time_window_core,
Jacob Pan087e9cb2014-11-07 09:29:25 -0800916};
917
Jacob Pand474a4d2015-03-13 03:48:56 -0700918static const struct rapl_defaults rapl_defaults_hsw_server = {
919 .check_unit = rapl_check_unit_core,
920 .set_floor_freq = set_floor_freq_default,
921 .compute_time_window = rapl_compute_time_window_core,
922 .dram_domain_energy_unit = 15300,
923};
924
Ajay Thomas51b63402015-04-30 01:43:23 +0530925static const struct rapl_defaults rapl_defaults_byt = {
926 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
Jacob Pan3c2c0842014-11-07 09:29:26 -0800927 .check_unit = rapl_check_unit_atom,
928 .set_floor_freq = set_floor_freq_atom,
929 .compute_time_window = rapl_compute_time_window_atom,
Jacob Pan087e9cb2014-11-07 09:29:25 -0800930};
931
Ajay Thomas51b63402015-04-30 01:43:23 +0530932static const struct rapl_defaults rapl_defaults_tng = {
933 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
934 .check_unit = rapl_check_unit_atom,
935 .set_floor_freq = set_floor_freq_atom,
936 .compute_time_window = rapl_compute_time_window_atom,
937};
938
939static const struct rapl_defaults rapl_defaults_ann = {
940 .floor_freq_reg_addr = 0,
941 .check_unit = rapl_check_unit_atom,
942 .set_floor_freq = NULL,
943 .compute_time_window = rapl_compute_time_window_atom,
944};
945
946static const struct rapl_defaults rapl_defaults_cht = {
947 .floor_freq_reg_addr = 0,
948 .check_unit = rapl_check_unit_atom,
949 .set_floor_freq = NULL,
950 .compute_time_window = rapl_compute_time_window_atom,
951};
952
Mathias Krauseea85dbc2015-03-25 22:15:52 +0100953static const struct x86_cpu_id rapl_ids[] __initconst = {
Zhang Rui33823882019-07-10 21:44:30 +0800954 INTEL_CPU_FAM6(SANDYBRIDGE, rapl_defaults_core),
955 INTEL_CPU_FAM6(SANDYBRIDGE_X, rapl_defaults_core),
Dave Hansen0bb04b52016-06-02 17:19:37 -0700956
Zhang Rui33823882019-07-10 21:44:30 +0800957 INTEL_CPU_FAM6(IVYBRIDGE, rapl_defaults_core),
958 INTEL_CPU_FAM6(IVYBRIDGE_X, rapl_defaults_core),
Dave Hansen0bb04b52016-06-02 17:19:37 -0700959
Peter Zijlstrac66f78a2019-08-27 21:48:21 +0200960 INTEL_CPU_FAM6(HASWELL, rapl_defaults_core),
Peter Zijlstraaf239c42019-08-27 21:48:22 +0200961 INTEL_CPU_FAM6(HASWELL_L, rapl_defaults_core),
Peter Zijlstra5e741402019-08-27 21:48:23 +0200962 INTEL_CPU_FAM6(HASWELL_G, rapl_defaults_core),
Zhang Rui33823882019-07-10 21:44:30 +0800963 INTEL_CPU_FAM6(HASWELL_X, rapl_defaults_hsw_server),
Dave Hansen0bb04b52016-06-02 17:19:37 -0700964
Peter Zijlstrac66f78a2019-08-27 21:48:21 +0200965 INTEL_CPU_FAM6(BROADWELL, rapl_defaults_core),
Peter Zijlstra5e741402019-08-27 21:48:23 +0200966 INTEL_CPU_FAM6(BROADWELL_G, rapl_defaults_core),
Peter Zijlstra5ebb34e2019-08-27 21:48:24 +0200967 INTEL_CPU_FAM6(BROADWELL_D, rapl_defaults_core),
Zhang Rui33823882019-07-10 21:44:30 +0800968 INTEL_CPU_FAM6(BROADWELL_X, rapl_defaults_hsw_server),
Dave Hansen0bb04b52016-06-02 17:19:37 -0700969
Peter Zijlstrac66f78a2019-08-27 21:48:21 +0200970 INTEL_CPU_FAM6(SKYLAKE, rapl_defaults_core),
Peter Zijlstraaf239c42019-08-27 21:48:22 +0200971 INTEL_CPU_FAM6(SKYLAKE_L, rapl_defaults_core),
Zhang Rui33823882019-07-10 21:44:30 +0800972 INTEL_CPU_FAM6(SKYLAKE_X, rapl_defaults_hsw_server),
Peter Zijlstraaf239c42019-08-27 21:48:22 +0200973 INTEL_CPU_FAM6(KABYLAKE_L, rapl_defaults_core),
Peter Zijlstrac66f78a2019-08-27 21:48:21 +0200974 INTEL_CPU_FAM6(KABYLAKE, rapl_defaults_core),
Peter Zijlstraaf239c42019-08-27 21:48:22 +0200975 INTEL_CPU_FAM6(CANNONLAKE_L, rapl_defaults_core),
976 INTEL_CPU_FAM6(ICELAKE_L, rapl_defaults_core),
Peter Zijlstrac66f78a2019-08-27 21:48:21 +0200977 INTEL_CPU_FAM6(ICELAKE, rapl_defaults_core),
Rajneesh Bhardwaj2e3f4502019-07-10 21:44:38 +0800978 INTEL_CPU_FAM6(ICELAKE_NNPI, rapl_defaults_core),
Zhang Ruicceb1d92019-07-10 21:44:36 +0800979 INTEL_CPU_FAM6(ICELAKE_X, rapl_defaults_hsw_server),
Peter Zijlstra5ebb34e2019-08-27 21:48:24 +0200980 INTEL_CPU_FAM6(ICELAKE_D, rapl_defaults_hsw_server),
Zhang Ruicae47812019-10-31 21:18:11 +0800981 INTEL_CPU_FAM6(COMETLAKE_L, rapl_defaults_core),
Zhang Ruif84fdcb2019-10-31 21:18:12 +0800982 INTEL_CPU_FAM6(COMETLAKE, rapl_defaults_core),
Zhang Rui708d10e2019-12-17 09:56:23 +0800983 INTEL_CPU_FAM6(TIGERLAKE_L, rapl_defaults_core),
Dave Hansen0bb04b52016-06-02 17:19:37 -0700984
Zhang Rui33823882019-07-10 21:44:30 +0800985 INTEL_CPU_FAM6(ATOM_SILVERMONT, rapl_defaults_byt),
986 INTEL_CPU_FAM6(ATOM_AIRMONT, rapl_defaults_cht),
987 INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, rapl_defaults_tng),
988 INTEL_CPU_FAM6(ATOM_AIRMONT_MID, rapl_defaults_ann),
989 INTEL_CPU_FAM6(ATOM_GOLDMONT, rapl_defaults_core),
990 INTEL_CPU_FAM6(ATOM_GOLDMONT_PLUS, rapl_defaults_core),
Peter Zijlstra5ebb34e2019-08-27 21:48:24 +0200991 INTEL_CPU_FAM6(ATOM_GOLDMONT_D, rapl_defaults_core),
992 INTEL_CPU_FAM6(ATOM_TREMONT_D, rapl_defaults_core),
Zhang Rui2298cf82019-12-16 16:33:45 +0800993 INTEL_CPU_FAM6(ATOM_TREMONT_L, rapl_defaults_core),
Dave Hansen0bb04b52016-06-02 17:19:37 -0700994
Zhang Rui33823882019-07-10 21:44:30 +0800995 INTEL_CPU_FAM6(XEON_PHI_KNL, rapl_defaults_hsw_server),
996 INTEL_CPU_FAM6(XEON_PHI_KNM, rapl_defaults_hsw_server),
Jacob Pan2d281d82013-10-17 10:28:35 -0700997 {}
998};
Zhang Rui33823882019-07-10 21:44:30 +0800999
Jacob Pan2d281d82013-10-17 10:28:35 -07001000MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
1001
Thomas Gleixnerbed5ab62016-11-22 21:15:58 +00001002/* Read once for all raw primitive data for domains */
1003static void rapl_update_domain_data(struct rapl_package *rp)
Jacob Pan2d281d82013-10-17 10:28:35 -07001004{
1005 int dmn, prim;
1006 u64 val;
Jacob Pan2d281d82013-10-17 10:28:35 -07001007
Thomas Gleixnerbed5ab62016-11-22 21:15:58 +00001008 for (dmn = 0; dmn < rp->nr_domains; dmn++) {
Zhang Rui9ea76122019-05-13 13:58:53 -04001009 pr_debug("update %s domain %s data\n", rp->name,
Thomas Gleixnerbed5ab62016-11-22 21:15:58 +00001010 rp->domains[dmn].name);
1011 /* exclude non-raw primitives */
1012 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) {
1013 if (!rapl_read_data_raw(&rp->domains[dmn], prim,
1014 rpi[prim].unit, &val))
Zhang Rui33823882019-07-10 21:44:30 +08001015 rp->domains[dmn].rdd.primitives[prim] = val;
Jacob Pan2d281d82013-10-17 10:28:35 -07001016 }
1017 }
1018
1019}
1020
Jacob Pan2d281d82013-10-17 10:28:35 -07001021static int rapl_package_register_powercap(struct rapl_package *rp)
1022{
1023 struct rapl_domain *rd;
Jacob Pan2d281d82013-10-17 10:28:35 -07001024 struct powercap_zone *power_zone = NULL;
Luis de Bethencourt01857cf2018-01-17 10:30:34 +00001025 int nr_pl, ret;
Thomas Gleixnerbed5ab62016-11-22 21:15:58 +00001026
1027 /* Update the domain data of the new package */
1028 rapl_update_domain_data(rp);
Jacob Pan2d281d82013-10-17 10:28:35 -07001029
Zhang Rui33823882019-07-10 21:44:30 +08001030 /* first we register package domain as the parent zone */
Jacob Pan2d281d82013-10-17 10:28:35 -07001031 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1032 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1033 nr_pl = find_nr_power_limit(rd);
Zhang Rui9ea76122019-05-13 13:58:53 -04001034 pr_debug("register package domain %s\n", rp->name);
Jacob Pan2d281d82013-10-17 10:28:35 -07001035 power_zone = powercap_register_zone(&rd->power_zone,
Zhang Rui33823882019-07-10 21:44:30 +08001036 rp->priv->control_type, rp->name,
1037 NULL, &zone_ops[rd->id], nr_pl,
1038 &constraint_ops);
Jacob Pan2d281d82013-10-17 10:28:35 -07001039 if (IS_ERR(power_zone)) {
Zhang Rui9ea76122019-05-13 13:58:53 -04001040 pr_debug("failed to register power zone %s\n",
Zhang Rui33823882019-07-10 21:44:30 +08001041 rp->name);
Thomas Gleixnerbed5ab62016-11-22 21:15:58 +00001042 return PTR_ERR(power_zone);
Jacob Pan2d281d82013-10-17 10:28:35 -07001043 }
1044 /* track parent zone in per package/socket data */
1045 rp->power_zone = power_zone;
1046 /* done, only one package domain per socket */
1047 break;
1048 }
1049 }
1050 if (!power_zone) {
1051 pr_err("no package domain found, unknown topology!\n");
Thomas Gleixnerbed5ab62016-11-22 21:15:58 +00001052 return -ENODEV;
Jacob Pan2d281d82013-10-17 10:28:35 -07001053 }
Zhang Rui33823882019-07-10 21:44:30 +08001054 /* now register domains as children of the socket/package */
Jacob Pan2d281d82013-10-17 10:28:35 -07001055 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1056 if (rd->id == RAPL_DOMAIN_PACKAGE)
1057 continue;
1058 /* number of power limits per domain varies */
1059 nr_pl = find_nr_power_limit(rd);
1060 power_zone = powercap_register_zone(&rd->power_zone,
Zhang Rui33823882019-07-10 21:44:30 +08001061 rp->priv->control_type,
1062 rd->name, rp->power_zone,
1063 &zone_ops[rd->id], nr_pl,
1064 &constraint_ops);
Jacob Pan2d281d82013-10-17 10:28:35 -07001065
1066 if (IS_ERR(power_zone)) {
Zhang Rui9ea76122019-05-13 13:58:53 -04001067 pr_debug("failed to register power_zone, %s:%s\n",
Zhang Rui33823882019-07-10 21:44:30 +08001068 rp->name, rd->name);
Jacob Pan2d281d82013-10-17 10:28:35 -07001069 ret = PTR_ERR(power_zone);
1070 goto err_cleanup;
1071 }
1072 }
Thomas Gleixnerbed5ab62016-11-22 21:15:58 +00001073 return 0;
Jacob Pan2d281d82013-10-17 10:28:35 -07001074
Jacob Pan2d281d82013-10-17 10:28:35 -07001075err_cleanup:
Thomas Gleixner58705062016-11-22 21:16:02 +00001076 /*
1077 * Clean up previously initialized domains within the package if we
Jacob Pan2d281d82013-10-17 10:28:35 -07001078 * failed after the first domain setup.
1079 */
1080 while (--rd >= rp->domains) {
Zhang Rui9ea76122019-05-13 13:58:53 -04001081 pr_debug("unregister %s domain %s\n", rp->name, rd->name);
Zhang Rui33823882019-07-10 21:44:30 +08001082 powercap_unregister_zone(rp->priv->control_type,
1083 &rd->power_zone);
Jacob Pan2d281d82013-10-17 10:28:35 -07001084 }
1085
1086 return ret;
1087}
1088
Zhang Rui33823882019-07-10 21:44:30 +08001089int rapl_add_platform_domain(struct rapl_if_priv *priv)
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001090{
1091 struct rapl_domain *rd;
1092 struct powercap_zone *power_zone;
Zhang Rui8a006762019-07-10 21:44:28 +08001093 struct reg_action ra;
1094 int ret;
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001095
Zhang Rui8a006762019-07-10 21:44:28 +08001096 ra.reg = priv->regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_STATUS];
1097 ra.mask = ~0;
1098 ret = priv->read_raw(0, &ra);
1099 if (ret || !ra.value)
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001100 return -ENODEV;
1101
Zhang Rui8a006762019-07-10 21:44:28 +08001102 ra.reg = priv->regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_LIMIT];
1103 ra.mask = ~0;
1104 ret = priv->read_raw(0, &ra);
1105 if (ret || !ra.value)
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001106 return -ENODEV;
1107
1108 rd = kzalloc(sizeof(*rd), GFP_KERNEL);
1109 if (!rd)
1110 return -ENOMEM;
1111
1112 rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
1113 rd->id = RAPL_DOMAIN_PLATFORM;
Zhang Rui33823882019-07-10 21:44:30 +08001114 rd->regs[RAPL_DOMAIN_REG_LIMIT] =
1115 priv->regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_LIMIT];
1116 rd->regs[RAPL_DOMAIN_REG_STATUS] =
1117 priv->regs[RAPL_DOMAIN_PLATFORM][RAPL_DOMAIN_REG_STATUS];
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001118 rd->rpl[0].prim_id = PL1_ENABLE;
1119 rd->rpl[0].name = pl1_name;
1120 rd->rpl[1].prim_id = PL2_ENABLE;
1121 rd->rpl[1].name = pl2_name;
Zhang Rui8a006762019-07-10 21:44:28 +08001122 rd->rp = rapl_find_package_domain(0, priv);
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001123
Zhang Rui8a006762019-07-10 21:44:28 +08001124 power_zone = powercap_register_zone(&rd->power_zone, priv->control_type,
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001125 "psys", NULL,
1126 &zone_ops[RAPL_DOMAIN_PLATFORM],
1127 2, &constraint_ops);
1128
1129 if (IS_ERR(power_zone)) {
1130 kfree(rd);
1131 return PTR_ERR(power_zone);
1132 }
1133
Zhang Rui8a006762019-07-10 21:44:28 +08001134 priv->platform_rapl_domain = rd;
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001135
1136 return 0;
1137}
Zhang Rui33823882019-07-10 21:44:30 +08001138EXPORT_SYMBOL_GPL(rapl_add_platform_domain);
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001139
Zhang Rui33823882019-07-10 21:44:30 +08001140void rapl_remove_platform_domain(struct rapl_if_priv *priv)
Jacob Pan2d281d82013-10-17 10:28:35 -07001141{
Zhang Rui8a006762019-07-10 21:44:28 +08001142 if (priv->platform_rapl_domain) {
1143 powercap_unregister_zone(priv->control_type,
Zhang Rui33823882019-07-10 21:44:30 +08001144 &priv->platform_rapl_domain->power_zone);
Zhang Rui8a006762019-07-10 21:44:28 +08001145 kfree(priv->platform_rapl_domain);
Jacob Pan2d281d82013-10-17 10:28:35 -07001146 }
Jacob Pan2d281d82013-10-17 10:28:35 -07001147}
Zhang Rui33823882019-07-10 21:44:30 +08001148EXPORT_SYMBOL_GPL(rapl_remove_platform_domain);
Jacob Pan2d281d82013-10-17 10:28:35 -07001149
Zhang Rui7fde2712019-07-10 21:44:26 +08001150static int rapl_check_domain(int cpu, int domain, struct rapl_package *rp)
Jacob Pan2d281d82013-10-17 10:28:35 -07001151{
Zhang Rui1193b162019-07-10 21:44:29 +08001152 struct reg_action ra;
Jacob Pan2d281d82013-10-17 10:28:35 -07001153
1154 switch (domain) {
1155 case RAPL_DOMAIN_PACKAGE:
Jacob Pan2d281d82013-10-17 10:28:35 -07001156 case RAPL_DOMAIN_PP0:
Jacob Pan2d281d82013-10-17 10:28:35 -07001157 case RAPL_DOMAIN_PP1:
Jacob Pan2d281d82013-10-17 10:28:35 -07001158 case RAPL_DOMAIN_DRAM:
Zhang Rui1193b162019-07-10 21:44:29 +08001159 ra.reg = rp->priv->regs[domain][RAPL_DOMAIN_REG_STATUS];
Jacob Pan2d281d82013-10-17 10:28:35 -07001160 break;
Srinivas Pandruvada3521ba12016-04-17 15:03:01 -07001161 case RAPL_DOMAIN_PLATFORM:
1162 /* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
1163 return -EINVAL;
Jacob Pan2d281d82013-10-17 10:28:35 -07001164 default:
1165 pr_err("invalid domain id %d\n", domain);
1166 return -EINVAL;
1167 }
Jacob Pan9d31c672014-04-29 15:33:06 -07001168 /* make sure domain counters are available and contains non-zero
1169 * values, otherwise skip it.
1170 */
Zhang Rui1193b162019-07-10 21:44:29 +08001171
1172 ra.mask = ~0;
1173 if (rp->priv->read_raw(cpu, &ra) || !ra.value)
Jacob Pan2d281d82013-10-17 10:28:35 -07001174 return -ENODEV;
1175
Jacob Pan9d31c672014-04-29 15:33:06 -07001176 return 0;
Jacob Pan2d281d82013-10-17 10:28:35 -07001177}
1178
Jacob Pane1399ba2016-05-31 13:41:29 -07001179/*
1180 * Check if power limits are available. Two cases when they are not available:
1181 * 1. Locked by BIOS, in this case we still provide read-only access so that
1182 * users can see what limit is set by the BIOS.
1183 * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not
Zhang Rui33823882019-07-10 21:44:30 +08001184 * exist at all. In this case, we do not show the constraints in powercap.
Jacob Pane1399ba2016-05-31 13:41:29 -07001185 *
1186 * Called after domains are detected and initialized.
1187 */
1188static void rapl_detect_powerlimit(struct rapl_domain *rd)
1189{
1190 u64 val64;
1191 int i;
1192
1193 /* check if the domain is locked by BIOS, ignore if MSR doesn't exist */
1194 if (!rapl_read_data_raw(rd, FW_LOCK, false, &val64)) {
1195 if (val64) {
Zhang Rui9ea76122019-05-13 13:58:53 -04001196 pr_info("RAPL %s domain %s locked by BIOS\n",
1197 rd->rp->name, rd->name);
Jacob Pane1399ba2016-05-31 13:41:29 -07001198 rd->state |= DOMAIN_STATE_BIOS_LOCKED;
1199 }
1200 }
Zhang Rui33823882019-07-10 21:44:30 +08001201 /* check if power limit MSR exists, otherwise domain is monitoring only */
Jacob Pane1399ba2016-05-31 13:41:29 -07001202 for (i = 0; i < NR_POWER_LIMITS; i++) {
1203 int prim = rd->rpl[i].prim_id;
Zhang Rui33823882019-07-10 21:44:30 +08001204
Jacob Pane1399ba2016-05-31 13:41:29 -07001205 if (rapl_read_data_raw(rd, prim, false, &val64))
1206 rd->rpl[i].name = NULL;
1207 }
1208}
1209
Jacob Pan2d281d82013-10-17 10:28:35 -07001210/* Detect active and valid domains for the given CPU, caller must
1211 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
1212 */
1213static int rapl_detect_domains(struct rapl_package *rp, int cpu)
1214{
Jacob Pan2d281d82013-10-17 10:28:35 -07001215 struct rapl_domain *rd;
Thomas Gleixner58705062016-11-22 21:16:02 +00001216 int i;
Jacob Pan2d281d82013-10-17 10:28:35 -07001217
1218 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
1219 /* use physical package id to read counters */
Zhang Rui7fde2712019-07-10 21:44:26 +08001220 if (!rapl_check_domain(cpu, i, rp)) {
Jacob Pan2d281d82013-10-17 10:28:35 -07001221 rp->domain_map |= 1 << i;
Jacob Panfcdf1792014-09-02 02:55:21 -07001222 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
1223 }
Jacob Pan2d281d82013-10-17 10:28:35 -07001224 }
Zhang Rui33823882019-07-10 21:44:30 +08001225 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
Jacob Pan2d281d82013-10-17 10:28:35 -07001226 if (!rp->nr_domains) {
Zhang Rui9ea76122019-05-13 13:58:53 -04001227 pr_debug("no valid rapl domains found in %s\n", rp->name);
Thomas Gleixner58705062016-11-22 21:16:02 +00001228 return -ENODEV;
Jacob Pan2d281d82013-10-17 10:28:35 -07001229 }
Zhang Rui9ea76122019-05-13 13:58:53 -04001230 pr_debug("found %d domains on %s\n", rp->nr_domains, rp->name);
Jacob Pan2d281d82013-10-17 10:28:35 -07001231
1232 rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
Zhang Rui33823882019-07-10 21:44:30 +08001233 GFP_KERNEL);
Thomas Gleixner58705062016-11-22 21:16:02 +00001234 if (!rp->domains)
1235 return -ENOMEM;
1236
Jacob Pan2d281d82013-10-17 10:28:35 -07001237 rapl_init_domains(rp);
1238
Jacob Pane1399ba2016-05-31 13:41:29 -07001239 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++)
1240 rapl_detect_powerlimit(rd);
1241
Jacob Pan2d281d82013-10-17 10:28:35 -07001242 return 0;
1243}
1244
1245/* called from CPU hotplug notifier, hotplug lock held */
Zhang Rui33823882019-07-10 21:44:30 +08001246void rapl_remove_package(struct rapl_package *rp)
Jacob Pan2d281d82013-10-17 10:28:35 -07001247{
1248 struct rapl_domain *rd, *rd_package = NULL;
1249
Thomas Gleixner58705062016-11-22 21:16:02 +00001250 package_power_limit_irq_restore(rp);
1251
Jacob Pan2d281d82013-10-17 10:28:35 -07001252 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
Thomas Gleixner58705062016-11-22 21:16:02 +00001253 rapl_write_data_raw(rd, PL1_ENABLE, 0);
1254 rapl_write_data_raw(rd, PL1_CLAMP, 0);
1255 if (find_nr_power_limit(rd) > 1) {
1256 rapl_write_data_raw(rd, PL2_ENABLE, 0);
1257 rapl_write_data_raw(rd, PL2_CLAMP, 0);
1258 }
Jacob Pan2d281d82013-10-17 10:28:35 -07001259 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1260 rd_package = rd;
1261 continue;
1262 }
Zhang Rui9ea76122019-05-13 13:58:53 -04001263 pr_debug("remove package, undo power limit on %s: %s\n",
1264 rp->name, rd->name);
Zhang Rui33823882019-07-10 21:44:30 +08001265 powercap_unregister_zone(rp->priv->control_type,
1266 &rd->power_zone);
Jacob Pan2d281d82013-10-17 10:28:35 -07001267 }
1268 /* do parent zone last */
Zhang Rui33823882019-07-10 21:44:30 +08001269 powercap_unregister_zone(rp->priv->control_type,
1270 &rd_package->power_zone);
Jacob Pan2d281d82013-10-17 10:28:35 -07001271 list_del(&rp->plist);
1272 kfree(rp);
1273}
Zhang Rui33823882019-07-10 21:44:30 +08001274EXPORT_SYMBOL_GPL(rapl_remove_package);
1275
1276/* caller to ensure CPU hotplug lock is held */
1277struct rapl_package *rapl_find_package_domain(int cpu, struct rapl_if_priv *priv)
1278{
1279 int id = topology_logical_die_id(cpu);
1280 struct rapl_package *rp;
1281
1282 list_for_each_entry(rp, &rapl_packages, plist) {
1283 if (rp->id == id
1284 && rp->priv->control_type == priv->control_type)
1285 return rp;
1286 }
1287
1288 return NULL;
1289}
1290EXPORT_SYMBOL_GPL(rapl_find_package_domain);
Jacob Pan2d281d82013-10-17 10:28:35 -07001291
1292/* called from CPU hotplug notifier, hotplug lock held */
Zhang Rui33823882019-07-10 21:44:30 +08001293struct rapl_package *rapl_add_package(int cpu, struct rapl_if_priv *priv)
Jacob Pan2d281d82013-10-17 10:28:35 -07001294{
Zhang Rui32fb4802019-05-13 13:58:51 -04001295 int id = topology_logical_die_id(cpu);
Jacob Pan2d281d82013-10-17 10:28:35 -07001296 struct rapl_package *rp;
Zhang Rui9ea76122019-05-13 13:58:53 -04001297 struct cpuinfo_x86 *c = &cpu_data(cpu);
Thomas Gleixnerb4005e92016-11-22 21:16:05 +00001298 int ret;
Jacob Pan2d281d82013-10-17 10:28:35 -07001299
Harry Pan3aa3c582019-12-30 22:36:56 +08001300 if (!rapl_defaults)
1301 return ERR_PTR(-ENODEV);
1302
Jacob Pan2d281d82013-10-17 10:28:35 -07001303 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
1304 if (!rp)
Thomas Gleixnerb4005e92016-11-22 21:16:05 +00001305 return ERR_PTR(-ENOMEM);
Jacob Pan2d281d82013-10-17 10:28:35 -07001306
1307 /* add the new package to the list */
Zhang Ruiaadf7b32019-05-13 13:58:50 -04001308 rp->id = id;
Jacob Pan323ee642016-02-24 13:31:38 -08001309 rp->lead_cpu = cpu;
Zhang Rui7ebf8ef2019-07-10 21:44:25 +08001310 rp->priv = priv;
Jacob Pan323ee642016-02-24 13:31:38 -08001311
Zhang Rui9ea76122019-05-13 13:58:53 -04001312 if (topology_max_die_per_package() > 1)
1313 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH,
Zhang Rui33823882019-07-10 21:44:30 +08001314 "package-%d-die-%d", c->phys_proc_id, c->cpu_die_id);
Zhang Rui9ea76122019-05-13 13:58:53 -04001315 else
1316 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d",
Zhang Rui33823882019-07-10 21:44:30 +08001317 c->phys_proc_id);
Zhang Rui9ea76122019-05-13 13:58:53 -04001318
Jacob Pan2d281d82013-10-17 10:28:35 -07001319 /* check if the package contains valid domains */
Zhang Rui33823882019-07-10 21:44:30 +08001320 if (rapl_detect_domains(rp, cpu) || rapl_defaults->check_unit(rp, cpu)) {
Jacob Pan2d281d82013-10-17 10:28:35 -07001321 ret = -ENODEV;
1322 goto err_free_package;
1323 }
Thomas Gleixnera74f4362016-11-22 21:15:59 +00001324 ret = rapl_package_register_powercap(rp);
1325 if (!ret) {
Jacob Pan2d281d82013-10-17 10:28:35 -07001326 INIT_LIST_HEAD(&rp->plist);
1327 list_add(&rp->plist, &rapl_packages);
Thomas Gleixnerb4005e92016-11-22 21:16:05 +00001328 return rp;
Jacob Pan2d281d82013-10-17 10:28:35 -07001329 }
1330
1331err_free_package:
1332 kfree(rp->domains);
1333 kfree(rp);
Thomas Gleixnerb4005e92016-11-22 21:16:05 +00001334 return ERR_PTR(ret);
Jacob Pan2d281d82013-10-17 10:28:35 -07001335}
Zhang Rui33823882019-07-10 21:44:30 +08001336EXPORT_SYMBOL_GPL(rapl_add_package);
Jacob Pan2d281d82013-10-17 10:28:35 -07001337
Zhen Han52b36722018-01-10 08:38:23 +08001338static void power_limit_state_save(void)
1339{
1340 struct rapl_package *rp;
1341 struct rapl_domain *rd;
1342 int nr_pl, ret, i;
1343
1344 get_online_cpus();
1345 list_for_each_entry(rp, &rapl_packages, plist) {
1346 if (!rp->power_zone)
1347 continue;
1348 rd = power_zone_to_rapl_domain(rp->power_zone);
1349 nr_pl = find_nr_power_limit(rd);
1350 for (i = 0; i < nr_pl; i++) {
1351 switch (rd->rpl[i].prim_id) {
1352 case PL1_ENABLE:
1353 ret = rapl_read_data_raw(rd,
Zhang Rui33823882019-07-10 21:44:30 +08001354 POWER_LIMIT1, true,
1355 &rd->rpl[i].last_power_limit);
Zhen Han52b36722018-01-10 08:38:23 +08001356 if (ret)
1357 rd->rpl[i].last_power_limit = 0;
1358 break;
1359 case PL2_ENABLE:
1360 ret = rapl_read_data_raw(rd,
Zhang Rui33823882019-07-10 21:44:30 +08001361 POWER_LIMIT2, true,
1362 &rd->rpl[i].last_power_limit);
Zhen Han52b36722018-01-10 08:38:23 +08001363 if (ret)
1364 rd->rpl[i].last_power_limit = 0;
1365 break;
1366 }
1367 }
1368 }
1369 put_online_cpus();
1370}
1371
1372static void power_limit_state_restore(void)
1373{
1374 struct rapl_package *rp;
1375 struct rapl_domain *rd;
1376 int nr_pl, i;
1377
1378 get_online_cpus();
1379 list_for_each_entry(rp, &rapl_packages, plist) {
1380 if (!rp->power_zone)
1381 continue;
1382 rd = power_zone_to_rapl_domain(rp->power_zone);
1383 nr_pl = find_nr_power_limit(rd);
1384 for (i = 0; i < nr_pl; i++) {
1385 switch (rd->rpl[i].prim_id) {
1386 case PL1_ENABLE:
1387 if (rd->rpl[i].last_power_limit)
Zhang Rui33823882019-07-10 21:44:30 +08001388 rapl_write_data_raw(rd, POWER_LIMIT1,
1389 rd->rpl[i].last_power_limit);
Zhen Han52b36722018-01-10 08:38:23 +08001390 break;
1391 case PL2_ENABLE:
1392 if (rd->rpl[i].last_power_limit)
Zhang Rui33823882019-07-10 21:44:30 +08001393 rapl_write_data_raw(rd, POWER_LIMIT2,
1394 rd->rpl[i].last_power_limit);
Zhen Han52b36722018-01-10 08:38:23 +08001395 break;
1396 }
1397 }
1398 }
1399 put_online_cpus();
1400}
1401
1402static int rapl_pm_callback(struct notifier_block *nb,
Zhang Rui33823882019-07-10 21:44:30 +08001403 unsigned long mode, void *_unused)
Zhen Han52b36722018-01-10 08:38:23 +08001404{
1405 switch (mode) {
1406 case PM_SUSPEND_PREPARE:
1407 power_limit_state_save();
1408 break;
1409 case PM_POST_SUSPEND:
1410 power_limit_state_restore();
1411 break;
1412 }
1413 return NOTIFY_OK;
1414}
1415
1416static struct notifier_block rapl_pm_notifier = {
1417 .notifier_call = rapl_pm_callback,
1418};
1419
Zhang Ruiabcfaeb2019-07-10 21:44:34 +08001420static struct platform_device *rapl_msr_platdev;
1421
1422static int __init rapl_init(void)
Jacob Pan2d281d82013-10-17 10:28:35 -07001423{
Jacob Pan087e9cb2014-11-07 09:29:25 -08001424 const struct x86_cpu_id *id;
Thomas Gleixner58705062016-11-22 21:16:02 +00001425 int ret;
Jacob Pan2d281d82013-10-17 10:28:35 -07001426
Jacob Pan087e9cb2014-11-07 09:29:25 -08001427 id = x86_match_cpu(rapl_ids);
1428 if (!id) {
Jacob Pan2d281d82013-10-17 10:28:35 -07001429 pr_err("driver does not support CPU family %d model %d\n",
Zhang Rui33823882019-07-10 21:44:30 +08001430 boot_cpu_data.x86, boot_cpu_data.x86_model);
Jacob Pan2d281d82013-10-17 10:28:35 -07001431
1432 return -ENODEV;
1433 }
Srivatsa S. Bhat009f2252014-03-11 02:09:26 +05301434
Jacob Pan087e9cb2014-11-07 09:29:25 -08001435 rapl_defaults = (struct rapl_defaults *)id->driver_data;
1436
Zhen Han52b36722018-01-10 08:38:23 +08001437 ret = register_pm_notifier(&rapl_pm_notifier);
Zhang Ruiabcfaeb2019-07-10 21:44:34 +08001438 if (ret)
1439 return ret;
Zhen Han52b36722018-01-10 08:38:23 +08001440
Zhang Ruiabcfaeb2019-07-10 21:44:34 +08001441 rapl_msr_platdev = platform_device_alloc("intel_rapl_msr", 0);
1442 if (!rapl_msr_platdev) {
1443 ret = -ENOMEM;
1444 goto end;
1445 }
1446
1447 ret = platform_device_add(rapl_msr_platdev);
1448 if (ret)
1449 platform_device_put(rapl_msr_platdev);
1450
1451end:
1452 if (ret)
1453 unregister_pm_notifier(&rapl_pm_notifier);
1454
1455 return ret;
Jacob Pan2d281d82013-10-17 10:28:35 -07001456}
1457
Zhang Ruiabcfaeb2019-07-10 21:44:34 +08001458static void __exit rapl_exit(void)
Jacob Pan2d281d82013-10-17 10:28:35 -07001459{
Zhang Ruiabcfaeb2019-07-10 21:44:34 +08001460 platform_device_unregister(rapl_msr_platdev);
Zhen Han52b36722018-01-10 08:38:23 +08001461 unregister_pm_notifier(&rapl_pm_notifier);
Jacob Pan2d281d82013-10-17 10:28:35 -07001462}
1463
Zhang Ruif76cb062019-07-19 23:25:14 +08001464fs_initcall(rapl_init);
Zhang Ruiabcfaeb2019-07-10 21:44:34 +08001465module_exit(rapl_exit);
1466
Zhang Rui33823882019-07-10 21:44:30 +08001467MODULE_DESCRIPTION("Intel Runtime Average Power Limit (RAPL) common code");
Jacob Pan2d281d82013-10-17 10:28:35 -07001468MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
1469MODULE_LICENSE("GPL v2");