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Benjamin Gaignard8de50dc2017-11-30 09:45:00 +01001// SPDX-License-Identifier: GPL-2.0
Alexandre TORGUEe07204162016-09-20 18:00:57 +02002/*
3 * Copyright (C) Maxime Coquelin 2015
Benjamin Gaignard8de50dc2017-11-30 09:45:00 +01004 * Copyright (C) STMicroelectronics 2017
Alexandre TORGUEe07204162016-09-20 18:00:57 +02005 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Alexandre TORGUEe07204162016-09-20 18:00:57 +02006 */
7
8#include <linux/bitops.h>
Benjamin Gaignardfb941092018-12-17 15:22:14 +01009#include <linux/delay.h>
10#include <linux/hwspinlock.h>
Alexandre TORGUEe07204162016-09-20 18:00:57 +020011#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/irqchip.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
Fabien Dessennecfbf9e42019-04-17 15:02:56 +020017#include <linux/module.h>
Alexandre TORGUEe07204162016-09-20 18:00:57 +020018#include <linux/of_address.h>
19#include <linux/of_irq.h>
Fabien Dessennecfbf9e42019-04-17 15:02:56 +020020#include <linux/of_platform.h>
Ludovic Barre73958b32018-04-26 18:18:31 +020021#include <linux/syscore_ops.h>
Alexandre TORGUEe07204162016-09-20 18:00:57 +020022
Ludovic Barre927abfc2018-04-26 18:18:30 +020023#include <dt-bindings/interrupt-controller/arm-gic.h>
24
Ludovic Barre6dd64ee2017-11-06 18:03:32 +010025#define IRQS_PER_BANK 32
26
Benjamin Gaignardfb941092018-12-17 15:22:14 +010027#define HWSPNLCK_TIMEOUT 1000 /* usec */
Benjamin Gaignardfb941092018-12-17 15:22:14 +010028
Ludovic Barre6dd64ee2017-11-06 18:03:32 +010029struct stm32_exti_bank {
30 u32 imr_ofst;
31 u32 emr_ofst;
32 u32 rtsr_ofst;
33 u32 ftsr_ofst;
34 u32 swier_ofst;
Ludovic Barrebe6230f2018-04-26 18:18:26 +020035 u32 rpr_ofst;
36 u32 fpr_ofst;
Ludovic Barre6dd64ee2017-11-06 18:03:32 +010037};
38
Ludovic Barrebe6230f2018-04-26 18:18:26 +020039#define UNDEF_REG ~0
40
Ludovic Barre927abfc2018-04-26 18:18:30 +020041struct stm32_desc_irq {
42 u32 exti;
43 u32 irq_parent;
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +020044 struct irq_chip *chip;
Ludovic Barre927abfc2018-04-26 18:18:30 +020045};
46
Ludovic Barref9fc1742018-04-26 18:18:28 +020047struct stm32_exti_drv_data {
48 const struct stm32_exti_bank **exti_banks;
Ludovic Barre927abfc2018-04-26 18:18:30 +020049 const struct stm32_desc_irq *desc_irqs;
Ludovic Barref9fc1742018-04-26 18:18:28 +020050 u32 bank_nr;
Ludovic Barre927abfc2018-04-26 18:18:30 +020051 u32 irq_nr;
Ludovic Barref9fc1742018-04-26 18:18:28 +020052};
53
Ludovic Barred9e2b19b02018-04-26 18:18:27 +020054struct stm32_exti_chip_data {
Ludovic Barref9fc1742018-04-26 18:18:28 +020055 struct stm32_exti_host_data *host_data;
Ludovic Barred9e2b19b02018-04-26 18:18:27 +020056 const struct stm32_exti_bank *reg_bank;
Ludovic Barre927abfc2018-04-26 18:18:30 +020057 struct raw_spinlock rlock;
58 u32 wake_active;
59 u32 mask_cache;
Ludovic Barred9e2b19b02018-04-26 18:18:27 +020060 u32 rtsr_cache;
61 u32 ftsr_cache;
62};
63
Ludovic Barref9fc1742018-04-26 18:18:28 +020064struct stm32_exti_host_data {
65 void __iomem *base;
66 struct stm32_exti_chip_data *chips_data;
67 const struct stm32_exti_drv_data *drv_data;
Benjamin Gaignardfb941092018-12-17 15:22:14 +010068 struct hwspinlock *hwlock;
Ludovic Barref9fc1742018-04-26 18:18:28 +020069};
Ludovic Barred9e2b19b02018-04-26 18:18:27 +020070
Ludovic Barre73958b32018-04-26 18:18:31 +020071static struct stm32_exti_host_data *stm32_host_data;
72
Ludovic Barre6dd64ee2017-11-06 18:03:32 +010073static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
74 .imr_ofst = 0x00,
75 .emr_ofst = 0x04,
76 .rtsr_ofst = 0x08,
77 .ftsr_ofst = 0x0C,
78 .swier_ofst = 0x10,
Ludovic Barrebe6230f2018-04-26 18:18:26 +020079 .rpr_ofst = 0x14,
80 .fpr_ofst = UNDEF_REG,
Ludovic Barre6dd64ee2017-11-06 18:03:32 +010081};
82
83static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
84 &stm32f4xx_exti_b1,
85};
86
Ludovic Barref9fc1742018-04-26 18:18:28 +020087static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
88 .exti_banks = stm32f4xx_exti_banks,
89 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
90};
91
Ludovic Barre539c6032017-11-06 18:03:34 +010092static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
93 .imr_ofst = 0x80,
94 .emr_ofst = 0x84,
95 .rtsr_ofst = 0x00,
96 .ftsr_ofst = 0x04,
97 .swier_ofst = 0x08,
Ludovic Barrebe6230f2018-04-26 18:18:26 +020098 .rpr_ofst = 0x88,
99 .fpr_ofst = UNDEF_REG,
Ludovic Barre539c6032017-11-06 18:03:34 +0100100};
101
102static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
103 .imr_ofst = 0x90,
104 .emr_ofst = 0x94,
105 .rtsr_ofst = 0x20,
106 .ftsr_ofst = 0x24,
107 .swier_ofst = 0x28,
Ludovic Barrebe6230f2018-04-26 18:18:26 +0200108 .rpr_ofst = 0x98,
109 .fpr_ofst = UNDEF_REG,
Ludovic Barre539c6032017-11-06 18:03:34 +0100110};
111
112static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
113 .imr_ofst = 0xA0,
114 .emr_ofst = 0xA4,
115 .rtsr_ofst = 0x40,
116 .ftsr_ofst = 0x44,
117 .swier_ofst = 0x48,
Ludovic Barrebe6230f2018-04-26 18:18:26 +0200118 .rpr_ofst = 0xA8,
119 .fpr_ofst = UNDEF_REG,
Ludovic Barre539c6032017-11-06 18:03:34 +0100120};
121
122static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
123 &stm32h7xx_exti_b1,
124 &stm32h7xx_exti_b2,
125 &stm32h7xx_exti_b3,
126};
127
Ludovic Barref9fc1742018-04-26 18:18:28 +0200128static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
129 .exti_banks = stm32h7xx_exti_banks,
130 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
131};
132
Ludovic Barre927abfc2018-04-26 18:18:30 +0200133static const struct stm32_exti_bank stm32mp1_exti_b1 = {
134 .imr_ofst = 0x80,
135 .emr_ofst = 0x84,
136 .rtsr_ofst = 0x00,
137 .ftsr_ofst = 0x04,
138 .swier_ofst = 0x08,
139 .rpr_ofst = 0x0C,
140 .fpr_ofst = 0x10,
141};
142
143static const struct stm32_exti_bank stm32mp1_exti_b2 = {
144 .imr_ofst = 0x90,
145 .emr_ofst = 0x94,
146 .rtsr_ofst = 0x20,
147 .ftsr_ofst = 0x24,
148 .swier_ofst = 0x28,
149 .rpr_ofst = 0x2C,
150 .fpr_ofst = 0x30,
151};
152
153static const struct stm32_exti_bank stm32mp1_exti_b3 = {
154 .imr_ofst = 0xA0,
155 .emr_ofst = 0xA4,
156 .rtsr_ofst = 0x40,
157 .ftsr_ofst = 0x44,
158 .swier_ofst = 0x48,
159 .rpr_ofst = 0x4C,
160 .fpr_ofst = 0x50,
161};
162
163static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
164 &stm32mp1_exti_b1,
165 &stm32mp1_exti_b2,
166 &stm32mp1_exti_b3,
167};
168
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200169static struct irq_chip stm32_exti_h_chip;
170static struct irq_chip stm32_exti_h_chip_direct;
171
Ludovic Barre927abfc2018-04-26 18:18:30 +0200172static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200173 { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
174 { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
175 { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
176 { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
177 { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
178 { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
179 { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
180 { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
181 { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
182 { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
183 { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
184 { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
185 { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
186 { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
187 { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
188 { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
189 { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
190 { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
191 { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
192 { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
193 { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
194 { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
195 { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
Erwan Le Raye12c4552021-03-19 19:42:51 +0100196 { .exti = 26, .irq_parent = 37, .chip = &stm32_exti_h_chip_direct },
197 { .exti = 27, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct },
198 { .exti = 28, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct },
199 { .exti = 29, .irq_parent = 71, .chip = &stm32_exti_h_chip_direct },
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200200 { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
Erwan Le Raye12c4552021-03-19 19:42:51 +0100201 { .exti = 31, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct },
202 { .exti = 32, .irq_parent = 82, .chip = &stm32_exti_h_chip_direct },
203 { .exti = 33, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct },
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200204 { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
Fabrice Gasniera00e85b2020-10-16 16:40:17 +0200205 { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
206 { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
207 { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
208 { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200209 { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
210 { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
211 { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
212 { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
213 { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
214 { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
Ludovic Barre927abfc2018-04-26 18:18:30 +0200215};
216
217static const struct stm32_exti_drv_data stm32mp1_drv_data = {
218 .exti_banks = stm32mp1_exti_banks,
219 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
220 .desc_irqs = stm32mp1_desc_irq,
221 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
222};
223
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200224static const struct
225stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
226 irq_hw_number_t hwirq)
Ludovic Barre927abfc2018-04-26 18:18:30 +0200227{
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200228 const struct stm32_desc_irq *desc = NULL;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200229 int i;
230
231 if (!drv_data->desc_irqs)
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200232 return NULL;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200233
234 for (i = 0; i < drv_data->irq_nr; i++) {
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200235 desc = &drv_data->desc_irqs[i];
236 if (desc->exti == hwirq)
237 break;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200238 }
239
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200240 return desc;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200241}
242
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100243static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
244{
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200245 struct stm32_exti_chip_data *chip_data = gc->private;
246 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
Ludovic Barrebe6230f2018-04-26 18:18:26 +0200247 unsigned long pending;
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100248
Ludovic Barrebe6230f2018-04-26 18:18:26 +0200249 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
250 if (stm32_bank->fpr_ofst != UNDEF_REG)
251 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
252
253 return pending;
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100254}
255
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200256static void stm32_irq_handler(struct irq_desc *desc)
257{
258 struct irq_domain *domain = irq_desc_get_handler_data(desc);
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200259 struct irq_chip *chip = irq_desc_get_chip(desc);
Marc Zyngier046a6ee2021-05-04 17:42:18 +0100260 unsigned int nbanks = domain->gc->num_chips;
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100261 struct irq_chip_generic *gc;
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200262 unsigned long pending;
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100263 int n, i, irq_base = 0;
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200264
265 chained_irq_enter(chip, desc);
266
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100267 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
268 gc = irq_get_domain_generic_chip(domain, irq_base);
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100269
270 while ((pending = stm32_exti_pending(gc))) {
Marc Zyngier046a6ee2021-05-04 17:42:18 +0100271 for_each_set_bit(n, &pending, IRQS_PER_BANK)
272 generic_handle_domain_irq(domain, irq_base + n);
273 }
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200274 }
275
276 chained_irq_exit(chip, desc);
277}
278
Ludovic Barre5a2490e2018-04-26 18:18:29 +0200279static int stm32_exti_set_type(struct irq_data *d,
280 unsigned int type, u32 *rtsr, u32 *ftsr)
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200281{
Ludovic Barre5a2490e2018-04-26 18:18:29 +0200282 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
283
284 switch (type) {
285 case IRQ_TYPE_EDGE_RISING:
286 *rtsr |= mask;
287 *ftsr &= ~mask;
288 break;
289 case IRQ_TYPE_EDGE_FALLING:
290 *rtsr &= ~mask;
291 *ftsr |= mask;
292 break;
293 case IRQ_TYPE_EDGE_BOTH:
294 *rtsr |= mask;
295 *ftsr |= mask;
296 break;
297 default:
298 return -EINVAL;
299 }
300
301 return 0;
302}
303
304static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
305{
306 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200307 struct stm32_exti_chip_data *chip_data = gc->private;
308 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
Fabien Dessenne52571692020-07-06 10:11:15 +0200309 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200310 u32 rtsr, ftsr;
Ludovic Barre5a2490e2018-04-26 18:18:29 +0200311 int err;
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200312
313 irq_gc_lock(gc);
314
Fabien Dessenne52571692020-07-06 10:11:15 +0200315 if (hwlock) {
316 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
317 if (err) {
318 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
319 goto unlock;
320 }
321 }
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100322
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100323 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
324 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200325
Ludovic Barre5a2490e2018-04-26 18:18:29 +0200326 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100327 if (err)
328 goto unspinlock;
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200329
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100330 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
331 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200332
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100333unspinlock:
Fabien Dessenne52571692020-07-06 10:11:15 +0200334 if (hwlock)
335 hwspin_unlock_in_atomic(hwlock);
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100336unlock:
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200337 irq_gc_unlock(gc);
338
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100339 return err;
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200340}
341
Ludovic Barre5a2490e2018-04-26 18:18:29 +0200342static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
343 u32 wake_active)
344{
345 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
346 void __iomem *base = chip_data->host_data->base;
347
348 /* save rtsr, ftsr registers */
349 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
350 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
351
352 writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
353}
354
355static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
356 u32 mask_cache)
357{
358 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
359 void __iomem *base = chip_data->host_data->base;
360
361 /* restore rtsr, ftsr, registers */
362 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
363 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
364
365 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
366}
367
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200368static void stm32_irq_suspend(struct irq_chip_generic *gc)
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200369{
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200370 struct stm32_exti_chip_data *chip_data = gc->private;
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200371
372 irq_gc_lock(gc);
Ludovic Barre5a2490e2018-04-26 18:18:29 +0200373 stm32_chip_suspend(chip_data, gc->wake_active);
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200374 irq_gc_unlock(gc);
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200375}
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200376
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200377static void stm32_irq_resume(struct irq_chip_generic *gc)
378{
379 struct stm32_exti_chip_data *chip_data = gc->private;
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200380
381 irq_gc_lock(gc);
Ludovic Barre5a2490e2018-04-26 18:18:29 +0200382 stm32_chip_resume(chip_data, gc->mask_cache);
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200383 irq_gc_unlock(gc);
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200384}
385
386static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
387 unsigned int nr_irqs, void *data)
388{
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200389 struct irq_fwspec *fwspec = data;
390 irq_hw_number_t hwirq;
391
392 hwirq = fwspec->param[0];
393
394 irq_map_generic_chip(d, virq, hwirq);
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200395
396 return 0;
397}
398
399static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
400 unsigned int nr_irqs)
401{
402 struct irq_data *data = irq_domain_get_irq_data(d, virq);
403
404 irq_domain_reset_irq_data(data);
405}
406
Ludovic Barreea80aa22018-04-26 18:18:25 +0200407static const struct irq_domain_ops irq_exti_domain_ops = {
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200408 .map = irq_map_generic_chip,
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200409 .alloc = stm32_exti_alloc,
410 .free = stm32_exti_free,
411};
412
Ludovic Barrebe6230f2018-04-26 18:18:26 +0200413static void stm32_irq_ack(struct irq_data *d)
414{
415 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200416 struct stm32_exti_chip_data *chip_data = gc->private;
417 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
Ludovic Barrebe6230f2018-04-26 18:18:26 +0200418
419 irq_gc_lock(gc);
420
421 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
422 if (stm32_bank->fpr_ofst != UNDEF_REG)
423 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
424
425 irq_gc_unlock(gc);
426}
Ludovic Barre927abfc2018-04-26 18:18:30 +0200427
qiuguorui1e5790762020-08-20 11:16:29 +0800428/* directly set the target bit without reading first. */
429static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
430{
431 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
432 void __iomem *base = chip_data->host_data->base;
433 u32 val = BIT(d->hwirq % IRQS_PER_BANK);
434
435 writel_relaxed(val, base + reg);
436}
437
Ludovic Barre927abfc2018-04-26 18:18:30 +0200438static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
439{
440 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
441 void __iomem *base = chip_data->host_data->base;
442 u32 val;
443
444 val = readl_relaxed(base + reg);
445 val |= BIT(d->hwirq % IRQS_PER_BANK);
446 writel_relaxed(val, base + reg);
447
448 return val;
449}
450
451static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
452{
453 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
454 void __iomem *base = chip_data->host_data->base;
455 u32 val;
456
457 val = readl_relaxed(base + reg);
458 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
459 writel_relaxed(val, base + reg);
460
461 return val;
462}
463
464static void stm32_exti_h_eoi(struct irq_data *d)
465{
466 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
467 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
468
469 raw_spin_lock(&chip_data->rlock);
470
qiuguorui1e5790762020-08-20 11:16:29 +0800471 stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
Ludovic Barre927abfc2018-04-26 18:18:30 +0200472 if (stm32_bank->fpr_ofst != UNDEF_REG)
qiuguorui1e5790762020-08-20 11:16:29 +0800473 stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
Ludovic Barre927abfc2018-04-26 18:18:30 +0200474
475 raw_spin_unlock(&chip_data->rlock);
476
477 if (d->parent_data->chip)
478 irq_chip_eoi_parent(d);
479}
480
481static void stm32_exti_h_mask(struct irq_data *d)
482{
483 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
484 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
485
486 raw_spin_lock(&chip_data->rlock);
487 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
488 raw_spin_unlock(&chip_data->rlock);
489
490 if (d->parent_data->chip)
491 irq_chip_mask_parent(d);
492}
493
494static void stm32_exti_h_unmask(struct irq_data *d)
495{
496 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
497 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
498
499 raw_spin_lock(&chip_data->rlock);
500 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
501 raw_spin_unlock(&chip_data->rlock);
502
503 if (d->parent_data->chip)
504 irq_chip_unmask_parent(d);
505}
506
507static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
508{
509 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
510 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
Fabien Dessenne52571692020-07-06 10:11:15 +0200511 struct hwspinlock *hwlock = chip_data->host_data->hwlock;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200512 void __iomem *base = chip_data->host_data->base;
513 u32 rtsr, ftsr;
514 int err;
515
516 raw_spin_lock(&chip_data->rlock);
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100517
Fabien Dessenne52571692020-07-06 10:11:15 +0200518 if (hwlock) {
519 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
520 if (err) {
521 pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
522 goto unlock;
523 }
524 }
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100525
Ludovic Barre927abfc2018-04-26 18:18:30 +0200526 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
527 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
528
529 err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100530 if (err)
531 goto unspinlock;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200532
533 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
534 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100535
536unspinlock:
Fabien Dessenne52571692020-07-06 10:11:15 +0200537 if (hwlock)
538 hwspin_unlock_in_atomic(hwlock);
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100539unlock:
Ludovic Barre927abfc2018-04-26 18:18:30 +0200540 raw_spin_unlock(&chip_data->rlock);
541
Benjamin Gaignardfb941092018-12-17 15:22:14 +0100542 return err;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200543}
544
545static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
546{
547 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
548 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
549
550 raw_spin_lock(&chip_data->rlock);
551
552 if (on)
553 chip_data->wake_active |= mask;
554 else
555 chip_data->wake_active &= ~mask;
556
557 raw_spin_unlock(&chip_data->rlock);
558
559 return 0;
560}
561
562static int stm32_exti_h_set_affinity(struct irq_data *d,
563 const struct cpumask *dest, bool force)
564{
565 if (d->parent_data->chip)
566 return irq_chip_set_affinity_parent(d, dest, force);
567
568 return -EINVAL;
569}
570
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200571static int __maybe_unused stm32_exti_h_suspend(void)
Ludovic Barre73958b32018-04-26 18:18:31 +0200572{
573 struct stm32_exti_chip_data *chip_data;
574 int i;
575
576 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
577 chip_data = &stm32_host_data->chips_data[i];
578 raw_spin_lock(&chip_data->rlock);
579 stm32_chip_suspend(chip_data, chip_data->wake_active);
580 raw_spin_unlock(&chip_data->rlock);
581 }
582
583 return 0;
584}
585
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200586static void __maybe_unused stm32_exti_h_resume(void)
Ludovic Barre73958b32018-04-26 18:18:31 +0200587{
588 struct stm32_exti_chip_data *chip_data;
589 int i;
590
591 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
592 chip_data = &stm32_host_data->chips_data[i];
593 raw_spin_lock(&chip_data->rlock);
594 stm32_chip_resume(chip_data, chip_data->mask_cache);
595 raw_spin_unlock(&chip_data->rlock);
596 }
597}
598
599static struct syscore_ops stm32_exti_h_syscore_ops = {
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200600#ifdef CONFIG_PM_SLEEP
Ludovic Barre73958b32018-04-26 18:18:31 +0200601 .suspend = stm32_exti_h_suspend,
602 .resume = stm32_exti_h_resume,
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200603#endif
Ludovic Barre73958b32018-04-26 18:18:31 +0200604};
605
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200606static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
Ludovic Barre73958b32018-04-26 18:18:31 +0200607{
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200608 stm32_host_data = host_data;
Ludovic Barre73958b32018-04-26 18:18:31 +0200609 register_syscore_ops(&stm32_exti_h_syscore_ops);
610}
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200611
612static void stm32_exti_h_syscore_deinit(void)
613{
614 unregister_syscore_ops(&stm32_exti_h_syscore_ops);
615}
Ludovic Barre73958b32018-04-26 18:18:31 +0200616
Alexandre Torgue25591d42020-02-19 15:32:28 +0100617static int stm32_exti_h_retrigger(struct irq_data *d)
618{
619 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
620 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
621 void __iomem *base = chip_data->host_data->base;
622 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
623
624 writel_relaxed(mask, base + stm32_bank->swier_ofst);
625
626 return 0;
627}
628
Ludovic Barre927abfc2018-04-26 18:18:30 +0200629static struct irq_chip stm32_exti_h_chip = {
630 .name = "stm32-exti-h",
631 .irq_eoi = stm32_exti_h_eoi,
632 .irq_mask = stm32_exti_h_mask,
633 .irq_unmask = stm32_exti_h_unmask,
Alexandre Torgue25591d42020-02-19 15:32:28 +0100634 .irq_retrigger = stm32_exti_h_retrigger,
Ludovic Barre927abfc2018-04-26 18:18:30 +0200635 .irq_set_type = stm32_exti_h_set_type,
636 .irq_set_wake = stm32_exti_h_set_wake,
637 .flags = IRQCHIP_MASK_ON_SUSPEND,
Arnd Bergmanna84277b2018-06-05 13:43:34 +0200638 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
Ludovic Barre927abfc2018-04-26 18:18:30 +0200639};
640
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200641static struct irq_chip stm32_exti_h_chip_direct = {
642 .name = "stm32-exti-h-direct",
643 .irq_eoi = irq_chip_eoi_parent,
644 .irq_ack = irq_chip_ack_parent,
645 .irq_mask = irq_chip_mask_parent,
646 .irq_unmask = irq_chip_unmask_parent,
647 .irq_retrigger = irq_chip_retrigger_hierarchy,
648 .irq_set_type = irq_chip_set_type_parent,
649 .irq_set_wake = stm32_exti_h_set_wake,
650 .flags = IRQCHIP_MASK_ON_SUSPEND,
651 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
652};
653
Ludovic Barre927abfc2018-04-26 18:18:30 +0200654static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
655 unsigned int virq,
656 unsigned int nr_irqs, void *data)
657{
658 struct stm32_exti_host_data *host_data = dm->host_data;
659 struct stm32_exti_chip_data *chip_data;
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200660 const struct stm32_desc_irq *desc;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200661 struct irq_fwspec *fwspec = data;
662 struct irq_fwspec p_fwspec;
663 irq_hw_number_t hwirq;
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200664 int bank;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200665
666 hwirq = fwspec->param[0];
667 bank = hwirq / IRQS_PER_BANK;
668 chip_data = &host_data->chips_data[bank];
669
Ludovic Barre927abfc2018-04-26 18:18:30 +0200670
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200671 desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
672 if (!desc)
673 return -EINVAL;
674
675 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
676 chip_data);
677 if (desc->irq_parent) {
Ludovic Barre927abfc2018-04-26 18:18:30 +0200678 p_fwspec.fwnode = dm->parent->fwnode;
679 p_fwspec.param_count = 3;
680 p_fwspec.param[0] = GIC_SPI;
Alexandre Torgue9d6a5fe2020-07-17 16:07:17 +0200681 p_fwspec.param[1] = desc->irq_parent;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200682 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
683
684 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
685 }
686
687 return 0;
688}
689
Ludovic Barref9fc1742018-04-26 18:18:28 +0200690static struct
691stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
692 struct device_node *node)
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200693{
Ludovic Barref9fc1742018-04-26 18:18:28 +0200694 struct stm32_exti_host_data *host_data;
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200695
Ludovic Barref9fc1742018-04-26 18:18:28 +0200696 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
697 if (!host_data)
698 return NULL;
699
700 host_data->drv_data = dd;
701 host_data->chips_data = kcalloc(dd->bank_nr,
702 sizeof(struct stm32_exti_chip_data),
703 GFP_KERNEL);
704 if (!host_data->chips_data)
Dan Carpenter40961652018-08-08 15:03:19 +0300705 goto free_host_data;
Ludovic Barref9fc1742018-04-26 18:18:28 +0200706
707 host_data->base = of_iomap(node, 0);
708 if (!host_data->base) {
Rob Herringe81f54c2017-07-18 16:43:10 -0500709 pr_err("%pOF: Unable to map registers\n", node);
Dan Carpenter40961652018-08-08 15:03:19 +0300710 goto free_chips_data;
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200711 }
712
Ludovic Barre73958b32018-04-26 18:18:31 +0200713 stm32_host_data = host_data;
714
Ludovic Barref9fc1742018-04-26 18:18:28 +0200715 return host_data;
Dan Carpenter40961652018-08-08 15:03:19 +0300716
717free_chips_data:
718 kfree(host_data->chips_data);
719free_host_data:
720 kfree(host_data);
721
722 return NULL;
Ludovic Barref9fc1742018-04-26 18:18:28 +0200723}
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200724
Ludovic Barref9fc1742018-04-26 18:18:28 +0200725static struct
726stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200727 u32 bank_idx,
728 struct device_node *node)
Ludovic Barref9fc1742018-04-26 18:18:28 +0200729{
730 const struct stm32_exti_bank *stm32_bank;
731 struct stm32_exti_chip_data *chip_data;
732 void __iomem *base = h_data->base;
Ludovic Barref9fc1742018-04-26 18:18:28 +0200733
734 stm32_bank = h_data->drv_data->exti_banks[bank_idx];
735 chip_data = &h_data->chips_data[bank_idx];
736 chip_data->host_data = h_data;
737 chip_data->reg_bank = stm32_bank;
738
Ludovic Barre927abfc2018-04-26 18:18:30 +0200739 raw_spin_lock_init(&chip_data->rlock);
740
Ludovic Barref9fc1742018-04-26 18:18:28 +0200741 /*
742 * This IP has no reset, so after hot reboot we should
743 * clear registers to avoid residue
744 */
745 writel_relaxed(0, base + stm32_bank->imr_ofst);
746 writel_relaxed(0, base + stm32_bank->emr_ofst);
Ludovic Barref9fc1742018-04-26 18:18:28 +0200747
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200748 pr_info("%pOF: bank%d\n", node, bank_idx);
Ludovic Barref9fc1742018-04-26 18:18:28 +0200749
750 return chip_data;
751}
752
753static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
754 struct device_node *node)
755{
756 struct stm32_exti_host_data *host_data;
757 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
758 int nr_irqs, ret, i;
759 struct irq_chip_generic *gc;
760 struct irq_domain *domain;
761
762 host_data = stm32_exti_host_init(drv_data, node);
Dan Carpenter40961652018-08-08 15:03:19 +0300763 if (!host_data)
764 return -ENOMEM;
Ludovic Barref9fc1742018-04-26 18:18:28 +0200765
766 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200767 &irq_exti_domain_ops, NULL);
768 if (!domain) {
Yangtao Lif9c75bc2018-11-23 11:54:18 -0500769 pr_err("%pOFn: Could not register interrupt domain.\n",
770 node);
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200771 ret = -ENOMEM;
772 goto out_unmap;
773 }
774
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100775 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200776 handle_edge_irq, clr, 0, 0);
777 if (ret) {
Rob Herringe81f54c2017-07-18 16:43:10 -0500778 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
Ludovic Barreea80aa22018-04-26 18:18:25 +0200779 node);
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200780 goto out_free_domain;
781 }
782
Ludovic Barref9fc1742018-04-26 18:18:28 +0200783 for (i = 0; i < drv_data->bank_nr; i++) {
784 const struct stm32_exti_bank *stm32_bank;
785 struct stm32_exti_chip_data *chip_data;
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100786
Ludovic Barref9fc1742018-04-26 18:18:28 +0200787 stm32_bank = drv_data->exti_banks[i];
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200788 chip_data = stm32_exti_chip_init(host_data, i, node);
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200789
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100790 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
791
Ludovic Barref9fc1742018-04-26 18:18:28 +0200792 gc->reg_base = host_data->base;
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100793 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
Ludovic Barrebe6230f2018-04-26 18:18:26 +0200794 gc->chip_types->chip.irq_ack = stm32_irq_ack;
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100795 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
796 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
797 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200798 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
799 gc->suspend = stm32_irq_suspend;
800 gc->resume = stm32_irq_resume;
801 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
802
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100803 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
Ludovic Barred9e2b19b02018-04-26 18:18:27 +0200804 gc->private = (void *)chip_data;
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100805 }
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200806
807 nr_irqs = of_irq_count(node);
808 for (i = 0; i < nr_irqs; i++) {
809 unsigned int irq = irq_of_parse_and_map(node, i);
810
811 irq_set_handler_data(irq, domain);
812 irq_set_chained_handler(irq, stm32_irq_handler);
813 }
814
815 return 0;
816
817out_free_domain:
818 irq_domain_remove(domain);
819out_unmap:
Ludovic Barref9fc1742018-04-26 18:18:28 +0200820 iounmap(host_data->base);
Ludovic Barref9fc1742018-04-26 18:18:28 +0200821 kfree(host_data->chips_data);
822 kfree(host_data);
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200823 return ret;
824}
825
Ludovic Barre927abfc2018-04-26 18:18:30 +0200826static const struct irq_domain_ops stm32_exti_h_domain_ops = {
827 .alloc = stm32_exti_h_domain_alloc,
828 .free = irq_domain_free_irqs_common,
Loic Pallardy1d47f482019-01-11 18:54:31 +0100829 .xlate = irq_domain_xlate_twocell,
Ludovic Barre927abfc2018-04-26 18:18:30 +0200830};
831
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200832static void stm32_exti_remove_irq(void *data)
Ludovic Barre927abfc2018-04-26 18:18:30 +0200833{
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200834 struct irq_domain *domain = data;
835
836 irq_domain_remove(domain);
837}
838
839static int stm32_exti_remove(struct platform_device *pdev)
840{
841 stm32_exti_h_syscore_deinit();
842 return 0;
843}
844
845static int stm32_exti_probe(struct platform_device *pdev)
846{
847 int ret, i;
848 struct device *dev = &pdev->dev;
849 struct device_node *np = dev->of_node;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200850 struct irq_domain *parent_domain, *domain;
851 struct stm32_exti_host_data *host_data;
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200852 const struct stm32_exti_drv_data *drv_data;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200853
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200854 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
Dan Carpenter40961652018-08-08 15:03:19 +0300855 if (!host_data)
856 return -ENOMEM;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200857
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200858 /* check for optional hwspinlock which may be not available yet */
859 ret = of_hwspin_lock_get_id(np, 0);
860 if (ret == -EPROBE_DEFER)
861 /* hwspinlock framework not yet ready */
862 return ret;
863
864 if (ret >= 0) {
865 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
866 if (!host_data->hwlock) {
867 dev_err(dev, "Failed to request hwspinlock\n");
868 return -EINVAL;
869 }
870 } else if (ret != -ENOENT) {
871 /* note: ENOENT is a valid case (means 'no hwspinlock') */
872 dev_err(dev, "Failed to get hwspinlock\n");
873 return ret;
874 }
875
876 /* initialize host_data */
877 drv_data = of_device_get_match_data(dev);
878 if (!drv_data) {
879 dev_err(dev, "no of match data\n");
880 return -ENODEV;
881 }
882 host_data->drv_data = drv_data;
883
884 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
885 sizeof(*host_data->chips_data),
886 GFP_KERNEL);
887 if (!host_data->chips_data)
888 return -ENOMEM;
889
Cai Huoqingfd9ac232021-09-08 18:57:15 +0800890 host_data->base = devm_platform_ioremap_resource(pdev, 0);
Zhen Leifbb80d52021-05-11 20:54:28 +0800891 if (IS_ERR(host_data->base))
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200892 return PTR_ERR(host_data->base);
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200893
Ludovic Barre927abfc2018-04-26 18:18:30 +0200894 for (i = 0; i < drv_data->bank_nr; i++)
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200895 stm32_exti_chip_init(host_data, i, np);
896
897 parent_domain = irq_find_host(of_irq_find_parent(np));
898 if (!parent_domain) {
899 dev_err(dev, "GIC interrupt-parent not found\n");
900 return -EINVAL;
901 }
Ludovic Barre927abfc2018-04-26 18:18:30 +0200902
903 domain = irq_domain_add_hierarchy(parent_domain, 0,
904 drv_data->bank_nr * IRQS_PER_BANK,
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200905 np, &stm32_exti_h_domain_ops,
Ludovic Barre927abfc2018-04-26 18:18:30 +0200906 host_data);
907
908 if (!domain) {
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200909 dev_err(dev, "Could not register exti domain\n");
910 return -ENOMEM;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200911 }
912
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200913 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
914 if (ret)
915 return ret;
916
917 stm32_exti_h_syscore_init(host_data);
Ludovic Barre73958b32018-04-26 18:18:31 +0200918
Ludovic Barre927abfc2018-04-26 18:18:30 +0200919 return 0;
Ludovic Barre927abfc2018-04-26 18:18:30 +0200920}
921
Fabien Dessennecfbf9e42019-04-17 15:02:56 +0200922/* platform driver only for MP1 */
923static const struct of_device_id stm32_exti_ids[] = {
924 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
925 {},
926};
927MODULE_DEVICE_TABLE(of, stm32_exti_ids);
928
929static struct platform_driver stm32_exti_driver = {
930 .probe = stm32_exti_probe,
931 .remove = stm32_exti_remove,
932 .driver = {
933 .name = "stm32_exti",
934 .of_match_table = stm32_exti_ids,
935 },
936};
937
938static int __init stm32_exti_arch_init(void)
939{
940 return platform_driver_register(&stm32_exti_driver);
941}
942
943static void __exit stm32_exti_arch_exit(void)
944{
945 return platform_driver_unregister(&stm32_exti_driver);
946}
947
948arch_initcall(stm32_exti_arch_init);
949module_exit(stm32_exti_arch_exit);
950
951/* no platform driver for F4 and H7 */
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100952static int __init stm32f4_exti_of_init(struct device_node *np,
953 struct device_node *parent)
954{
Ludovic Barref9fc1742018-04-26 18:18:28 +0200955 return stm32_exti_init(&stm32f4xx_drv_data, np);
Ludovic Barre6dd64ee2017-11-06 18:03:32 +0100956}
957
958IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
Ludovic Barre539c6032017-11-06 18:03:34 +0100959
960static int __init stm32h7_exti_of_init(struct device_node *np,
961 struct device_node *parent)
962{
Ludovic Barref9fc1742018-04-26 18:18:28 +0200963 return stm32_exti_init(&stm32h7xx_drv_data, np);
Ludovic Barre539c6032017-11-06 18:03:34 +0100964}
965
966IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);