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Dan Williams6f231dd2011-07-02 22:56:22 -07001/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * BSD LICENSE
25 *
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
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32 *
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34 * notice, this list of conditions and the following disclaimer.
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37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
Dan Williams0d843662011-05-08 01:56:57 -070056#ifndef _ISCI_REQUEST_H_
Dan Williams6f231dd2011-07-02 22:56:22 -070057#define _ISCI_REQUEST_H_
58
59#include "isci.h"
Dan Williamsce2b3262011-05-08 15:49:15 -070060#include "host.h"
Dan Williamsf1f52e72011-05-10 02:28:45 -070061#include "scu_task_context.h"
Dan Williams6f231dd2011-07-02 22:56:22 -070062
63/**
Dan Williamsba7cb222011-06-27 11:56:41 -070064 * isci_stp_request - extra request infrastructure to handle pio/atapi protocol
65 * @pio_len - number of bytes requested at PIO setup
66 * @status - pio setup ending status value to tell us if we need
Dan Williams5076a1a2011-06-27 14:57:03 -070067 * to wait for another fis or if the transfer is complete. Upon
Dan Williamsba7cb222011-06-27 11:56:41 -070068 * receipt of a d2h fis this will be the status field of that fis.
69 * @sgl - track pio transfer progress as we iterate through the sgl
Dan Williamsba7cb222011-06-27 11:56:41 -070070 */
71struct isci_stp_request {
72 u32 pio_len;
73 u8 status;
Dan Williams5dec6f4e2011-05-10 02:28:49 -070074
Dan Williamsba7cb222011-06-27 11:56:41 -070075 struct isci_stp_pio_sgl {
76 int index;
77 u8 set;
78 u32 offset;
79 } sgl;
Dan Williams5dec6f4e2011-05-10 02:28:49 -070080};
81
Dan Williams5076a1a2011-06-27 14:57:03 -070082struct isci_request {
Dan Williams5076a1a2011-06-27 14:57:03 -070083 #define IREQ_COMPLETE_IN_TARGET 0
84 #define IREQ_TERMINATED 1
85 #define IREQ_TMF 2
86 #define IREQ_ACTIVE 3
Jeff Skirvin726980d2012-03-08 22:41:50 -080087 #define IREQ_PENDING_ABORT 4 /* Set == device was not suspended yet */
88 #define IREQ_TC_ABORT_POSTED 5
Jeff Skirvin14aaa9f2012-03-08 22:41:54 -080089 #define IREQ_ABORT_PATH_ACTIVE 6
Jeff Skirvin621120c2012-03-08 22:42:03 -080090 #define IREQ_NO_AUTO_FREE_TAG 7 /* Set when being explicitly managed */
Dan Williams5076a1a2011-06-27 14:57:03 -070091 unsigned long flags;
92 /* XXX kill ttype and ttype_ptr, allocate full sas_task */
Dan Williams5076a1a2011-06-27 14:57:03 -070093 union ttype_ptr_union {
94 struct sas_task *io_task_ptr; /* When ttype==io_task */
95 struct isci_tmf *tmf_task_ptr; /* When ttype==tmf_task */
96 } ttype_ptr;
97 struct isci_host *isci_host;
Dan Williams5076a1a2011-06-27 14:57:03 -070098 dma_addr_t request_daddr;
99 dma_addr_t zero_scatter_daddr;
100 unsigned int num_sg_entries;
101 /* Note: "io_request_completion" is completed in two different ways
102 * depending on whether this is a TMF or regular request.
103 * - TMF requests are completed in the thread that started them;
104 * - regular requests are completed in the request completion callback
105 * function.
106 * This difference in operation allows the aborter of a TMF request
107 * to be sure that once the TMF request completes, the I/O that the
108 * TMF was aborting is guaranteed to have completed.
109 *
110 * XXX kill io_request_completion
Dan Williamsf1f52e72011-05-10 02:28:45 -0700111 */
Dan Williams5076a1a2011-06-27 14:57:03 -0700112 struct completion *io_request_completion;
Edmund Nadolskie3013702011-06-02 00:10:43 +0000113 struct sci_base_state_machine sm;
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700114 struct isci_host *owning_controller;
Dan Williams78a6f062011-06-30 16:31:37 -0700115 struct isci_remote_device *target_device;
Dan Williamsf1f52e72011-05-10 02:28:45 -0700116 u16 io_tag;
Dan Williamsc79dd802012-02-01 00:44:14 -0800117 enum sas_protocol protocol;
Dan Williams5076a1a2011-06-27 14:57:03 -0700118 u32 scu_status; /* hardware result */
119 u32 sci_status; /* upper layer disposition */
Dan Williamsf1f52e72011-05-10 02:28:45 -0700120 u32 post_context;
Dan Williams312e0c22011-06-28 13:47:09 -0700121 struct scu_task_context *tc;
Dan Williamsf1f52e72011-05-10 02:28:45 -0700122 /* could be larger with sg chaining */
Dan Williams7c78da32011-06-01 16:00:01 -0700123 #define SCU_SGL_SIZE ((SCI_MAX_SCATTER_GATHER_ELEMENTS + 1) / 2)
Dan Williamsf1f52e72011-05-10 02:28:45 -0700124 struct scu_sgl_element_pair sg_table[SCU_SGL_SIZE] __attribute__ ((aligned(32)));
Dan Williams5076a1a2011-06-27 14:57:03 -0700125 /* This field is a pointer to the stored rx frame data. It is used in
Edmund Nadolskie3013702011-06-02 00:10:43 +0000126 * STP internal requests and SMP response frames. If this field is
127 * non-NULL the saved frame must be released on IO request completion.
Dan Williamsf1f52e72011-05-10 02:28:45 -0700128 */
129 u32 saved_rx_frame_index;
130
Dan Williamsf1f52e72011-05-10 02:28:45 -0700131 union {
132 struct {
133 union {
134 struct ssp_cmd_iu cmd;
135 struct ssp_task_iu tmf;
136 };
137 union {
138 struct ssp_response_iu rsp;
139 u8 rsp_buf[SSP_RESP_IU_MAX_SIZE];
140 };
141 } ssp;
Dan Williamsf1f52e72011-05-10 02:28:45 -0700142 struct {
Dan Williamsba7cb222011-06-27 11:56:41 -0700143 struct isci_stp_request req;
Dan Williamsf1f52e72011-05-10 02:28:45 -0700144 struct host_to_dev_fis cmd;
145 struct dev_to_host_fis rsp;
146 } stp;
147 };
Dan Williamsf1f52e72011-05-10 02:28:45 -0700148};
149
Dan Williams5076a1a2011-06-27 14:57:03 -0700150static inline struct isci_request *to_ireq(struct isci_stp_request *stp_req)
Dan Williamsf1f52e72011-05-10 02:28:45 -0700151{
Dan Williams5076a1a2011-06-27 14:57:03 -0700152 struct isci_request *ireq;
Dan Williamsf1f52e72011-05-10 02:28:45 -0700153
Dan Williams5076a1a2011-06-27 14:57:03 -0700154 ireq = container_of(stp_req, typeof(*ireq), stp.req);
Dan Williams67ea8382011-05-08 11:47:15 -0700155 return ireq;
156}
157
Dan Williams6f231dd2011-07-02 22:56:22 -0700158/**
Dan Williamsd7a0ccd2012-02-10 01:18:44 -0800159 * enum sci_base_request_states - request state machine states
Dan Williamsf1f52e72011-05-10 02:28:45 -0700160 *
Dan Williamsd7a0ccd2012-02-10 01:18:44 -0800161 * @SCI_REQ_INIT: Simply the initial state for the base request state machine.
Dan Williamsf1f52e72011-05-10 02:28:45 -0700162 *
Dan Williamsd7a0ccd2012-02-10 01:18:44 -0800163 * @SCI_REQ_CONSTRUCTED: This state indicates that the request has been
164 * constructed. This state is entered from the INITIAL state.
165 *
166 * @SCI_REQ_STARTED: This state indicates that the request has been started.
167 * This state is entered from the CONSTRUCTED state.
168 *
169 * @SCI_REQ_STP_UDMA_WAIT_TC_COMP:
170 * @SCI_REQ_STP_UDMA_WAIT_D2H:
171 * @SCI_REQ_STP_NON_DATA_WAIT_H2D:
172 * @SCI_REQ_STP_NON_DATA_WAIT_D2H:
173 *
174 * @SCI_REQ_STP_PIO_WAIT_H2D: While in this state the IO request object is
175 * waiting for the TC completion notification for the H2D Register FIS
176 *
177 * @SCI_REQ_STP_PIO_WAIT_FRAME: While in this state the IO request object is
178 * waiting for either a PIO Setup FIS or a D2H register FIS. The type of frame
179 * received is based on the result of the prior frame and line conditions.
180 *
181 * @SCI_REQ_STP_PIO_DATA_IN: While in this state the IO request object is
182 * waiting for a DATA frame from the device.
183 *
184 * @SCI_REQ_STP_PIO_DATA_OUT: While in this state the IO request object is
185 * waiting to transmit the next data frame to the device.
186 *
187 * @SCI_REQ_ATAPI_WAIT_H2D: While in this state the IO request object is
188 * waiting for the TC completion notification for the H2D Register FIS
189 *
190 * @SCI_REQ_ATAPI_WAIT_PIO_SETUP: While in this state the IO request object is
191 * waiting for either a PIO Setup.
192 *
193 * @SCI_REQ_ATAPI_WAIT_D2H: The non-data IO transit to this state in this state
194 * after receiving TC completion. While in this state IO request object is
195 * waiting for D2H status frame as UF.
196 *
197 * @SCI_REQ_ATAPI_WAIT_TC_COMP: When transmitting raw frames hardware reports
198 * task context completion after every frame submission, so in the
199 * non-accelerated case we need to expect the completion for the "cdb" frame.
200 *
201 * @SCI_REQ_TASK_WAIT_TC_COMP: The AWAIT_TC_COMPLETION sub-state indicates that
202 * the started raw task management request is waiting for the transmission of
203 * the initial frame (i.e. command, task, etc.).
204 *
205 * @SCI_REQ_TASK_WAIT_TC_RESP: This sub-state indicates that the started task
206 * management request is waiting for the reception of an unsolicited frame
207 * (i.e. response IU).
208 *
209 * @SCI_REQ_SMP_WAIT_RESP: This sub-state indicates that the started task
210 * management request is waiting for the reception of an unsolicited frame
211 * (i.e. response IU).
212 *
213 * @SCI_REQ_SMP_WAIT_TC_COMP: The AWAIT_TC_COMPLETION sub-state indicates that
214 * the started SMP request is waiting for the transmission of the initial frame
215 * (i.e. command, task, etc.).
216 *
217 * @SCI_REQ_COMPLETED: This state indicates that the request has completed.
218 * This state is entered from the STARTED state. This state is entered from the
219 * ABORTING state.
220 *
221 * @SCI_REQ_ABORTING: This state indicates that the request is in the process
222 * of being terminated/aborted. This state is entered from the CONSTRUCTED
223 * state. This state is entered from the STARTED state.
224 *
225 * @SCI_REQ_FINAL: Simply the final state for the base request state machine.
Dan Williamsf1f52e72011-05-10 02:28:45 -0700226 */
Dan Williamsd7a0ccd2012-02-10 01:18:44 -0800227#define REQUEST_STATES {\
228 C(REQ_INIT),\
229 C(REQ_CONSTRUCTED),\
230 C(REQ_STARTED),\
231 C(REQ_STP_UDMA_WAIT_TC_COMP),\
232 C(REQ_STP_UDMA_WAIT_D2H),\
233 C(REQ_STP_NON_DATA_WAIT_H2D),\
234 C(REQ_STP_NON_DATA_WAIT_D2H),\
235 C(REQ_STP_PIO_WAIT_H2D),\
236 C(REQ_STP_PIO_WAIT_FRAME),\
237 C(REQ_STP_PIO_DATA_IN),\
238 C(REQ_STP_PIO_DATA_OUT),\
239 C(REQ_ATAPI_WAIT_H2D),\
240 C(REQ_ATAPI_WAIT_PIO_SETUP),\
241 C(REQ_ATAPI_WAIT_D2H),\
242 C(REQ_ATAPI_WAIT_TC_COMP),\
243 C(REQ_TASK_WAIT_TC_COMP),\
244 C(REQ_TASK_WAIT_TC_RESP),\
245 C(REQ_SMP_WAIT_RESP),\
246 C(REQ_SMP_WAIT_TC_COMP),\
247 C(REQ_COMPLETED),\
248 C(REQ_ABORTING),\
249 C(REQ_FINAL),\
250 }
251#undef C
252#define C(a) SCI_##a
253enum sci_base_request_states REQUEST_STATES;
254#undef C
255const char *req_state_name(enum sci_base_request_states state);
Dan Williamsf1f52e72011-05-10 02:28:45 -0700256
Dan Williams89a73012011-06-30 19:14:33 -0700257enum sci_status sci_request_start(struct isci_request *ireq);
258enum sci_status sci_io_request_terminate(struct isci_request *ireq);
Edmund Nadolskie3013702011-06-02 00:10:43 +0000259enum sci_status
Dan Williams89a73012011-06-30 19:14:33 -0700260sci_io_request_event_handler(struct isci_request *ireq,
Edmund Nadolskie3013702011-06-02 00:10:43 +0000261 u32 event_code);
262enum sci_status
Dan Williams89a73012011-06-30 19:14:33 -0700263sci_io_request_frame_handler(struct isci_request *ireq,
Edmund Nadolskie3013702011-06-02 00:10:43 +0000264 u32 frame_index);
265enum sci_status
Dan Williams89a73012011-06-30 19:14:33 -0700266sci_task_request_terminate(struct isci_request *ireq);
Edmund Nadolskie3013702011-06-02 00:10:43 +0000267extern enum sci_status
Dan Williams89a73012011-06-30 19:14:33 -0700268sci_request_complete(struct isci_request *ireq);
Edmund Nadolskie3013702011-06-02 00:10:43 +0000269extern enum sci_status
Dan Williams89a73012011-06-30 19:14:33 -0700270sci_io_request_tc_completion(struct isci_request *ireq, u32 code);
Dan Williamsf1f52e72011-05-10 02:28:45 -0700271
Dan Williamsf1f52e72011-05-10 02:28:45 -0700272/* XXX open code in caller */
Edmund Nadolskie3013702011-06-02 00:10:43 +0000273static inline dma_addr_t
Dan Williams89a73012011-06-30 19:14:33 -0700274sci_io_request_get_dma_addr(struct isci_request *ireq, void *virt_addr)
Dan Williamsf1f52e72011-05-10 02:28:45 -0700275{
Dan Williamsf1f52e72011-05-10 02:28:45 -0700276
277 char *requested_addr = (char *)virt_addr;
278 char *base_addr = (char *)ireq;
279
280 BUG_ON(requested_addr < base_addr);
281 BUG_ON((requested_addr - base_addr) >= sizeof(*ireq));
282
283 return ireq->request_daddr + (requested_addr - base_addr);
284}
285
Edmund Nadolskie3013702011-06-02 00:10:43 +0000286#define isci_request_access_task(req) ((req)->ttype_ptr.io_task_ptr)
Dan Williams6f231dd2011-07-02 22:56:22 -0700287
Edmund Nadolskie3013702011-06-02 00:10:43 +0000288#define isci_request_access_tmf(req) ((req)->ttype_ptr.tmf_task_ptr)
Dan Williams6f231dd2011-07-02 22:56:22 -0700289
Dan Williamsdb056252011-06-17 14:18:39 -0700290struct isci_request *isci_tmf_request_from_tag(struct isci_host *ihost,
291 struct isci_tmf *isci_tmf,
292 u16 tag);
Dan Williams209fae12011-06-13 17:39:44 -0700293int isci_request_execute(struct isci_host *ihost, struct isci_remote_device *idev,
Dan Williamsdb056252011-06-17 14:18:39 -0700294 struct sas_task *task, u16 tag);
Edmund Nadolskie3013702011-06-02 00:10:43 +0000295enum sci_status
Dan Williams89a73012011-06-30 19:14:33 -0700296sci_task_request_construct(struct isci_host *ihost,
Dan Williams78a6f062011-06-30 16:31:37 -0700297 struct isci_remote_device *idev,
Edmund Nadolskie3013702011-06-02 00:10:43 +0000298 u16 io_tag,
Dan Williams5076a1a2011-06-27 14:57:03 -0700299 struct isci_request *ireq);
Dan Williams43a5ab152011-12-08 23:20:44 -0800300enum sci_status sci_task_request_construct_ssp(struct isci_request *ireq);
Dan Williams89a73012011-06-30 19:14:33 -0700301void sci_smp_request_copy_response(struct isci_request *ireq);
Jeff Skirvin9274f452011-06-23 17:09:02 -0700302
303static inline int isci_task_is_ncq_recovery(struct sas_task *task)
304{
305 return (sas_protocol_ata(task->task_proto) &&
James Bottomleya5ec7f862011-07-03 14:14:45 -0500306 task->ata_task.fis.command == ATA_CMD_READ_LOG_EXT &&
307 task->ata_task.fis.lbal == ATA_LOG_SATA_NCQ);
Jeff Skirvin9274f452011-06-23 17:09:02 -0700308
309}
Dan Williams6f231dd2011-07-02 22:56:22 -0700310#endif /* !defined(_ISCI_REQUEST_H_) */