| Wang Dongsheng | d64716c | 2015-10-26 14:44:12 +0800 | [diff] [blame^] | 1 | * Run Control and Power Management |
| 2 | ------------------------------------------- |
| 3 | The RCPM performs all device-level tasks associated with device run control |
| 4 | and power management. |
| 5 | |
| 6 | Required properites: |
| 7 | - reg : Offset and length of the register set of the RCPM block. |
| 8 | - fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the |
| 9 | fsl,rcpm-wakeup property. |
| 10 | - compatible : Must contain a chip-specific RCPM block compatible string |
| 11 | and (if applicable) may contain a chassis-version RCPM compatible |
| 12 | string. Chip-specific strings are of the form "fsl,<chip>-rcpm", |
| 13 | such as: |
| 14 | * "fsl,p2041-rcpm" |
| 15 | * "fsl,p5020-rcpm" |
| 16 | * "fsl,t4240-rcpm" |
| 17 | |
| 18 | Chassis-version strings are of the form "fsl,qoriq-rcpm-<version>", |
| 19 | such as: |
| 20 | * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm |
| 21 | * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm |
| 22 | * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm |
| 23 | |
| 24 | All references to "1.0" and "2.0" refer to the QorIQ chassis version to |
| 25 | which the chip complies. |
| 26 | Chassis Version Example Chips |
| 27 | --------------- ------------------------------- |
| 28 | 1.0 p4080, p5020, p5040, p2041, p3041 |
| 29 | 2.0 t4240, b4860, b4420 |
| 30 | 2.1 t1040, ls1021 |
| 31 | |
| 32 | Example: |
| 33 | The RCPM node for T4240: |
| 34 | rcpm: global-utilities@e2000 { |
| 35 | compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; |
| 36 | reg = <0xe2000 0x1000>; |
| 37 | fsl,#rcpm-wakeup-cells = <2>; |
| 38 | }; |
| 39 | |
| 40 | * Freescale RCPM Wakeup Source Device Tree Bindings |
| 41 | ------------------------------------------- |
| 42 | Required fsl,rcpm-wakeup property should be added to a device node if the device |
| 43 | can be used as a wakeup source. |
| 44 | |
| 45 | - fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR |
| 46 | register cells. The number of IPPDEXPCR register cells is defined in |
| 47 | "fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is |
| 48 | the bit mask that should be set in IPPDEXPCR0, and the second register |
| 49 | cell is for IPPDEXPCR1, and so on. |
| 50 | |
| 51 | Note: IPPDEXPCR(IP Powerdown Exception Control Register) provides a |
| 52 | mechanism for keeping certain blocks awake during STANDBY and MEM, in |
| 53 | order to use them as wake-up sources. |
| 54 | |
| 55 | Example: |
| 56 | lpuart0: serial@2950000 { |
| 57 | compatible = "fsl,ls1021a-lpuart"; |
| 58 | reg = <0x0 0x2950000 0x0 0x1000>; |
| 59 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| 60 | clocks = <&sysclk>; |
| 61 | clock-names = "ipg"; |
| 62 | fsl,rcpm-wakeup = <&rcpm 0x0 0x40000000>; |
| 63 | }; |
