blob: 64200c78e90dc7fce4112abc0336c0c79b757bce [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Ben Dooks0d1bb412009-06-14 13:52:37 +01002/* linux/drivers/mmc/host/sdhci-s3c.c
3 *
4 * Copyright 2008 Openmoko Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * SDHCI (HSMMC) support for Samsung SoC
Ben Dooks0d1bb412009-06-14 13:52:37 +010010 */
11
Paul Osmialowski017210d2015-02-04 10:16:59 +010012#include <linux/spinlock.h>
Ben Dooks0d1bb412009-06-14 13:52:37 +010013#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
Arnd Bergmanncc014f32013-03-04 18:28:21 +010016#include <linux/platform_data/mmc-sdhci-s3c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090017#include <linux/slab.h>
Ben Dooks0d1bb412009-06-14 13:52:37 +010018#include <linux/clk.h>
19#include <linux/io.h>
Marek Szyprowski17866e12010-08-10 18:01:58 -070020#include <linux/gpio.h>
Mark Brown55156d22011-07-29 15:35:00 +010021#include <linux/module.h>
Mark Brownd5e9c022012-03-03 00:46:41 +000022#include <linux/of.h>
23#include <linux/of_gpio.h>
24#include <linux/pm.h>
Mark Brown9f4e8152012-03-31 23:31:55 -040025#include <linux/pm_runtime.h>
Ben Dooks0d1bb412009-06-14 13:52:37 +010026
27#include <linux/mmc/host.h>
28
Ben Dooks0d1bb412009-06-14 13:52:37 +010029#include "sdhci.h"
30
31#define MAX_BUS_CLK (4)
32
Jaehoon Chung57f83242017-01-24 18:27:27 +090033#define S3C_SDHCI_CONTROL2 (0x80)
34#define S3C_SDHCI_CONTROL3 (0x84)
35#define S3C64XX_SDHCI_CONTROL4 (0x8C)
36
Jaehoon Chunge64aae82017-01-24 18:27:28 +090037#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
38#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
39#define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
40#define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
Jaehoon Chung57f83242017-01-24 18:27:27 +090041
42#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
43#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
44#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
45
46#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
47#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
48#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
49
Jaehoon Chunge64aae82017-01-24 18:27:28 +090050#define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
51#define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
52#define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
53#define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
54#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
Jaehoon Chung57f83242017-01-24 18:27:27 +090055
56#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
57#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
58#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
59#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
60#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
61#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
62
Jaehoon Chunge64aae82017-01-24 18:27:28 +090063#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
64#define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
65#define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
66
Jaehoon Chung57f83242017-01-24 18:27:27 +090067#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
68#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
Jaehoon Chunge64aae82017-01-24 18:27:28 +090069#define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
70#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
71#define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
Jaehoon Chung57f83242017-01-24 18:27:27 +090072
Jaehoon Chunge64aae82017-01-24 18:27:28 +090073#define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
74#define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
75#define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
76#define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
Jaehoon Chung57f83242017-01-24 18:27:27 +090077
78#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
79#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
80#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
81
82#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
83#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
84#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
85
86#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
87#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
88#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
89
90#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
91#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
92#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
93
94#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
95#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
96#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
97#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
98#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
99#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
100
101#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
102
Ben Dooks0d1bb412009-06-14 13:52:37 +0100103/**
104 * struct sdhci_s3c - S3C SDHCI instance
105 * @host: The SDHCI host created
106 * @pdev: The platform device we where created from.
107 * @ioarea: The resource created when we claimed the IO area.
108 * @pdata: The platform data for this controller.
109 * @cur_clk: The index of the current bus clock.
110 * @clk_io: The clock for the internal bus interface.
111 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
112 */
113struct sdhci_s3c {
114 struct sdhci_host *host;
115 struct platform_device *pdev;
116 struct resource *ioarea;
117 struct s3c_sdhci_platdata *pdata;
Tomasz Figa3ac147f2014-01-11 22:39:05 +0100118 int cur_clk;
Marek Szyprowski17866e12010-08-10 18:01:58 -0700119 int ext_cd_irq;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100120
121 struct clk *clk_io;
122 struct clk *clk_bus[MAX_BUS_CLK];
Tomasz Figa6eb28bd2014-01-11 22:39:02 +0100123 unsigned long clk_rates[MAX_BUS_CLK];
Russell King17710592014-04-25 12:58:55 +0100124
125 bool no_divider;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100126};
127
Thomas Abraham3119936a2012-02-16 22:23:58 +0900128/**
129 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
130 * @sdhci_quirks: sdhci host specific quirks.
131 *
132 * Specifies platform specific configuration of sdhci controller.
133 * Note: A structure for driver specific platform data is used for future
134 * expansion of its usage.
135 */
136struct sdhci_s3c_drv_data {
137 unsigned int sdhci_quirks;
Russell King17710592014-04-25 12:58:55 +0100138 bool no_divider;
Thomas Abraham3119936a2012-02-16 22:23:58 +0900139};
140
Ben Dooks0d1bb412009-06-14 13:52:37 +0100141static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
142{
143 return sdhci_priv(host);
144}
145
146/**
Ben Dooks0d1bb412009-06-14 13:52:37 +0100147 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
148 * @host: The SDHCI host instance.
149 *
150 * Callback to return the maximum clock rate acheivable by the controller.
151*/
152static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
153{
154 struct sdhci_s3c *ourhost = to_s3c(host);
Tomasz Figa222a13c2014-01-11 22:39:04 +0100155 unsigned long rate, max = 0;
156 int src;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100157
Tomasz Figa222a13c2014-01-11 22:39:04 +0100158 for (src = 0; src < MAX_BUS_CLK; src++) {
159 rate = ourhost->clk_rates[src];
Ben Dooks0d1bb412009-06-14 13:52:37 +0100160 if (rate > max)
161 max = rate;
162 }
163
164 return max;
165}
166
Ben Dooks0d1bb412009-06-14 13:52:37 +0100167/**
168 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
169 * @ourhost: Our SDHCI instance.
170 * @src: The source clock index.
171 * @wanted: The clock frequency wanted.
172 */
173static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
174 unsigned int src,
175 unsigned int wanted)
176{
177 unsigned long rate;
178 struct clk *clksrc = ourhost->clk_bus[src];
Tomasz Figa8880a4a2014-01-11 22:39:01 +0100179 int shift;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100180
Tomasz Figa8f4b78d2014-01-11 22:39:03 +0100181 if (IS_ERR(clksrc))
Ben Dooks0d1bb412009-06-14 13:52:37 +0100182 return UINT_MAX;
183
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900184 /*
Thomas Abraham3119936a2012-02-16 22:23:58 +0900185 * If controller uses a non-standard clock division, find the best clock
186 * speed possible with selected clock source and skip the division.
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900187 */
Russell King17710592014-04-25 12:58:55 +0100188 if (ourhost->no_divider) {
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900189 rate = clk_round_rate(clksrc, wanted);
190 return wanted - rate;
191 }
192
Tomasz Figa6eb28bd2014-01-11 22:39:02 +0100193 rate = ourhost->clk_rates[src];
Ben Dooks0d1bb412009-06-14 13:52:37 +0100194
Tomasz Figa22003002014-01-11 22:39:06 +0100195 for (shift = 0; shift <= 8; ++shift) {
Tomasz Figa8880a4a2014-01-11 22:39:01 +0100196 if ((rate >> shift) <= wanted)
Ben Dooks0d1bb412009-06-14 13:52:37 +0100197 break;
198 }
199
Tomasz Figa22003002014-01-11 22:39:06 +0100200 if (shift > 8) {
201 dev_dbg(&ourhost->pdev->dev,
202 "clk %d: rate %ld, min rate %lu > wanted %u\n",
203 src, rate, rate / 256, wanted);
204 return UINT_MAX;
205 }
206
Ben Dooks0d1bb412009-06-14 13:52:37 +0100207 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
Tomasz Figa8880a4a2014-01-11 22:39:01 +0100208 src, rate, wanted, rate >> shift);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100209
Tomasz Figa8880a4a2014-01-11 22:39:01 +0100210 return wanted - (rate >> shift);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100211}
212
213/**
214 * sdhci_s3c_set_clock - callback on clock change
215 * @host: The SDHCI host being changed
216 * @clock: The clock rate being requested.
217 *
218 * When the card's clock is going to be changed, look at the new frequency
219 * and find the best clock source to go with it.
220*/
221static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
222{
223 struct sdhci_s3c *ourhost = to_s3c(host);
224 unsigned int best = UINT_MAX;
225 unsigned int delta;
226 int best_src = 0;
227 int src;
228 u32 ctrl;
229
Russell King1650d0c2014-04-25 12:58:50 +0100230 host->mmc->actual_clock = 0;
231
Ben Dooks0d1bb412009-06-14 13:52:37 +0100232 /* don't bother if the clock is going off. */
Russell King17710592014-04-25 12:58:55 +0100233 if (clock == 0) {
234 sdhci_set_clock(host, clock);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100235 return;
Russell King17710592014-04-25 12:58:55 +0100236 }
Ben Dooks0d1bb412009-06-14 13:52:37 +0100237
238 for (src = 0; src < MAX_BUS_CLK; src++) {
239 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
240 if (delta < best) {
241 best = delta;
242 best_src = src;
243 }
244 }
245
246 dev_dbg(&ourhost->pdev->dev,
247 "selected source %d, clock %d, delta %d\n",
248 best_src, clock, best);
249
250 /* select the new clock source */
Ben Dooks0d1bb412009-06-14 13:52:37 +0100251 if (ourhost->cur_clk != best_src) {
252 struct clk *clk = ourhost->clk_bus[best_src];
253
Thomas Abraham0f310a052012-10-03 08:35:43 +0900254 clk_prepare_enable(clk);
Tomasz Figa3ac147f2014-01-11 22:39:05 +0100255 if (ourhost->cur_clk >= 0)
256 clk_disable_unprepare(
257 ourhost->clk_bus[ourhost->cur_clk]);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100258
259 ourhost->cur_clk = best_src;
Tomasz Figa6eb28bd2014-01-11 22:39:02 +0100260 host->max_clk = ourhost->clk_rates[best_src];
Ben Dooks0d1bb412009-06-14 13:52:37 +0100261 }
262
Tomasz Figa3ac147f2014-01-11 22:39:05 +0100263 /* turn clock off to card before changing clock source */
264 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
265
266 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
267 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
268 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
269 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
270
Thomas Abraham6fe47172011-09-14 12:39:17 +0530271 /* reprogram default hardware configuration */
272 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
273 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100274
Thomas Abraham6fe47172011-09-14 12:39:17 +0530275 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
276 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
277 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
278 S3C_SDHCI_CTRL2_ENFBCLKRX |
279 S3C_SDHCI_CTRL2_DFCNT_NONE |
280 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
281 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100282
Thomas Abraham6fe47172011-09-14 12:39:17 +0530283 /* reconfigure the controller for new clock rate */
284 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
285 if (clock < 25 * 1000000)
286 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
287 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
Russell King17710592014-04-25 12:58:55 +0100288
289 sdhci_set_clock(host, clock);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100290}
291
Marek Szyprowskice5f0362010-08-10 18:01:56 -0700292/**
293 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
294 * @host: The SDHCI host being queried
295 *
296 * To init mmc host properly a minimal clock value is needed. For high system
297 * bus clock's values the standard formula gives values out of allowed range.
298 * The clock still can be set to lower values, if clock source other then
299 * system bus is selected.
300*/
301static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
302{
303 struct sdhci_s3c *ourhost = to_s3c(host);
Tomasz Figa222a13c2014-01-11 22:39:04 +0100304 unsigned long rate, min = ULONG_MAX;
Marek Szyprowskice5f0362010-08-10 18:01:56 -0700305 int src;
306
307 for (src = 0; src < MAX_BUS_CLK; src++) {
Tomasz Figa222a13c2014-01-11 22:39:04 +0100308 rate = ourhost->clk_rates[src] / 256;
309 if (!rate)
Marek Szyprowskice5f0362010-08-10 18:01:56 -0700310 continue;
Tomasz Figa222a13c2014-01-11 22:39:04 +0100311 if (rate < min)
312 min = rate;
Marek Szyprowskice5f0362010-08-10 18:01:56 -0700313 }
Tomasz Figa222a13c2014-01-11 22:39:04 +0100314
Marek Szyprowskice5f0362010-08-10 18:01:56 -0700315 return min;
316}
317
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900318/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
319static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
320{
321 struct sdhci_s3c *ourhost = to_s3c(host);
Tomasz Figa222a13c2014-01-11 22:39:04 +0100322 unsigned long rate, max = 0;
323 int src;
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900324
Tomasz Figa222a13c2014-01-11 22:39:04 +0100325 for (src = 0; src < MAX_BUS_CLK; src++) {
326 struct clk *clk;
327
328 clk = ourhost->clk_bus[src];
329 if (IS_ERR(clk))
330 continue;
331
332 rate = clk_round_rate(clk, ULONG_MAX);
333 if (rate > max)
334 max = rate;
335 }
336
337 return max;
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900338}
339
340/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
341static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
342{
343 struct sdhci_s3c *ourhost = to_s3c(host);
Tomasz Figa222a13c2014-01-11 22:39:04 +0100344 unsigned long rate, min = ULONG_MAX;
345 int src;
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900346
Tomasz Figa222a13c2014-01-11 22:39:04 +0100347 for (src = 0; src < MAX_BUS_CLK; src++) {
348 struct clk *clk;
349
350 clk = ourhost->clk_bus[src];
351 if (IS_ERR(clk))
352 continue;
353
354 rate = clk_round_rate(clk, 0);
355 if (rate < min)
356 min = rate;
357 }
358
359 return min;
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900360}
361
362/* sdhci_cmu_set_clock - callback on clock change.*/
363static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
364{
365 struct sdhci_s3c *ourhost = to_s3c(host);
Jingoo Han2ad0b242012-08-29 14:35:06 +0900366 struct device *dev = &ourhost->pdev->dev;
Thomas Abraham3119936a2012-02-16 22:23:58 +0900367 unsigned long timeout;
368 u16 clk = 0;
Mark Browncd0cfdd2014-11-04 12:26:42 +0000369 int ret;
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900370
Russell King1650d0c2014-04-25 12:58:50 +0100371 host->mmc->actual_clock = 0;
372
Jaehoon Chung7ef2a5e2013-08-02 23:08:58 +0900373 /* If the clock is going off, set to 0 at clock control register */
374 if (clock == 0) {
375 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900376 return;
Jaehoon Chung7ef2a5e2013-08-02 23:08:58 +0900377 }
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900378
379 sdhci_s3c_set_clock(host, clock);
380
Paul Osmialowski017210d2015-02-04 10:16:59 +0100381 /* Reset SD Clock Enable */
382 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
383 clk &= ~SDHCI_CLOCK_CARD_EN;
384 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
385
Mark Browncd0cfdd2014-11-04 12:26:42 +0000386 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
387 if (ret != 0) {
388 dev_err(dev, "%s: failed to set clock rate %uHz\n",
389 mmc_hostname(host->mmc), clock);
390 return;
391 }
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900392
Thomas Abraham3119936a2012-02-16 22:23:58 +0900393 clk = SDHCI_CLOCK_INT_EN;
394 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
395
396 /* Wait max 20 ms */
397 timeout = 20;
398 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
399 & SDHCI_CLOCK_INT_STABLE)) {
400 if (timeout == 0) {
Jingoo Han2ad0b242012-08-29 14:35:06 +0900401 dev_err(dev, "%s: Internal clock never stabilised.\n",
402 mmc_hostname(host->mmc));
Thomas Abraham3119936a2012-02-16 22:23:58 +0900403 return;
404 }
405 timeout--;
406 mdelay(1);
407 }
408
409 clk |= SDHCI_CLOCK_CARD_EN;
410 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900411}
412
Ben Dooks0d1bb412009-06-14 13:52:37 +0100413static struct sdhci_ops sdhci_s3c_ops = {
414 .get_max_clock = sdhci_s3c_get_max_clk,
Ben Dooks0d1bb412009-06-14 13:52:37 +0100415 .set_clock = sdhci_s3c_set_clock,
Marek Szyprowskice5f0362010-08-10 18:01:56 -0700416 .get_min_clock = sdhci_s3c_get_min_clock,
Michał Mirosław5b7f5ea2017-08-14 22:00:26 +0200417 .set_bus_width = sdhci_set_bus_width,
Russell King03231f92014-04-25 12:57:12 +0100418 .reset = sdhci_reset,
Russell King96d7b782014-04-25 12:59:26 +0100419 .set_uhs_signaling = sdhci_set_uhs_signaling,
Ben Dooks0d1bb412009-06-14 13:52:37 +0100420};
421
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000422#ifdef CONFIG_OF
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500423static int sdhci_s3c_parse_dt(struct device *dev,
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000424 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
425{
426 struct device_node *node = dev->of_node;
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000427 u32 max_width;
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000428
429 /* if the bus-width property is not specified, assume width as 1 */
430 if (of_property_read_u32(node, "bus-width", &max_width))
431 max_width = 1;
432 pdata->max_width = max_width;
433
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000434 /* get the card detection method */
Tushar Beheraab5023e2012-11-20 09:41:53 +0530435 if (of_get_property(node, "broken-cd", NULL)) {
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000436 pdata->cd_type = S3C_SDHCI_CD_NONE;
Thomas Abrahame19499a2013-03-06 17:06:16 +0530437 return 0;
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000438 }
439
Tushar Beheraab5023e2012-11-20 09:41:53 +0530440 if (of_get_property(node, "non-removable", NULL)) {
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000441 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
Thomas Abrahame19499a2013-03-06 17:06:16 +0530442 return 0;
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000443 }
444
Jaehoon Chung11bc9382014-05-26 13:58:28 +0900445 if (of_get_named_gpio(node, "cd-gpios", 0))
Thomas Abrahame19499a2013-03-06 17:06:16 +0530446 return 0;
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000447
Tomasz Figab96efcc2012-11-16 15:28:17 +0100448 /* assuming internal card detect that will be configured by pinctrl */
449 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000450 return 0;
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000451}
452#else
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500453static int sdhci_s3c_parse_dt(struct device *dev,
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000454 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
455{
456 return -EINVAL;
457}
458#endif
459
460static const struct of_device_id sdhci_s3c_dt_match[];
461
Thomas Abraham3119936a2012-02-16 22:23:58 +0900462static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
463 struct platform_device *pdev)
464{
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000465#ifdef CONFIG_OF
466 if (pdev->dev.of_node) {
467 const struct of_device_id *match;
468 match = of_match_node(sdhci_s3c_dt_match, pdev->dev.of_node);
469 return (struct sdhci_s3c_drv_data *)match->data;
470 }
471#endif
Thomas Abraham3119936a2012-02-16 22:23:58 +0900472 return (struct sdhci_s3c_drv_data *)
473 platform_get_device_id(pdev)->driver_data;
474}
475
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500476static int sdhci_s3c_probe(struct platform_device *pdev)
Ben Dooks0d1bb412009-06-14 13:52:37 +0100477{
Thomas Abraham1d4dc332012-02-16 22:23:59 +0900478 struct s3c_sdhci_platdata *pdata;
Thomas Abraham3119936a2012-02-16 22:23:58 +0900479 struct sdhci_s3c_drv_data *drv_data;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100480 struct device *dev = &pdev->dev;
481 struct sdhci_host *host;
482 struct sdhci_s3c *sc;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100483 int ret, irq, ptr, clks;
484
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000485 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
Ben Dooks0d1bb412009-06-14 13:52:37 +0100486 dev_err(dev, "no device data specified\n");
487 return -ENOENT;
488 }
489
490 irq = platform_get_irq(pdev, 0);
Stephen Boyd9a7957d2019-07-30 11:15:29 -0700491 if (irq < 0)
Ben Dooks0d1bb412009-06-14 13:52:37 +0100492 return irq;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100493
Ben Dooks0d1bb412009-06-14 13:52:37 +0100494 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
495 if (IS_ERR(host)) {
496 dev_err(dev, "sdhci_alloc_host() failed\n");
497 return PTR_ERR(host);
498 }
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000499 sc = sdhci_priv(host);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100500
Thomas Abraham1d4dc332012-02-16 22:23:59 +0900501 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
502 if (!pdata) {
503 ret = -ENOMEM;
Tomasz Figab1b8fea2012-11-25 15:40:44 -0500504 goto err_pdata_io_clk;
Thomas Abraham1d4dc332012-02-16 22:23:59 +0900505 }
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000506
507 if (pdev->dev.of_node) {
508 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
509 if (ret)
Tomasz Figab1b8fea2012-11-25 15:40:44 -0500510 goto err_pdata_io_clk;
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000511 } else {
512 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000513 }
Thomas Abraham1d4dc332012-02-16 22:23:59 +0900514
Thomas Abraham3119936a2012-02-16 22:23:58 +0900515 drv_data = sdhci_s3c_get_driver_data(pdev);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100516
517 sc->host = host;
518 sc->pdev = pdev;
519 sc->pdata = pdata;
Tomasz Figa3ac147f2014-01-11 22:39:05 +0100520 sc->cur_clk = -1;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100521
522 platform_set_drvdata(pdev, host);
523
Jingoo Han3aaf7ba2013-02-12 12:24:39 +0900524 sc->clk_io = devm_clk_get(dev, "hsmmc");
Ben Dooks0d1bb412009-06-14 13:52:37 +0100525 if (IS_ERR(sc->clk_io)) {
526 dev_err(dev, "failed to get io clock\n");
527 ret = PTR_ERR(sc->clk_io);
Tomasz Figab1b8fea2012-11-25 15:40:44 -0500528 goto err_pdata_io_clk;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100529 }
530
531 /* enable the local io clock and keep it running for the moment. */
Thomas Abraham0f310a052012-10-03 08:35:43 +0900532 clk_prepare_enable(sc->clk_io);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100533
534 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
Rajeshwari Shinde4346b6d2011-11-03 10:52:58 +0900535 char name[14];
Ben Dooks0d1bb412009-06-14 13:52:37 +0100536
Rajeshwari Shinde4346b6d2011-11-03 10:52:58 +0900537 snprintf(name, 14, "mmc_busclk.%d", ptr);
Tomasz Figa8f4b78d2014-01-11 22:39:03 +0100538 sc->clk_bus[ptr] = devm_clk_get(dev, name);
539 if (IS_ERR(sc->clk_bus[ptr]))
Ben Dooks0d1bb412009-06-14 13:52:37 +0100540 continue;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100541
542 clks++;
Tomasz Figa6eb28bd2014-01-11 22:39:02 +0100543 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
544
Ben Dooks0d1bb412009-06-14 13:52:37 +0100545 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
Tomasz Figa6eb28bd2014-01-11 22:39:02 +0100546 ptr, name, sc->clk_rates[ptr]);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100547 }
548
549 if (clks == 0) {
550 dev_err(dev, "failed to find any bus clocks\n");
551 ret = -ENOENT;
552 goto err_no_busclks;
553 }
554
Yangtao Li09938ce2019-12-15 17:51:11 +0000555 host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
Thierry Redinga3e2cd72013-01-21 11:09:11 +0100556 if (IS_ERR(host->ioaddr)) {
557 ret = PTR_ERR(host->ioaddr);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100558 goto err_req_regs;
559 }
560
561 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
562 if (pdata->cfg_gpio)
563 pdata->cfg_gpio(pdev, pdata->max_width);
564
565 host->hw_name = "samsung-hsmmc";
566 host->ops = &sdhci_s3c_ops;
567 host->quirks = 0;
Jaehoon Chung285e2442013-08-02 23:09:00 +0900568 host->quirks2 = 0;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100569 host->irq = irq;
570
571 /* Setup quirks for the controller */
Thomas Abrahamb2e75ef2010-05-26 14:42:05 -0700572 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
Marek Szyprowskia1d56462010-08-10 18:01:57 -0700573 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
Russell King17710592014-04-25 12:58:55 +0100574 if (drv_data) {
Thomas Abraham3119936a2012-02-16 22:23:58 +0900575 host->quirks |= drv_data->sdhci_quirks;
Russell King17710592014-04-25 12:58:55 +0100576 sc->no_divider = drv_data->no_divider;
577 }
Ben Dooks0d1bb412009-06-14 13:52:37 +0100578
579#ifndef CONFIG_MMC_SDHCI_S3C_DMA
580
581 /* we currently see overruns on errors, so disable the SDMA
582 * support as well. */
583 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
584
Ben Dooks0d1bb412009-06-14 13:52:37 +0100585#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
586
587 /* It seems we do not get an DATA transfer complete on non-busy
588 * transfers, not sure if this is a problem with this specific
589 * SDHCI block, or a missing configuration that needs to be set. */
590 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
591
Kyungmin Park732f0e32010-10-30 12:58:56 +0900592 /* This host supports the Auto CMD12 */
593 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
594
Jaehoon Chung7199e2b2011-07-12 17:30:47 +0900595 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
596 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
597
Marek Szyprowski17866e12010-08-10 18:01:58 -0700598 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
599 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
600 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
601
602 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
603 host->mmc->caps = MMC_CAP_NONREMOVABLE;
604
Thomas Abraham0d22c772012-03-31 23:29:45 -0400605 switch (pdata->max_width) {
606 case 8:
607 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
Gustavo A. R. Silvab1507b22019-07-28 19:02:59 -0500608 /* Fall through */
Thomas Abraham0d22c772012-03-31 23:29:45 -0400609 case 4:
610 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
611 break;
612 }
613
Sangwook Leefa1773c2011-11-07 17:05:22 +0000614 if (pdata->pm_caps)
615 host->mmc->pm_caps |= pdata->pm_caps;
616
Ben Dooks0d1bb412009-06-14 13:52:37 +0100617 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
618 SDHCI_QUIRK_32BIT_DMA_SIZE);
619
Hyuk Lee3fe42e02010-08-10 18:01:55 -0700620 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
621 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
622
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900623 /*
624 * If controller does not have internal clock divider,
625 * we can use overriding functions instead of default.
626 */
Russell King17710592014-04-25 12:58:55 +0100627 if (sc->no_divider) {
Jeongbae Seo253e0a72010-10-08 17:46:21 +0900628 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
629 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
630 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
631 }
632
Jeongbae Seob3824f22010-10-08 17:46:20 +0900633 /* It supports additional host capabilities if needed */
634 if (pdata->host_caps)
635 host->mmc->caps |= pdata->host_caps;
636
Jaehoon Chungc1c4b662012-02-07 15:59:01 +0900637 if (pdata->host_caps2)
638 host->mmc->caps2 |= pdata->host_caps2;
639
Mark Brown9f4e8152012-03-31 23:31:55 -0400640 pm_runtime_enable(&pdev->dev);
641 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
642 pm_runtime_use_autosuspend(&pdev->dev);
643 pm_suspend_ignore_children(&pdev->dev, 1);
644
Ulf Hanssonf8e32602014-12-18 10:41:42 +0100645 ret = mmc_of_parse(host->mmc);
646 if (ret)
647 goto err_req_regs;
Jaehoon Chung11bc9382014-05-26 13:58:28 +0900648
Ben Dooks0d1bb412009-06-14 13:52:37 +0100649 ret = sdhci_add_host(host);
Jisheng Zhangfb8617e2018-05-25 15:15:09 +0800650 if (ret)
Julia Lawall9bda6da2012-03-08 23:24:53 -0500651 goto err_req_regs;
Ben Dooks0d1bb412009-06-14 13:52:37 +0100652
Rafael J. Wysocki162d6f92014-12-05 03:05:33 +0100653#ifdef CONFIG_PM
Seungwon Jeon0aa55c22012-10-30 14:28:36 +0900654 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
655 clk_disable_unprepare(sc->clk_io);
Chander Kashyap2abeb5c2012-09-21 05:42:08 +0000656#endif
Ben Dooks0d1bb412009-06-14 13:52:37 +0100657 return 0;
658
Ben Dooks0d1bb412009-06-14 13:52:37 +0100659 err_req_regs:
Bartlomiej Zolnierkiewicz221414d2014-08-07 18:07:07 +0200660 pm_runtime_disable(&pdev->dev);
661
Ben Dooks0d1bb412009-06-14 13:52:37 +0100662 err_no_busclks:
Thomas Abraham0f310a052012-10-03 08:35:43 +0900663 clk_disable_unprepare(sc->clk_io);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100664
Tomasz Figab1b8fea2012-11-25 15:40:44 -0500665 err_pdata_io_clk:
Ben Dooks0d1bb412009-06-14 13:52:37 +0100666 sdhci_free_host(host);
667
668 return ret;
669}
670
Bill Pemberton6e0ee712012-11-19 13:26:03 -0500671static int sdhci_s3c_remove(struct platform_device *pdev)
Ben Dooks0d1bb412009-06-14 13:52:37 +0100672{
Marek Szyprowski9d51a6b2010-07-20 13:24:33 -0700673 struct sdhci_host *host = platform_get_drvdata(pdev);
674 struct sdhci_s3c *sc = sdhci_priv(host);
Marek Szyprowski17866e12010-08-10 18:01:58 -0700675
676 if (sc->ext_cd_irq)
677 free_irq(sc->ext_cd_irq, sc);
678
Rafael J. Wysocki162d6f92014-12-05 03:05:33 +0100679#ifdef CONFIG_PM
Jaehoon Chung11bc9382014-05-26 13:58:28 +0900680 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
Seungwon Jeon0aa55c22012-10-30 14:28:36 +0900681 clk_prepare_enable(sc->clk_io);
Chander Kashyap2abeb5c2012-09-21 05:42:08 +0000682#endif
Marek Szyprowski9d51a6b2010-07-20 13:24:33 -0700683 sdhci_remove_host(host, 1);
684
Chander Kashyap387a8cbd2012-09-14 09:08:50 +0000685 pm_runtime_dont_use_autosuspend(&pdev->dev);
Mark Brown9f4e8152012-03-31 23:31:55 -0400686 pm_runtime_disable(&pdev->dev);
687
Thomas Abraham0f310a052012-10-03 08:35:43 +0900688 clk_disable_unprepare(sc->clk_io);
Marek Szyprowski9d51a6b2010-07-20 13:24:33 -0700689
Marek Szyprowski9d51a6b2010-07-20 13:24:33 -0700690 sdhci_free_host(host);
Marek Szyprowski9d51a6b2010-07-20 13:24:33 -0700691
Ben Dooks0d1bb412009-06-14 13:52:37 +0100692 return 0;
693}
694
Mark Brownd5e9c022012-03-03 00:46:41 +0000695#ifdef CONFIG_PM_SLEEP
Manuel Lauss29495aa2011-11-03 11:09:45 +0100696static int sdhci_s3c_suspend(struct device *dev)
Ben Dooks0d1bb412009-06-14 13:52:37 +0100697{
Manuel Lauss29495aa2011-11-03 11:09:45 +0100698 struct sdhci_host *host = dev_get_drvdata(dev);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100699
Adrian Hunterd38dcad2017-03-20 19:50:32 +0200700 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
701 mmc_retune_needed(host->mmc);
702
Manuel Lauss29495aa2011-11-03 11:09:45 +0100703 return sdhci_suspend_host(host);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100704}
705
Manuel Lauss29495aa2011-11-03 11:09:45 +0100706static int sdhci_s3c_resume(struct device *dev)
Ben Dooks0d1bb412009-06-14 13:52:37 +0100707{
Manuel Lauss29495aa2011-11-03 11:09:45 +0100708 struct sdhci_host *host = dev_get_drvdata(dev);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100709
Wonil Choi65d13512011-06-29 11:38:38 +0900710 return sdhci_resume_host(host);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100711}
Mark Brownd5e9c022012-03-03 00:46:41 +0000712#endif
Ben Dooks0d1bb412009-06-14 13:52:37 +0100713
Rafael J. Wysocki162d6f92014-12-05 03:05:33 +0100714#ifdef CONFIG_PM
Mark Brown9f4e8152012-03-31 23:31:55 -0400715static int sdhci_s3c_runtime_suspend(struct device *dev)
716{
717 struct sdhci_host *host = dev_get_drvdata(dev);
Chander Kashyap2abeb5c2012-09-21 05:42:08 +0000718 struct sdhci_s3c *ourhost = to_s3c(host);
719 struct clk *busclk = ourhost->clk_io;
720 int ret;
Mark Brown9f4e8152012-03-31 23:31:55 -0400721
Chander Kashyap2abeb5c2012-09-21 05:42:08 +0000722 ret = sdhci_runtime_suspend_host(host);
723
Adrian Hunterd38dcad2017-03-20 19:50:32 +0200724 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
725 mmc_retune_needed(host->mmc);
726
Tomasz Figa3ac147f2014-01-11 22:39:05 +0100727 if (ourhost->cur_clk >= 0)
728 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
Thomas Abraham0f310a052012-10-03 08:35:43 +0900729 clk_disable_unprepare(busclk);
Chander Kashyap2abeb5c2012-09-21 05:42:08 +0000730 return ret;
Mark Brown9f4e8152012-03-31 23:31:55 -0400731}
732
733static int sdhci_s3c_runtime_resume(struct device *dev)
734{
735 struct sdhci_host *host = dev_get_drvdata(dev);
Chander Kashyap2abeb5c2012-09-21 05:42:08 +0000736 struct sdhci_s3c *ourhost = to_s3c(host);
737 struct clk *busclk = ourhost->clk_io;
738 int ret;
Mark Brown9f4e8152012-03-31 23:31:55 -0400739
Thomas Abraham0f310a052012-10-03 08:35:43 +0900740 clk_prepare_enable(busclk);
Tomasz Figa3ac147f2014-01-11 22:39:05 +0100741 if (ourhost->cur_clk >= 0)
742 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
Baolin Wangc6303c52019-07-25 11:14:22 +0800743 ret = sdhci_runtime_resume_host(host, 0);
Chander Kashyap2abeb5c2012-09-21 05:42:08 +0000744 return ret;
Mark Brown9f4e8152012-03-31 23:31:55 -0400745}
746#endif
747
Manuel Lauss29495aa2011-11-03 11:09:45 +0100748static const struct dev_pm_ops sdhci_s3c_pmops = {
Mark Brownd5e9c022012-03-03 00:46:41 +0000749 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
Mark Brown9f4e8152012-03-31 23:31:55 -0400750 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
751 NULL)
Manuel Lauss29495aa2011-11-03 11:09:45 +0100752};
753
Krzysztof Kozlowski4d0aa492015-05-02 00:49:22 +0900754static const struct platform_device_id sdhci_s3c_driver_ids[] = {
Thomas Abraham3119936a2012-02-16 22:23:58 +0900755 {
756 .name = "s3c-sdhci",
757 .driver_data = (kernel_ulong_t)NULL,
Thomas Abraham3119936a2012-02-16 22:23:58 +0900758 },
759 { }
760};
761MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
762
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000763#ifdef CONFIG_OF
Marek Szyprowski3a8e9ca2017-10-04 08:38:24 +0200764static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
765 .no_divider = true,
766};
767
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000768static const struct of_device_id sdhci_s3c_dt_match[] = {
769 { .compatible = "samsung,s3c6410-sdhci", },
770 { .compatible = "samsung,exynos4210-sdhci",
Marek Szyprowski3a8e9ca2017-10-04 08:38:24 +0200771 .data = &exynos4_sdhci_drv_data },
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000772 {},
773};
774MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
775#endif
776
Ben Dooks0d1bb412009-06-14 13:52:37 +0100777static struct platform_driver sdhci_s3c_driver = {
778 .probe = sdhci_s3c_probe,
Bill Pemberton0433c142012-11-19 13:20:26 -0500779 .remove = sdhci_s3c_remove,
Thomas Abraham3119936a2012-02-16 22:23:58 +0900780 .id_table = sdhci_s3c_driver_ids,
Ben Dooks0d1bb412009-06-14 13:52:37 +0100781 .driver = {
Ben Dooks0d1bb412009-06-14 13:52:37 +0100782 .name = "s3c-sdhci",
Thomas Abrahamcd1b00e2012-08-23 17:10:09 +0000783 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
Ulf Hansson6b3a1942016-07-27 11:23:37 +0200784 .pm = &sdhci_s3c_pmops,
Ben Dooks0d1bb412009-06-14 13:52:37 +0100785 },
786};
787
Axel Lind1f81a642011-11-26 12:55:43 +0800788module_platform_driver(sdhci_s3c_driver);
Ben Dooks0d1bb412009-06-14 13:52:37 +0100789
790MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
791MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
792MODULE_LICENSE("GPL v2");
793MODULE_ALIAS("platform:s3c-sdhci");