Gregory CLEMENT | ca36855 | 2018-03-15 12:03:52 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Device Tree file for Marvell RD-AXPWiFiAP. |
| 4 | * |
| 5 | * Note: this board is shipped with a new generation boot loader that |
| 6 | * remaps internal registers at 0xf1000000. Therefore, if earlyprintk |
Paul Bolle | 6cc082a | 2015-01-19 20:40:25 +0100 | [diff] [blame] | 7 | * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the |
| 8 | * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used. |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 9 | * |
| 10 | * Copyright (C) 2013 Marvell |
| 11 | * |
| 12 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | /dts-v1/; |
Thomas Petazzoni | 29e74f8 | 2014-02-11 18:07:12 +0100 | [diff] [blame] | 16 | #include <dt-bindings/gpio/gpio.h> |
Thomas Petazzoni | 5c0169d | 2014-02-11 18:07:13 +0100 | [diff] [blame] | 17 | #include <dt-bindings/input/input.h> |
Ezequiel Garcia | d10ff4d | 2013-08-06 14:09:42 -0300 | [diff] [blame] | 18 | #include "armada-xp-mv78230.dtsi" |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 19 | |
| 20 | / { |
| 21 | model = "Marvell RD-AXPWiFiAP"; |
| 22 | compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; |
| 23 | |
| 24 | chosen { |
Thomas Petazzoni | 9552203 | 2015-03-03 15:41:02 +0100 | [diff] [blame] | 25 | stdout-path = "serial0:115200n8"; |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 26 | }; |
| 27 | |
Gregory CLEMENT | 6f477f4 | 2016-11-06 09:29:35 +0100 | [diff] [blame] | 28 | memory@0 { |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 29 | device_type = "memory"; |
| 30 | reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */ |
| 31 | }; |
| 32 | |
| 33 | soc { |
Ezequiel Garcia | d10ff4d | 2013-08-06 14:09:42 -0300 | [diff] [blame] | 34 | ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 |
Boris Brezillon | c466d99 | 2015-08-18 10:08:53 +0200 | [diff] [blame] | 35 | MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 |
Thomas Petazzoni | d7d5a43 | 2016-03-08 16:59:57 +0100 | [diff] [blame] | 36 | MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 |
| 37 | MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; |
Ezequiel Garcia | d10ff4d | 2013-08-06 14:09:42 -0300 | [diff] [blame] | 38 | |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 39 | internal-regs { |
Paul Bolle | 6cc082a | 2015-01-19 20:40:25 +0100 | [diff] [blame] | 40 | /* UART0 */ |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 41 | serial@12000 { |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 42 | status = "okay"; |
| 43 | }; |
| 44 | |
Paul Bolle | 6cc082a | 2015-01-19 20:40:25 +0100 | [diff] [blame] | 45 | /* UART1 */ |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 46 | serial@12100 { |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 47 | status = "okay"; |
| 48 | }; |
| 49 | |
| 50 | sata@a0000 { |
| 51 | nr-ports = <1>; |
| 52 | status = "okay"; |
| 53 | }; |
| 54 | |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 55 | ethernet@70000 { |
Arnaud Ebalard | 70ee4e9 | 2014-11-22 17:23:30 +0100 | [diff] [blame] | 56 | pinctrl-0 = <&ge0_rgmii_pins>; |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 57 | pinctrl-names = "default"; |
| 58 | status = "okay"; |
| 59 | phy = <&phy0>; |
| 60 | phy-mode = "rgmii-id"; |
| 61 | }; |
| 62 | ethernet@74000 { |
Arnaud Ebalard | 70ee4e9 | 2014-11-22 17:23:30 +0100 | [diff] [blame] | 63 | pinctrl-0 = <&ge1_rgmii_pins>; |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 64 | pinctrl-names = "default"; |
| 65 | status = "okay"; |
| 66 | phy = <&phy1>; |
| 67 | phy-mode = "rgmii-id"; |
| 68 | }; |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 69 | }; |
| 70 | }; |
| 71 | |
| 72 | gpio_keys { |
| 73 | compatible = "gpio-keys"; |
| 74 | #address-cells = <1>; |
| 75 | #size-cells = <0>; |
Arnaud Ebalard | 70ee4e9 | 2014-11-22 17:23:30 +0100 | [diff] [blame] | 76 | pinctrl-0 = <&keys_pin>; |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 77 | pinctrl-names = "default"; |
| 78 | |
Gregory CLEMENT | 9e622af | 2016-11-06 10:59:19 +0100 | [diff] [blame] | 79 | reset { |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 80 | label = "Factory Reset Button"; |
Thomas Petazzoni | 5c0169d | 2014-02-11 18:07:13 +0100 | [diff] [blame] | 81 | linux,code = <KEY_SETUP>; |
Thomas Petazzoni | 29e74f8 | 2014-02-11 18:07:12 +0100 | [diff] [blame] | 82 | gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; |
Thomas Petazzoni | c784147 | 2013-07-30 17:44:50 +0200 | [diff] [blame] | 83 | }; |
| 84 | }; |
| 85 | }; |
Sebastian Hesselbarth | 01c4342 | 2014-09-19 21:20:09 +0200 | [diff] [blame] | 86 | |
Gregory CLEMENT | 1fc2129 | 2016-11-04 17:54:54 +0100 | [diff] [blame] | 87 | &mdio { |
| 88 | phy0: ethernet-phy@0 { |
| 89 | reg = <0>; |
| 90 | }; |
| 91 | |
| 92 | phy1: ethernet-phy@1 { |
| 93 | reg = <1>; |
| 94 | }; |
| 95 | }; |
| 96 | |
Gregory CLEMENT | 007d05d | 2016-11-05 19:03:50 +0100 | [diff] [blame] | 97 | &pciec { |
| 98 | status = "okay"; |
| 99 | |
| 100 | /* First mini-PCIe port */ |
| 101 | pcie@1,0 { |
| 102 | /* Port 0, Lane 0 */ |
| 103 | status = "okay"; |
| 104 | }; |
| 105 | |
| 106 | /* Second mini-PCIe port */ |
| 107 | pcie@2,0 { |
| 108 | /* Port 0, Lane 1 */ |
| 109 | status = "okay"; |
| 110 | }; |
| 111 | |
| 112 | /* Renesas uPD720202 USB 3.0 controller */ |
| 113 | pcie@3,0 { |
| 114 | /* Port 0, Lane 3 */ |
| 115 | status = "okay"; |
| 116 | }; |
| 117 | }; |
| 118 | |
Sebastian Hesselbarth | 01c4342 | 2014-09-19 21:20:09 +0200 | [diff] [blame] | 119 | &pinctrl { |
Arnaud Ebalard | 70ee4e9 | 2014-11-22 17:23:30 +0100 | [diff] [blame] | 120 | pinctrl-0 = <&phy_int_pin>; |
Sebastian Hesselbarth | 01c4342 | 2014-09-19 21:20:09 +0200 | [diff] [blame] | 121 | pinctrl-names = "default"; |
| 122 | |
Arnaud Ebalard | 70ee4e9 | 2014-11-22 17:23:30 +0100 | [diff] [blame] | 123 | keys_pin: keys-pin { |
Sebastian Hesselbarth | 01c4342 | 2014-09-19 21:20:09 +0200 | [diff] [blame] | 124 | marvell,pins = "mpp33"; |
| 125 | marvell,function = "gpio"; |
| 126 | }; |
| 127 | |
Arnaud Ebalard | 70ee4e9 | 2014-11-22 17:23:30 +0100 | [diff] [blame] | 128 | phy_int_pin: phy-int-pin { |
Sebastian Hesselbarth | 01c4342 | 2014-09-19 21:20:09 +0200 | [diff] [blame] | 129 | marvell,pins = "mpp32"; |
| 130 | marvell,function = "gpio"; |
| 131 | }; |
| 132 | }; |
Stefan Roese | 0160a4b | 2016-07-13 11:55:18 +0200 | [diff] [blame] | 133 | |
| 134 | &spi0 { |
| 135 | status = "okay"; |
| 136 | |
| 137 | spi-flash@0 { |
| 138 | #address-cells = <1>; |
| 139 | #size-cells = <1>; |
| 140 | compatible = "n25q128a13", "jedec,spi-nor"; |
| 141 | reg = <0>; /* Chip select 0 */ |
| 142 | spi-max-frequency = <108000000>; |
| 143 | }; |
| 144 | }; |