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Gregory CLEMENTca368552018-03-15 12:03:52 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Thomas Petazzonic7841472013-07-30 17:44:50 +02002/*
3 * Device Tree file for Marvell RD-AXPWiFiAP.
4 *
5 * Note: this board is shipped with a new generation boot loader that
6 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
Paul Bolle6cc082a2015-01-19 20:40:25 +01007 * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
8 * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
Thomas Petazzonic7841472013-07-30 17:44:50 +02009 *
10 * Copyright (C) 2013 Marvell
11 *
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Thomas Petazzonic7841472013-07-30 17:44:50 +020013 */
14
15/dts-v1/;
Thomas Petazzoni29e74f82014-02-11 18:07:12 +010016#include <dt-bindings/gpio/gpio.h>
Thomas Petazzoni5c0169d2014-02-11 18:07:13 +010017#include <dt-bindings/input/input.h>
Ezequiel Garciad10ff4d2013-08-06 14:09:42 -030018#include "armada-xp-mv78230.dtsi"
Thomas Petazzonic7841472013-07-30 17:44:50 +020019
20/ {
21 model = "Marvell RD-AXPWiFiAP";
22 compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
23
24 chosen {
Thomas Petazzoni95522032015-03-03 15:41:02 +010025 stdout-path = "serial0:115200n8";
Thomas Petazzonic7841472013-07-30 17:44:50 +020026 };
27
Gregory CLEMENT6f477f42016-11-06 09:29:35 +010028 memory@0 {
Thomas Petazzonic7841472013-07-30 17:44:50 +020029 device_type = "memory";
30 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
31 };
32
33 soc {
Ezequiel Garciad10ff4d2013-08-06 14:09:42 -030034 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
Boris Brezillonc466d992015-08-18 10:08:53 +020035 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
Thomas Petazzonid7d5a432016-03-08 16:59:57 +010036 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
37 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
Ezequiel Garciad10ff4d2013-08-06 14:09:42 -030038
Thomas Petazzonic7841472013-07-30 17:44:50 +020039 internal-regs {
Paul Bolle6cc082a2015-01-19 20:40:25 +010040 /* UART0 */
Thomas Petazzonic7841472013-07-30 17:44:50 +020041 serial@12000 {
Thomas Petazzonic7841472013-07-30 17:44:50 +020042 status = "okay";
43 };
44
Paul Bolle6cc082a2015-01-19 20:40:25 +010045 /* UART1 */
Thomas Petazzonic7841472013-07-30 17:44:50 +020046 serial@12100 {
Thomas Petazzonic7841472013-07-30 17:44:50 +020047 status = "okay";
48 };
49
50 sata@a0000 {
51 nr-ports = <1>;
52 status = "okay";
53 };
54
Thomas Petazzonic7841472013-07-30 17:44:50 +020055 ethernet@70000 {
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +010056 pinctrl-0 = <&ge0_rgmii_pins>;
Thomas Petazzonic7841472013-07-30 17:44:50 +020057 pinctrl-names = "default";
58 status = "okay";
59 phy = <&phy0>;
60 phy-mode = "rgmii-id";
61 };
62 ethernet@74000 {
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +010063 pinctrl-0 = <&ge1_rgmii_pins>;
Thomas Petazzonic7841472013-07-30 17:44:50 +020064 pinctrl-names = "default";
65 status = "okay";
66 phy = <&phy1>;
67 phy-mode = "rgmii-id";
68 };
Thomas Petazzonic7841472013-07-30 17:44:50 +020069 };
70 };
71
72 gpio_keys {
73 compatible = "gpio-keys";
74 #address-cells = <1>;
75 #size-cells = <0>;
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +010076 pinctrl-0 = <&keys_pin>;
Thomas Petazzonic7841472013-07-30 17:44:50 +020077 pinctrl-names = "default";
78
Gregory CLEMENT9e622af2016-11-06 10:59:19 +010079 reset {
Thomas Petazzonic7841472013-07-30 17:44:50 +020080 label = "Factory Reset Button";
Thomas Petazzoni5c0169d2014-02-11 18:07:13 +010081 linux,code = <KEY_SETUP>;
Thomas Petazzoni29e74f82014-02-11 18:07:12 +010082 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
Thomas Petazzonic7841472013-07-30 17:44:50 +020083 };
84 };
85};
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +020086
Gregory CLEMENT1fc21292016-11-04 17:54:54 +010087&mdio {
88 phy0: ethernet-phy@0 {
89 reg = <0>;
90 };
91
92 phy1: ethernet-phy@1 {
93 reg = <1>;
94 };
95};
96
Gregory CLEMENT007d05d2016-11-05 19:03:50 +010097&pciec {
98 status = "okay";
99
100 /* First mini-PCIe port */
101 pcie@1,0 {
102 /* Port 0, Lane 0 */
103 status = "okay";
104 };
105
106 /* Second mini-PCIe port */
107 pcie@2,0 {
108 /* Port 0, Lane 1 */
109 status = "okay";
110 };
111
112 /* Renesas uPD720202 USB 3.0 controller */
113 pcie@3,0 {
114 /* Port 0, Lane 3 */
115 status = "okay";
116 };
117};
118
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +0200119&pinctrl {
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +0100120 pinctrl-0 = <&phy_int_pin>;
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +0200121 pinctrl-names = "default";
122
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +0100123 keys_pin: keys-pin {
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +0200124 marvell,pins = "mpp33";
125 marvell,function = "gpio";
126 };
127
Arnaud Ebalard70ee4e92014-11-22 17:23:30 +0100128 phy_int_pin: phy-int-pin {
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +0200129 marvell,pins = "mpp32";
130 marvell,function = "gpio";
131 };
132};
Stefan Roese0160a4b2016-07-13 11:55:18 +0200133
134&spi0 {
135 status = "okay";
136
137 spi-flash@0 {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "n25q128a13", "jedec,spi-nor";
141 reg = <0>; /* Chip select 0 */
142 spi-max-frequency = <108000000>;
143 };
144};