Andrew Lunn | a2443fd | 2019-01-21 19:05:50 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Broadcom UniMAC MDIO bus controller driver |
| 4 | * |
Doug Berger | 4213808 | 2017-03-13 17:41:42 -0700 | [diff] [blame] | 5 | * Copyright (C) 2014-2017 Broadcom |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
Calvin Johnson | 1bf3436 | 2021-03-15 16:19:05 +0530 | [diff] [blame] | 8 | #include <linux/clk.h> |
| 9 | #include <linux/delay.h> |
| 10 | #include <linux/io.h> |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 11 | #include <linux/kernel.h> |
Calvin Johnson | 1bf3436 | 2021-03-15 16:19:05 +0530 | [diff] [blame] | 12 | #include <linux/module.h> |
| 13 | #include <linux/of.h> |
| 14 | #include <linux/of_mdio.h> |
| 15 | #include <linux/of_platform.h> |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 16 | #include <linux/phy.h> |
Calvin Johnson | 1bf3436 | 2021-03-15 16:19:05 +0530 | [diff] [blame] | 17 | #include <linux/platform_data/mdio-bcm-unimac.h> |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/sched.h> |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 20 | |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 21 | #define MDIO_CMD 0x00 |
| 22 | #define MDIO_START_BUSY (1 << 29) |
| 23 | #define MDIO_READ_FAIL (1 << 28) |
| 24 | #define MDIO_RD (2 << 26) |
| 25 | #define MDIO_WR (1 << 26) |
| 26 | #define MDIO_PMD_SHIFT 21 |
| 27 | #define MDIO_PMD_MASK 0x1F |
| 28 | #define MDIO_REG_SHIFT 16 |
| 29 | #define MDIO_REG_MASK 0x1F |
| 30 | |
| 31 | #define MDIO_CFG 0x04 |
| 32 | #define MDIO_C22 (1 << 0) |
| 33 | #define MDIO_C45 0 |
| 34 | #define MDIO_CLK_DIV_SHIFT 4 |
| 35 | #define MDIO_CLK_DIV_MASK 0x3F |
| 36 | #define MDIO_SUPP_PREAMBLE (1 << 12) |
| 37 | |
| 38 | struct unimac_mdio_priv { |
| 39 | struct mii_bus *mii_bus; |
| 40 | void __iomem *base; |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 41 | int (*wait_func) (void *wait_func_data); |
| 42 | void *wait_func_data; |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 43 | struct clk *clk; |
| 44 | u32 clk_freq; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 45 | }; |
| 46 | |
Florian Fainelli | cb51a09 | 2017-08-29 13:35:18 -0700 | [diff] [blame] | 47 | static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset) |
| 48 | { |
| 49 | /* MIPS chips strapped for BE will automagically configure the |
| 50 | * peripheral registers for CPU-native byte order. |
| 51 | */ |
| 52 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
| 53 | return __raw_readl(priv->base + offset); |
| 54 | else |
| 55 | return readl_relaxed(priv->base + offset); |
| 56 | } |
| 57 | |
| 58 | static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val, |
| 59 | u32 offset) |
| 60 | { |
| 61 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
| 62 | __raw_writel(val, priv->base + offset); |
| 63 | else |
| 64 | writel_relaxed(val, priv->base + offset); |
| 65 | } |
| 66 | |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 67 | static inline void unimac_mdio_start(struct unimac_mdio_priv *priv) |
| 68 | { |
| 69 | u32 reg; |
| 70 | |
Florian Fainelli | cb51a09 | 2017-08-29 13:35:18 -0700 | [diff] [blame] | 71 | reg = unimac_mdio_readl(priv, MDIO_CMD); |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 72 | reg |= MDIO_START_BUSY; |
Florian Fainelli | cb51a09 | 2017-08-29 13:35:18 -0700 | [diff] [blame] | 73 | unimac_mdio_writel(priv, reg, MDIO_CMD); |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 74 | } |
| 75 | |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 76 | static int unimac_mdio_poll(void *wait_func_data) |
Florian Fainelli | 69a60b0 | 2017-07-31 12:04:22 -0700 | [diff] [blame] | 77 | { |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 78 | struct unimac_mdio_priv *priv = wait_func_data; |
Justin Chen | 54a600e | 2023-12-13 14:27:44 -0800 | [diff] [blame] | 79 | u32 val; |
Justin Chen | 268531b | 2023-12-13 14:27:43 -0800 | [diff] [blame] | 80 | |
| 81 | /* |
| 82 | * C22 transactions should take ~25 usec, will need to adjust |
| 83 | * if C45 support is added. |
| 84 | */ |
| 85 | udelay(30); |
Florian Fainelli | 69a60b0 | 2017-07-31 12:04:22 -0700 | [diff] [blame] | 86 | |
Justin Chen | 54a600e | 2023-12-13 14:27:44 -0800 | [diff] [blame] | 87 | return read_poll_timeout(unimac_mdio_readl, val, !(val & MDIO_START_BUSY), |
| 88 | 2000, 100000, false, priv, MDIO_CMD); |
Florian Fainelli | 69a60b0 | 2017-07-31 12:04:22 -0700 | [diff] [blame] | 89 | } |
| 90 | |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 91 | static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg) |
| 92 | { |
| 93 | struct unimac_mdio_priv *priv = bus->priv; |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 94 | int ret; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 95 | u32 cmd; |
| 96 | |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 97 | ret = clk_prepare_enable(priv->clk); |
| 98 | if (ret) |
| 99 | return ret; |
| 100 | |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 101 | /* Prepare the read operation */ |
| 102 | cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT); |
Florian Fainelli | cb51a09 | 2017-08-29 13:35:18 -0700 | [diff] [blame] | 103 | unimac_mdio_writel(priv, cmd, MDIO_CMD); |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 104 | |
| 105 | /* Start MDIO transaction */ |
| 106 | unimac_mdio_start(priv); |
| 107 | |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 108 | ret = priv->wait_func(priv->wait_func_data); |
Florian Fainelli | 69a60b0 | 2017-07-31 12:04:22 -0700 | [diff] [blame] | 109 | if (ret) |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 110 | goto out; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 111 | |
Florian Fainelli | cb51a09 | 2017-08-29 13:35:18 -0700 | [diff] [blame] | 112 | cmd = unimac_mdio_readl(priv, MDIO_CMD); |
Florian Fainelli | 1a3f4e8 | 2015-06-10 12:24:11 -0700 | [diff] [blame] | 113 | |
| 114 | /* Some broken devices are known not to release the line during |
| 115 | * turn-around, e.g: Broadcom BCM53125 external switches, so check for |
| 116 | * that condition here and ignore the MDIO controller read failure |
| 117 | * indication. |
| 118 | */ |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 119 | if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL)) { |
| 120 | ret = -EIO; |
| 121 | goto out; |
| 122 | } |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 123 | |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 124 | ret = cmd & 0xffff; |
| 125 | out: |
| 126 | clk_disable_unprepare(priv->clk); |
| 127 | return ret; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | static int unimac_mdio_write(struct mii_bus *bus, int phy_id, |
| 131 | int reg, u16 val) |
| 132 | { |
| 133 | struct unimac_mdio_priv *priv = bus->priv; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 134 | u32 cmd; |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 135 | int ret; |
| 136 | |
| 137 | ret = clk_prepare_enable(priv->clk); |
| 138 | if (ret) |
| 139 | return ret; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 140 | |
| 141 | /* Prepare the write operation */ |
| 142 | cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | |
| 143 | (reg << MDIO_REG_SHIFT) | (0xffff & val); |
Florian Fainelli | cb51a09 | 2017-08-29 13:35:18 -0700 | [diff] [blame] | 144 | unimac_mdio_writel(priv, cmd, MDIO_CMD); |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 145 | |
| 146 | unimac_mdio_start(priv); |
| 147 | |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 148 | ret = priv->wait_func(priv->wait_func_data); |
| 149 | clk_disable_unprepare(priv->clk); |
| 150 | |
| 151 | return ret; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 152 | } |
| 153 | |
Florian Fainelli | d8e704e | 2015-06-26 10:39:06 -0700 | [diff] [blame] | 154 | /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with |
| 155 | * their internal MDIO management controller making them fail to successfully |
| 156 | * be read from or written to for the first transaction. We insert a dummy |
| 157 | * BMSR read here to make sure that phy_get_device() and get_phy_id() can |
| 158 | * correctly read the PHY MII_PHYSID1/2 registers and successfully register a |
| 159 | * PHY device for this peripheral. |
| 160 | * |
| 161 | * Once the PHY driver is registered, we can workaround subsequent reads from |
| 162 | * there (e.g: during system-wide power management). |
| 163 | * |
| 164 | * bus->reset is invoked before mdiobus_scan during mdiobus_register and is |
| 165 | * therefore the right location to stick that workaround. Since we do not want |
| 166 | * to read from non-existing PHYs, we either use bus->phy_mask or do a manual |
| 167 | * Device Tree scan to limit the search area. |
| 168 | */ |
| 169 | static int unimac_mdio_reset(struct mii_bus *bus) |
| 170 | { |
| 171 | struct device_node *np = bus->dev.of_node; |
| 172 | struct device_node *child; |
| 173 | u32 read_mask = 0; |
| 174 | int addr; |
| 175 | |
| 176 | if (!np) { |
| 177 | read_mask = ~bus->phy_mask; |
| 178 | } else { |
| 179 | for_each_available_child_of_node(np, child) { |
| 180 | addr = of_mdio_parse_addr(&bus->dev, child); |
| 181 | if (addr < 0) |
| 182 | continue; |
| 183 | |
| 184 | read_mask |= 1 << addr; |
| 185 | } |
| 186 | } |
| 187 | |
| 188 | for (addr = 0; addr < PHY_MAX_ADDR; addr++) { |
Florian Fainelli | e23597f | 2017-07-31 12:04:24 -0700 | [diff] [blame] | 189 | if (read_mask & 1 << addr) { |
| 190 | dev_dbg(&bus->dev, "Workaround for PHY @ %d\n", addr); |
Florian Fainelli | d8e704e | 2015-06-26 10:39:06 -0700 | [diff] [blame] | 191 | mdiobus_read(bus, addr, MII_BMSR); |
Florian Fainelli | e23597f | 2017-07-31 12:04:24 -0700 | [diff] [blame] | 192 | } |
Florian Fainelli | d8e704e | 2015-06-26 10:39:06 -0700 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | return 0; |
| 196 | } |
| 197 | |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 198 | static int unimac_mdio_clk_set(struct unimac_mdio_priv *priv) |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 199 | { |
| 200 | unsigned long rate; |
| 201 | u32 reg, div; |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 202 | int ret; |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 203 | |
| 204 | /* Keep the hardware default values */ |
| 205 | if (!priv->clk_freq) |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 206 | return 0; |
| 207 | |
| 208 | ret = clk_prepare_enable(priv->clk); |
| 209 | if (ret) |
| 210 | return ret; |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 211 | |
| 212 | if (!priv->clk) |
| 213 | rate = 250000000; |
| 214 | else |
| 215 | rate = clk_get_rate(priv->clk); |
| 216 | |
| 217 | div = (rate / (2 * priv->clk_freq)) - 1; |
| 218 | if (div & ~MDIO_CLK_DIV_MASK) { |
| 219 | pr_warn("Incorrect MDIO clock frequency, ignoring\n"); |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 220 | ret = 0; |
| 221 | goto out; |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 222 | } |
| 223 | |
Zheng Yongjun | e65c2793 | 2021-06-01 22:18:59 +0800 | [diff] [blame] | 224 | /* The MDIO clock is the reference clock (typically 250Mhz) divided by |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 225 | * 2 x (MDIO_CLK_DIV + 1) |
| 226 | */ |
| 227 | reg = unimac_mdio_readl(priv, MDIO_CFG); |
| 228 | reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT); |
| 229 | reg |= div << MDIO_CLK_DIV_SHIFT; |
| 230 | unimac_mdio_writel(priv, reg, MDIO_CFG); |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 231 | out: |
| 232 | clk_disable_unprepare(priv->clk); |
| 233 | return ret; |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 234 | } |
| 235 | |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 236 | static int unimac_mdio_probe(struct platform_device *pdev) |
| 237 | { |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 238 | struct unimac_mdio_pdata *pdata = pdev->dev.platform_data; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 239 | struct unimac_mdio_priv *priv; |
| 240 | struct device_node *np; |
| 241 | struct mii_bus *bus; |
| 242 | struct resource *r; |
| 243 | int ret; |
| 244 | |
| 245 | np = pdev->dev.of_node; |
| 246 | |
| 247 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 248 | if (!priv) |
| 249 | return -ENOMEM; |
| 250 | |
| 251 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Wei Yongjun | 297a696 | 2018-01-11 11:21:51 +0000 | [diff] [blame] | 252 | if (!r) |
| 253 | return -EINVAL; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 254 | |
| 255 | /* Just ioremap, as this MDIO block is usually integrated into an |
| 256 | * Ethernet MAC controller register range |
| 257 | */ |
| 258 | priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); |
| 259 | if (!priv->base) { |
| 260 | dev_err(&pdev->dev, "failed to remap register\n"); |
| 261 | return -ENOMEM; |
| 262 | } |
| 263 | |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 264 | if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq)) |
| 265 | priv->clk_freq = 0; |
| 266 | |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 267 | priv->mii_bus = mdiobus_alloc(); |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 268 | if (!priv->mii_bus) |
| 269 | return -ENOMEM; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 270 | |
| 271 | bus = priv->mii_bus; |
| 272 | bus->priv = priv; |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 273 | if (pdata) { |
| 274 | bus->name = pdata->bus_name; |
| 275 | priv->wait_func = pdata->wait_func; |
| 276 | priv->wait_func_data = pdata->wait_func_data; |
| 277 | bus->phy_mask = ~pdata->phy_mask; |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 278 | priv->clk = pdata->clk; |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 279 | } else { |
| 280 | bus->name = "unimac MII bus"; |
| 281 | priv->wait_func_data = priv; |
| 282 | priv->wait_func = unimac_mdio_poll; |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 283 | priv->clk = devm_clk_get_optional(&pdev->dev, NULL); |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 284 | } |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 285 | |
| 286 | if (IS_ERR(priv->clk)) { |
| 287 | ret = PTR_ERR(priv->clk); |
| 288 | goto out_mdio_free; |
| 289 | } |
| 290 | |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 291 | bus->parent = &pdev->dev; |
| 292 | bus->read = unimac_mdio_read; |
| 293 | bus->write = unimac_mdio_write; |
Florian Fainelli | d8e704e | 2015-06-26 10:39:06 -0700 | [diff] [blame] | 294 | bus->reset = unimac_mdio_reset; |
Florian Fainelli | d782f7c | 2017-07-31 12:04:23 -0700 | [diff] [blame] | 295 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id); |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 296 | |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 297 | ret = unimac_mdio_clk_set(priv); |
| 298 | if (ret) |
| 299 | goto out_mdio_free; |
| 300 | |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 301 | ret = of_mdiobus_register(bus, np); |
| 302 | if (ret) { |
| 303 | dev_err(&pdev->dev, "MDIO bus registration failed\n"); |
Andrew Lunn | e7f4dc3 | 2016-01-06 20:11:15 +0100 | [diff] [blame] | 304 | goto out_mdio_free; |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | platform_set_drvdata(pdev, priv); |
| 308 | |
Florian Fainelli | 647aed2 | 2019-03-20 09:45:15 -0700 | [diff] [blame] | 309 | dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus\n"); |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 310 | |
| 311 | return 0; |
| 312 | |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 313 | out_mdio_free: |
| 314 | mdiobus_free(bus); |
| 315 | return ret; |
| 316 | } |
| 317 | |
Uwe Kleine-König | 9b12e3f | 2023-09-18 21:50:46 +0200 | [diff] [blame] | 318 | static void unimac_mdio_remove(struct platform_device *pdev) |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 319 | { |
| 320 | struct unimac_mdio_priv *priv = platform_get_drvdata(pdev); |
| 321 | |
| 322 | mdiobus_unregister(priv->mii_bus); |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 323 | mdiobus_free(priv->mii_bus); |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 324 | } |
| 325 | |
Arnd Bergmann | 9b97123 | 2018-09-26 15:14:10 +0200 | [diff] [blame] | 326 | static int __maybe_unused unimac_mdio_resume(struct device *d) |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 327 | { |
| 328 | struct unimac_mdio_priv *priv = dev_get_drvdata(d); |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 329 | |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 330 | return unimac_mdio_clk_set(priv); |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops, |
Florian Fainelli | ee97535 | 2024-02-19 12:40:51 -0800 | [diff] [blame] | 334 | NULL, unimac_mdio_resume); |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 335 | |
Fabian Frederick | d8a7dad | 2015-03-17 19:40:23 +0100 | [diff] [blame] | 336 | static const struct of_device_id unimac_mdio_ids[] = { |
Justin Chen | 9112fc0 | 2024-02-28 14:53:58 -0800 | [diff] [blame] | 337 | { .compatible = "brcm,asp-v2.2-mdio", }, |
Justin Chen | 9de2b40 | 2023-07-13 15:19:04 -0700 | [diff] [blame] | 338 | { .compatible = "brcm,asp-v2.1-mdio", }, |
| 339 | { .compatible = "brcm,asp-v2.0-mdio", }, |
Doug Berger | 4213808 | 2017-03-13 17:41:42 -0700 | [diff] [blame] | 340 | { .compatible = "brcm,genet-mdio-v5", }, |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 341 | { .compatible = "brcm,genet-mdio-v4", }, |
| 342 | { .compatible = "brcm,genet-mdio-v3", }, |
| 343 | { .compatible = "brcm,genet-mdio-v2", }, |
| 344 | { .compatible = "brcm,genet-mdio-v1", }, |
| 345 | { .compatible = "brcm,unimac-mdio", }, |
Florian Fainelli | 4559154 | 2014-08-29 12:43:56 -0700 | [diff] [blame] | 346 | { /* sentinel */ }, |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 347 | }; |
Luis de Bethencourt | 2f90a30 | 2015-09-18 18:16:12 +0200 | [diff] [blame] | 348 | MODULE_DEVICE_TABLE(of, unimac_mdio_ids); |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 349 | |
| 350 | static struct platform_driver unimac_mdio_driver = { |
| 351 | .driver = { |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 352 | .name = UNIMAC_MDIO_DRV_NAME, |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 353 | .of_match_table = unimac_mdio_ids, |
Florian Fainelli | b78ac6e | 2018-09-20 17:05:40 -0700 | [diff] [blame] | 354 | .pm = &unimac_mdio_pm_ops, |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 355 | }, |
| 356 | .probe = unimac_mdio_probe, |
Uwe Kleine-König | 9b12e3f | 2023-09-18 21:50:46 +0200 | [diff] [blame] | 357 | .remove_new = unimac_mdio_remove, |
Florian Fainelli | 2ba1b16 | 2014-08-27 17:04:47 -0700 | [diff] [blame] | 358 | }; |
| 359 | module_platform_driver(unimac_mdio_driver); |
| 360 | |
| 361 | MODULE_AUTHOR("Broadcom Corporation"); |
| 362 | MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller"); |
| 363 | MODULE_LICENSE("GPL"); |
Florian Fainelli | f248aff | 2017-07-31 12:04:25 -0700 | [diff] [blame] | 364 | MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME); |