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Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
Sai Prakash Ranjan60457d52022-05-18 22:14:17 +05304/* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
5#define __DISABLE_TRACE_MMIO__
6
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06007#include <linux/clk.h>
8#include <linux/console.h>
9#include <linux/io.h>
10#include <linux/iopoll.h>
Akash Asthana3e4aaea2019-10-10 15:16:03 +053011#include <linux/irq.h>
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060012#include <linux/module.h>
13#include <linux/of.h>
Rajendra Nayaka5819b52020-06-15 17:32:39 +053014#include <linux/pm_opp.h>
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060015#include <linux/platform_device.h>
Akash Asthanaf3974412020-01-06 20:15:04 +053016#include <linux/pm_runtime.h>
Akash Asthana8b7103f2019-10-10 15:16:43 +053017#include <linux/pm_wakeirq.h>
Elliot Berman491581f2023-02-03 13:01:32 -080018#include <linux/soc/qcom/geni-se.h>
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060019#include <linux/serial.h>
20#include <linux/serial_core.h>
21#include <linux/slab.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
Vijaya Krishna Nivarthi408e5322022-09-07 21:01:42 +053024#include <dt-bindings/interconnect/qcom,icc.h>
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060025
26/* UART specific GENI registers */
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -060027#define SE_UART_LOOPBACK_CFG 0x22c
Roja Rani Yarubandi9fa3c4b2020-03-04 16:52:03 +053028#define SE_UART_IO_MACRO_CTRL 0x240
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060029#define SE_UART_TX_TRANS_CFG 0x25c
30#define SE_UART_TX_WORD_LEN 0x268
31#define SE_UART_TX_STOP_BIT_LEN 0x26c
32#define SE_UART_TX_TRANS_LEN 0x270
33#define SE_UART_RX_TRANS_CFG 0x280
34#define SE_UART_RX_WORD_LEN 0x28c
35#define SE_UART_RX_STALE_CNT 0x294
36#define SE_UART_TX_PARITY_CFG 0x2a4
37#define SE_UART_RX_PARITY_CFG 0x2a8
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -060038#define SE_UART_MANUAL_RFR 0x2ac
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060039
40/* SE_UART_TRANS_CFG */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010041#define UART_TX_PAR_EN BIT(0)
42#define UART_CTS_MASK BIT(1)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060043
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060044/* SE_UART_TX_STOP_BIT_LEN */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010045#define TX_STOP_BIT_LEN_1 0
46#define TX_STOP_BIT_LEN_2 2
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060047
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060048/* SE_UART_RX_TRANS_CFG */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010049#define UART_RX_PAR_EN BIT(3)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060050
51/* SE_UART_RX_WORD_LEN */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010052#define RX_WORD_LEN_MASK GENMASK(9, 0)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060053
54/* SE_UART_RX_STALE_CNT */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010055#define RX_STALE_CNT GENMASK(23, 0)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060056
57/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010058#define PAR_CALC_EN BIT(0)
59#define PAR_EVEN 0x00
60#define PAR_ODD 0x01
61#define PAR_SPACE 0x10
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060062
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -060063/* SE_UART_MANUAL_RFR register fields */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010064#define UART_MANUAL_RFR_EN BIT(31)
65#define UART_RFR_NOT_READY BIT(1)
66#define UART_RFR_READY BIT(0)
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -060067
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060068/* UART M_CMD OP codes */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010069#define UART_START_TX 0x1
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060070/* UART S_CMD OP codes */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010071#define UART_START_READ 0x1
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +010072#define UART_PARAM 0x1
73#define UART_PARAM_RFR_OPEN BIT(7)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060074
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010075#define UART_OVERSAMPLING 32
76#define STALE_TIMEOUT 16
77#define DEFAULT_BITS_PER_CHAR 10
78#define GENI_UART_CONS_PORTS 1
79#define GENI_UART_PORTS 3
80#define DEF_FIFO_DEPTH_WORDS 16
81#define DEF_TX_WM 2
82#define DEF_FIFO_WIDTH_BITS 32
83#define UART_RX_WM 2
Akash Asthana69bd1a42020-01-06 20:15:05 +053084
85/* SE_UART_LOOPBACK_CFG */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010086#define RX_TX_SORTED BIT(0)
87#define CTS_RTS_SORTED BIT(1)
88#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -060089
Roja Rani Yarubandi9fa3c4b2020-03-04 16:52:03 +053090/* UART pin swap value */
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010091#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
Roja Rani Yarubandi9fa3c4b2020-03-04 16:52:03 +053092#define IO_MACRO_IO0_SEL 0x3
Bartosz Golaszewski6cde11d2022-12-29 16:50:20 +010093#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
Roja Rani Yarubandi9fa3c4b2020-03-04 16:52:03 +053094#define IO_MACRO_IO2_IO3_SWAP 0x4640
95
Douglas Anderson650c8bd2020-06-26 13:00:33 -070096/* We always configure 4 bytes per FIFO word */
Bartosz Golaszewskibd795582022-12-29 16:50:26 +010097#define BYTES_PER_FIFO_WORD 4U
Douglas Anderson650c8bd2020-06-26 13:00:33 -070098
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +010099#define DMA_RX_BUF_SIZE 2048
100
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +0100101struct qcom_geni_device_data {
102 bool console;
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100103 enum geni_se_xfer_mode mode;
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +0100104};
105
Douglas Andersone42d6c32020-06-26 13:00:32 -0700106struct qcom_geni_private_data {
107 /* NOTE: earlycon port will have NULL here */
108 struct uart_driver *drv;
109
110 u32 poll_cached_bytes;
111 unsigned int poll_cached_bytes_cnt;
Douglas Anderson650c8bd2020-06-26 13:00:33 -0700112
113 u32 write_cached_bytes;
114 unsigned int write_cached_bytes_cnt;
Douglas Andersone42d6c32020-06-26 13:00:32 -0700115};
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600116
117struct qcom_geni_serial_port {
118 struct uart_port uport;
119 struct geni_se se;
Akash Asthanaf3974412020-01-06 20:15:04 +0530120 const char *name;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600121 u32 tx_fifo_depth;
122 u32 tx_fifo_width;
123 u32 rx_fifo_depth;
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100124 dma_addr_t tx_dma_addr;
125 dma_addr_t rx_dma_addr;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600126 bool setup;
Johan Hovoldc80ee362024-09-06 15:13:29 +0200127 unsigned long poll_timeout_us;
Johan Hovold8ece7b72023-07-14 15:02:13 +0200128 unsigned long clk_rate;
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100129 void *rx_buf;
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600130 u32 loopback;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600131 bool brk;
Ryan Casea1fee892018-11-29 18:18:40 -0800132
133 unsigned int tx_remaining;
Johan Hovoldcc4a0e52024-09-06 15:13:34 +0200134 unsigned int tx_queued;
Akash Asthana8b7103f2019-10-10 15:16:43 +0530135 int wakeup_irq;
Roja Rani Yarubandi9fa3c4b2020-03-04 16:52:03 +0530136 bool rx_tx_swap;
137 bool cts_rts_swap;
Douglas Andersone42d6c32020-06-26 13:00:32 -0700138
139 struct qcom_geni_private_data private_data;
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +0100140 const struct qcom_geni_device_data *dev_data;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600141};
142
Karthikeyan Ramasubramanianf7371752018-05-03 14:14:36 -0600143static const struct uart_ops qcom_geni_console_pops;
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600144static const struct uart_ops qcom_geni_uart_pops;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600145static struct uart_driver qcom_geni_console_driver;
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600146static struct uart_driver qcom_geni_uart_driver;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600147
Johan Hovold63d14d92024-09-06 15:13:36 +0200148static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport);
Johan Hovoldcc4a0e52024-09-06 15:13:34 +0200149static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport);
150
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100151static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport)
152{
153 return container_of(uport, struct qcom_geni_serial_port, uport);
154}
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600155
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600156static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
157 [0] = {
158 .uport = {
Bartosz Golaszewski3931b8f2022-12-29 16:50:24 +0100159 .iotype = UPIO_MEM,
160 .ops = &qcom_geni_uart_pops,
161 .flags = UPF_BOOT_AUTOCONF,
162 .line = 0,
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600163 },
164 },
165 [1] = {
166 .uport = {
Bartosz Golaszewski3931b8f2022-12-29 16:50:24 +0100167 .iotype = UPIO_MEM,
168 .ops = &qcom_geni_uart_pops,
169 .flags = UPF_BOOT_AUTOCONF,
170 .line = 1,
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600171 },
172 },
173 [2] = {
174 .uport = {
Bartosz Golaszewski3931b8f2022-12-29 16:50:24 +0100175 .iotype = UPIO_MEM,
176 .ops = &qcom_geni_uart_pops,
177 .flags = UPF_BOOT_AUTOCONF,
178 .line = 2,
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600179 },
180 },
181};
182
Karthikeyan Ramasubramanianf7371752018-05-03 14:14:36 -0600183static struct qcom_geni_serial_port qcom_geni_console_port = {
184 .uport = {
185 .iotype = UPIO_MEM,
186 .ops = &qcom_geni_console_pops,
187 .flags = UPF_BOOT_AUTOCONF,
188 .line = 0,
189 },
190};
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600191
192static int qcom_geni_serial_request_port(struct uart_port *uport)
193{
194 struct platform_device *pdev = to_platform_device(uport->dev);
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100195 struct qcom_geni_serial_port *port = to_dev_port(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600196
YueHaibing44e60d52019-08-02 21:08:17 +0800197 uport->membase = devm_platform_ioremap_resource(pdev, 0);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600198 if (IS_ERR(uport->membase))
199 return PTR_ERR(uport->membase);
200 port->se.base = uport->membase;
201 return 0;
202}
203
204static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
205{
206 if (cfg_flags & UART_CONFIG_TYPE) {
207 uport->type = PORT_MSM;
208 qcom_geni_serial_request_port(uport);
209 }
210}
211
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600212static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600213{
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600214 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
215 u32 geni_ios;
216
Matthias Kaehlckee8a6ca82019-01-18 16:23:05 -0800217 if (uart_console(uport)) {
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600218 mctrl |= TIOCM_CTS;
219 } else {
Ryan Case9e06d552019-01-07 17:58:35 -0800220 geni_ios = readl(uport->membase + SE_GENI_IOS);
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600221 if (!(geni_ios & IO2_DATA_IN))
222 mctrl |= TIOCM_CTS;
223 }
224
225 return mctrl;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600226}
227
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600228static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600229 unsigned int mctrl)
230{
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600231 u32 uart_manual_rfr = 0;
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100232 struct qcom_geni_serial_port *port = to_dev_port(uport);
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600233
Matthias Kaehlckee8a6ca82019-01-18 16:23:05 -0800234 if (uart_console(uport))
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600235 return;
236
Akash Asthana69bd1a42020-01-06 20:15:05 +0530237 if (mctrl & TIOCM_LOOP)
238 port->loopback = RX_TX_CTS_RTS_SORTED;
239
satya priyaa4ced372020-09-10 18:23:58 +0530240 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600241 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
Ryan Case9e06d552019-01-07 17:58:35 -0800242 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600243}
244
245static const char *qcom_geni_serial_get_type(struct uart_port *uport)
246{
247 return "MSM";
248}
249
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600250static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600251{
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600252 struct qcom_geni_serial_port *port;
253 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
254
255 if (line < 0 || line >= nr_ports)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600256 return ERR_PTR(-ENXIO);
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600257
258 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
259 return port;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600260}
261
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100262static bool qcom_geni_serial_main_active(struct uart_port *uport)
263{
264 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE;
265}
266
267static bool qcom_geni_serial_secondary_active(struct uart_port *uport)
268{
269 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE;
270}
271
Douglas Andersonb26d1ad2024-09-06 15:13:33 +0200272static bool qcom_geni_serial_poll_bitfield(struct uart_port *uport,
273 unsigned int offset, u32 field, u32 val)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600274{
275 u32 reg;
276 struct qcom_geni_serial_port *port;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600277 unsigned long timeout_us = 20000;
Douglas Andersone42d6c32020-06-26 13:00:32 -0700278 struct qcom_geni_private_data *private_data = uport->private_data;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600279
Douglas Andersone42d6c32020-06-26 13:00:32 -0700280 if (private_data->drv) {
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100281 port = to_dev_port(uport);
Johan Hovoldc80ee362024-09-06 15:13:29 +0200282 if (port->poll_timeout_us)
283 timeout_us = port->poll_timeout_us;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600284 }
285
Karthikeyan Ramasubramanian43f18312018-05-03 14:14:40 -0600286 /*
287 * Use custom implementation instead of readl_poll_atomic since ktimer
288 * is not ready at the time of early console.
289 */
290 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
291 while (timeout_us) {
Ryan Case9e06d552019-01-07 17:58:35 -0800292 reg = readl(uport->membase + offset);
Douglas Andersonb26d1ad2024-09-06 15:13:33 +0200293 if ((reg & field) == val)
Karthikeyan Ramasubramanian43f18312018-05-03 14:14:40 -0600294 return true;
295 udelay(10);
296 timeout_us -= 10;
297 }
298 return false;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600299}
300
Douglas Andersonb26d1ad2024-09-06 15:13:33 +0200301static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
302 unsigned int offset, u32 field, bool set)
303{
304 return qcom_geni_serial_poll_bitfield(uport, offset, field, set ? field : 0);
305}
306
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600307static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
308{
309 u32 m_cmd;
310
Ryan Case9e06d552019-01-07 17:58:35 -0800311 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600312 m_cmd = UART_START_TX << M_OPCODE_SHFT;
313 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
314}
315
316static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
317{
318 int done;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600319
320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
321 M_CMD_DONE_EN, true);
322 if (!done) {
Ryan Case9e06d552019-01-07 17:58:35 -0800323 writel(M_GENI_CMD_ABORT, uport->membase +
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600324 SE_GENI_M_CMD_CTRL_REG);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600325 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
326 M_CMD_ABORT_EN, true);
Johan Hovoldf97cdbbf2024-09-06 15:13:30 +0200327 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600328 }
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600329}
330
331static void qcom_geni_serial_abort_rx(struct uart_port *uport)
332{
333 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
334
335 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
336 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
337 S_GENI_CMD_ABORT, false);
Ryan Case9e06d552019-01-07 17:58:35 -0800338 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
339 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600340}
341
342#ifdef CONFIG_CONSOLE_POLL
343static int qcom_geni_serial_get_char(struct uart_port *uport)
344{
Douglas Andersone42d6c32020-06-26 13:00:32 -0700345 struct qcom_geni_private_data *private_data = uport->private_data;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600346 u32 status;
Douglas Andersone42d6c32020-06-26 13:00:32 -0700347 u32 word_cnt;
348 int ret;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600349
Douglas Andersone42d6c32020-06-26 13:00:32 -0700350 if (!private_data->poll_cached_bytes_cnt) {
351 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
352 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600353
Douglas Andersone42d6c32020-06-26 13:00:32 -0700354 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
355 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600356
Douglas Andersone42d6c32020-06-26 13:00:32 -0700357 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
358 word_cnt = status & RX_FIFO_WC_MSK;
359 if (!word_cnt)
360 return NO_POLL_CHAR;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600361
Douglas Andersone42d6c32020-06-26 13:00:32 -0700362 if (word_cnt == 1 && (status & RX_LAST))
Douglas Andersond681a6e2020-08-06 22:19:08 -0700363 /*
364 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
365 * treated as if it was BYTES_PER_FIFO_WORD.
366 */
Douglas Andersone42d6c32020-06-26 13:00:32 -0700367 private_data->poll_cached_bytes_cnt =
368 (status & RX_LAST_BYTE_VALID_MSK) >>
369 RX_LAST_BYTE_VALID_SHFT;
Douglas Andersond681a6e2020-08-06 22:19:08 -0700370
371 if (private_data->poll_cached_bytes_cnt == 0)
372 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
Douglas Andersone42d6c32020-06-26 13:00:32 -0700373
374 private_data->poll_cached_bytes =
375 readl(uport->membase + SE_GENI_RX_FIFOn);
376 }
377
378 private_data->poll_cached_bytes_cnt--;
379 ret = private_data->poll_cached_bytes & 0xff;
380 private_data->poll_cached_bytes >>= 8;
381
382 return ret;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600383}
384
385static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
386 unsigned char c)
387{
Johan Hovold63d14d92024-09-06 15:13:36 +0200388 if (qcom_geni_serial_main_active(uport)) {
389 qcom_geni_serial_poll_tx_done(uport);
390 __qcom_geni_serial_cancel_tx_cmd(uport);
391 }
392
Johan Hovoldf97cdbbf2024-09-06 15:13:30 +0200393 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600394 qcom_geni_serial_setup_tx(uport, 1);
Ryan Case9e06d552019-01-07 17:58:35 -0800395 writel(c, uport->membase + SE_GENI_TX_FIFOn);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600396 qcom_geni_serial_poll_tx_done(uport);
397}
398#endif
399
400#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
Johan Hovoldcc4a0e52024-09-06 15:13:34 +0200401static void qcom_geni_serial_drain_fifo(struct uart_port *uport)
402{
403 struct qcom_geni_serial_port *port = to_dev_port(uport);
404
405 qcom_geni_serial_poll_bitfield(uport, SE_GENI_M_GP_LENGTH, GP_LENGTH,
406 port->tx_queued);
407}
408
Jiri Slaby3f8bab12022-03-03 09:08:31 +0100409static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600410{
Douglas Anderson650c8bd2020-06-26 13:00:33 -0700411 struct qcom_geni_private_data *private_data = uport->private_data;
412
413 private_data->write_cached_bytes =
414 (private_data->write_cached_bytes >> 8) | (ch << 24);
415 private_data->write_cached_bytes_cnt++;
416
417 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
418 writel(private_data->write_cached_bytes,
419 uport->membase + SE_GENI_TX_FIFOn);
420 private_data->write_cached_bytes_cnt = 0;
421 }
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600422}
423
424static void
425__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
426 unsigned int count)
427{
Douglas Anderson650c8bd2020-06-26 13:00:33 -0700428 struct qcom_geni_private_data *private_data = uport->private_data;
429
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600430 int i;
431 u32 bytes_to_send = count;
432
433 for (i = 0; i < count; i++) {
Karthikeyan Ramasubramanianf0262562018-05-03 14:14:33 -0600434 /*
435 * uart_console_write() adds a carriage return for each newline.
436 * Account for additional bytes to be written.
437 */
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600438 if (s[i] == '\n')
439 bytes_to_send++;
440 }
441
Ryan Case9e06d552019-01-07 17:58:35 -0800442 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
Johan Hovoldf97cdbbf2024-09-06 15:13:30 +0200443 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600444 qcom_geni_serial_setup_tx(uport, bytes_to_send);
445 for (i = 0; i < count; ) {
446 size_t chars_to_write = 0;
447 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
448
449 /*
450 * If the WM bit never set, then the Tx state machine is not
451 * in a valid state, so break, cancel/abort any existing
452 * command. Unfortunately the current data being written is
453 * lost.
454 */
455 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
456 M_TX_FIFO_WATERMARK_EN, true))
457 break;
Karthikeyan Ramasubramanian6a106352018-05-03 14:14:34 -0600458 chars_to_write = min_t(size_t, count - i, avail / 2);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600459 uart_console_write(uport, s + i, chars_to_write,
460 qcom_geni_serial_wr_char);
Ryan Case9e06d552019-01-07 17:58:35 -0800461 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600462 SE_GENI_M_IRQ_CLEAR);
463 i += chars_to_write;
464 }
Douglas Anderson650c8bd2020-06-26 13:00:33 -0700465
466 if (private_data->write_cached_bytes_cnt) {
467 private_data->write_cached_bytes >>= BITS_PER_BYTE *
468 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
469 writel(private_data->write_cached_bytes,
470 uport->membase + SE_GENI_TX_FIFOn);
471 private_data->write_cached_bytes_cnt = 0;
472 }
473
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600474 qcom_geni_serial_poll_tx_done(uport);
475}
476
477static void qcom_geni_serial_console_write(struct console *co, const char *s,
478 unsigned int count)
479{
480 struct uart_port *uport;
481 struct qcom_geni_serial_port *port;
Johan Hovold6f3c3ca2024-09-06 15:13:35 +0200482 u32 m_irq_en, s_irq_en;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600483 bool locked = true;
484 unsigned long flags;
485
486 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
487
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600488 port = get_port_from_line(co->index, true);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600489 if (IS_ERR(port))
490 return;
491
492 uport = &port->uport;
493 if (oops_in_progress)
Thomas Gleixnerb8ba915d2023-09-14 20:44:06 +0206494 locked = uart_port_trylock_irqsave(uport, &flags);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600495 else
Thomas Gleixnerb8ba915d2023-09-14 20:44:06 +0206496 uart_port_lock_irqsave(uport, &flags);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600497
Johan Hovold6f3c3ca2024-09-06 15:13:35 +0200498 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
499 s_irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
500 writel(0, uport->membase + SE_GENI_M_IRQ_EN);
501 writel(0, uport->membase + SE_GENI_S_IRQ_EN);
502
Johan Hovoldcc4a0e52024-09-06 15:13:34 +0200503 if (qcom_geni_serial_main_active(uport)) {
504 /* Wait for completion or drain FIFO */
505 if (!locked || port->tx_remaining == 0)
506 qcom_geni_serial_poll_tx_done(uport);
507 else
508 qcom_geni_serial_drain_fifo(uport);
Ryan Casea1fee892018-11-29 18:18:40 -0800509
Johan Hovoldcc4a0e52024-09-06 15:13:34 +0200510 qcom_geni_serial_cancel_tx_cmd(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600511 }
512
513 __qcom_geni_serial_console_write(uport, s, count);
Ryan Casea1fee892018-11-29 18:18:40 -0800514
Johan Hovold6f3c3ca2024-09-06 15:13:35 +0200515 writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN);
516 writel(s_irq_en, uport->membase + SE_GENI_S_IRQ_EN);
517
Johan Hovoldcc4a0e52024-09-06 15:13:34 +0200518 if (locked)
Thomas Gleixnerb8ba915d2023-09-14 20:44:06 +0206519 uart_port_unlock_irqrestore(uport, flags);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600520}
521
Bartosz Golaszewski0626afe2022-12-29 16:50:27 +0100522static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600523{
524 u32 i;
525 unsigned char buf[sizeof(u32)];
526 struct tty_port *tport;
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100527 struct qcom_geni_serial_port *port = to_dev_port(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600528
529 tport = &uport->state->port;
530 for (i = 0; i < bytes; ) {
531 int c;
Douglas Anderson650c8bd2020-06-26 13:00:33 -0700532 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600533
534 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
535 i += chunk;
536 if (drop)
537 continue;
538
539 for (c = 0; c < chunk; c++) {
540 int sysrq;
541
542 uport->icount.rx++;
543 if (port->brk && buf[c] == 0) {
544 port->brk = false;
545 if (uart_handle_break(uport))
546 continue;
547 }
548
Douglas Anderson336447b2018-10-30 15:11:05 -0700549 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
Douglas Andersonbabeca82018-10-30 15:11:03 -0700550
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600551 if (!sysrq)
552 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
553 }
554 }
555 if (!drop)
556 tty_flip_buffer_push(tport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600557}
558#else
Bartosz Golaszewski0626afe2022-12-29 16:50:27 +0100559static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600560{
Bartosz Golaszewski0626afe2022-12-29 16:50:27 +0100561
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600562}
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600563#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
564
Bartosz Golaszewski0626afe2022-12-29 16:50:27 +0100565static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600566{
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100567 struct qcom_geni_serial_port *port = to_dev_port(uport);
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100568 struct tty_port *tport = &uport->state->port;
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600569 int ret;
570
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100571 ret = tty_insert_flip_string(tport, port->rx_buf, bytes);
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600572 if (ret != bytes) {
573 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
574 __func__, ret, bytes);
575 WARN_ON_ONCE(1);
576 }
577 uport->icount.rx += ret;
578 tty_flip_buffer_push(tport);
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -0600579}
580
Bartosz Golaszewskid0fabb02022-12-29 16:50:18 +0100581static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
582{
583 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
584}
585
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100586static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600587{
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100588 struct qcom_geni_serial_port *port = to_dev_port(uport);
589 bool done;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600590
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100591 if (!qcom_geni_serial_main_active(uport))
Ryan Casebdc05a82019-01-07 17:58:37 -0800592 return;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600593
Johan Hovold95fcfc02023-03-07 17:44:03 +0100594 if (port->tx_dma_addr) {
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100595 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr,
596 port->tx_remaining);
597 port->tx_dma_addr = 0;
598 port->tx_remaining = 0;
599 }
600
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100601 geni_se_cancel_m_cmd(&port->se);
602
Vijaya Krishna Nivarthi9c844132023-08-09 16:23:13 +0530603 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
604 M_CMD_CANCEL_EN, true);
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100605 if (!done) {
606 geni_se_abort_m_cmd(&port->se);
607 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
608 M_CMD_ABORT_EN, true);
609 if (!done)
610 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set");
611 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
612 }
613
614 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
615}
616
617static void qcom_geni_serial_start_tx_dma(struct uart_port *uport)
618{
619 struct qcom_geni_serial_port *port = to_dev_port(uport);
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200620 struct tty_port *tport = &uport->state->port;
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100621 unsigned int xmit_size;
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200622 u8 *tail;
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100623 int ret;
624
625 if (port->tx_dma_addr)
626 return;
627
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200628 if (kfifo_is_empty(&tport->xmit_fifo))
Johan Hovold97820782023-03-07 17:44:04 +0100629 return;
630
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200631 xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail,
632 UART_XMIT_SIZE);
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100633
634 qcom_geni_serial_setup_tx(uport, xmit_size);
635
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200636 ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size,
637 &port->tx_dma_addr);
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100638 if (ret) {
639 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret);
640 qcom_geni_serial_stop_tx_dma(uport);
641 return;
642 }
643
644 port->tx_remaining = xmit_size;
645}
646
647static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport)
648{
Johan Hovold947cc4e2024-07-04 12:18:03 +0200649 unsigned char c;
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100650 u32 irq_en;
651
Johan Hovold947cc4e2024-07-04 12:18:03 +0200652 /*
653 * Start a new transfer in case the previous command was cancelled and
654 * left data in the FIFO which may prevent the watermark interrupt
655 * from triggering. Note that the stale data is discarded.
656 */
657 if (!qcom_geni_serial_main_active(uport) &&
658 !qcom_geni_serial_tx_empty(uport)) {
659 if (uart_fifo_out(uport, &c, 1) == 1) {
660 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
661 qcom_geni_serial_setup_tx(uport, 1);
662 writel(c, uport->membase + SE_GENI_TX_FIFOn);
663 }
664 }
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600665
Ryan Casebdc05a82019-01-07 17:58:37 -0800666 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
667 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
Ryan Casebdc05a82019-01-07 17:58:37 -0800668 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
669 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600670}
671
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100672static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600673{
674 u32 irq_en;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600675
Ryan Case9e06d552019-01-07 17:58:35 -0800676 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
Ryan Casebdc05a82019-01-07 17:58:37 -0800677 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
678 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
Ryan Case9e06d552019-01-07 17:58:35 -0800679 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
Johan Hovold947cc4e2024-07-04 12:18:03 +0200680}
681
Johan Hovold63d14d92024-09-06 15:13:36 +0200682static void __qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport)
Johan Hovold947cc4e2024-07-04 12:18:03 +0200683{
684 struct qcom_geni_serial_port *port = to_dev_port(uport);
685
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600686 geni_se_cancel_m_cmd(&port->se);
687 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
688 M_CMD_CANCEL_EN, true)) {
689 geni_se_abort_m_cmd(&port->se);
690 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
691 M_CMD_ABORT_EN, true);
Ryan Case9e06d552019-01-07 17:58:35 -0800692 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600693 }
Ryan Case9e06d552019-01-07 17:58:35 -0800694 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
Johan Hovold63d14d92024-09-06 15:13:36 +0200695}
696
697static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport)
698{
699 struct qcom_geni_serial_port *port = to_dev_port(uport);
700
701 if (!qcom_geni_serial_main_active(uport))
702 return;
703
704 __qcom_geni_serial_cancel_tx_cmd(uport);
Johan Hovold947cc4e2024-07-04 12:18:03 +0200705
706 port->tx_remaining = 0;
Johan Hovoldcc4a0e52024-09-06 15:13:34 +0200707 port->tx_queued = 0;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600708}
709
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100710static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600711{
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600712 u32 status;
Bartosz Golaszewskid0fabb02022-12-29 16:50:18 +0100713 u32 word_cnt;
714 u32 last_word_byte_cnt;
715 u32 last_word_partial;
716 u32 total_bytes;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600717
Bartosz Golaszewskid0fabb02022-12-29 16:50:18 +0100718 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
719 word_cnt = status & RX_FIFO_WC_MSK;
720 last_word_partial = status & RX_LAST;
721 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
722 RX_LAST_BYTE_VALID_SHFT;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600723
Bartosz Golaszewskid0fabb02022-12-29 16:50:18 +0100724 if (!word_cnt)
725 return;
726 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
727 if (last_word_partial && last_word_byte_cnt)
728 total_bytes += last_word_byte_cnt;
729 else
730 total_bytes += BYTES_PER_FIFO_WORD;
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100731 handle_rx_console(uport, total_bytes, drop);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600732}
733
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100734static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600735{
736 u32 irq_en;
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100737 struct qcom_geni_serial_port *port = to_dev_port(uport);
satya priya679aac52020-02-11 15:43:02 +0530738 u32 s_irq_status;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600739
Ryan Casebdc05a82019-01-07 17:58:37 -0800740 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
741 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
742 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600743
Ryan Casebdc05a82019-01-07 17:58:37 -0800744 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
745 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
746 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600747
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100748 if (!qcom_geni_serial_secondary_active(uport))
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600749 return;
750
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600751 geni_se_cancel_s_cmd(&port->se);
satya priya679aac52020-02-11 15:43:02 +0530752 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
753 S_CMD_CANCEL_EN, true);
754 /*
755 * If timeout occurs secondary engine remains active
756 * and Abort sequence is executed.
757 */
758 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
759 /* Flush the Rx buffer */
760 if (s_irq_status & S_RX_FIFO_LAST_EN)
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100761 qcom_geni_serial_handle_rx_fifo(uport, true);
satya priya679aac52020-02-11 15:43:02 +0530762 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
763
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100764 if (qcom_geni_serial_secondary_active(uport))
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600765 qcom_geni_serial_abort_rx(uport);
766}
767
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100768static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600769{
Bartosz Golaszewskid0fabb02022-12-29 16:50:18 +0100770 u32 irq_en;
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100771 struct qcom_geni_serial_port *port = to_dev_port(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600772
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100773 if (qcom_geni_serial_secondary_active(uport))
774 qcom_geni_serial_stop_rx_fifo(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600775
Bartosz Golaszewskid0fabb02022-12-29 16:50:18 +0100776 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
777
778 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
779 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
780 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
781
782 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
783 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
784 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600785}
786
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100787static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport)
788{
789 struct qcom_geni_serial_port *port = to_dev_port(uport);
790
791 if (!qcom_geni_serial_secondary_active(uport))
792 return;
793
794 geni_se_cancel_s_cmd(&port->se);
795 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
796 S_CMD_CANCEL_EN, true);
797
798 if (qcom_geni_serial_secondary_active(uport))
799 qcom_geni_serial_abort_rx(uport);
800
801 if (port->rx_dma_addr) {
802 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr,
803 DMA_RX_BUF_SIZE);
804 port->rx_dma_addr = 0;
805 }
806}
807
808static void qcom_geni_serial_start_rx_dma(struct uart_port *uport)
809{
810 struct qcom_geni_serial_port *port = to_dev_port(uport);
811 int ret;
812
813 if (qcom_geni_serial_secondary_active(uport))
814 qcom_geni_serial_stop_rx_dma(uport);
815
816 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN);
817
818 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,
819 DMA_RX_BUF_SIZE,
820 &port->rx_dma_addr);
821 if (ret) {
822 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);
823 qcom_geni_serial_stop_rx_dma(uport);
824 }
825}
826
827static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop)
828{
829 struct qcom_geni_serial_port *port = to_dev_port(uport);
830 u32 rx_in;
831 int ret;
832
833 if (!qcom_geni_serial_secondary_active(uport))
834 return;
835
836 if (!port->rx_dma_addr)
837 return;
838
839 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE);
840 port->rx_dma_addr = 0;
841
842 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN);
843 if (!rx_in) {
844 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n");
845 return;
846 }
847
848 if (!drop)
849 handle_rx_uart(uport, rx_in, drop);
850
851 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,
852 DMA_RX_BUF_SIZE,
853 &port->rx_dma_addr);
854 if (ret) {
855 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);
856 qcom_geni_serial_stop_rx_dma(uport);
857 }
858}
859
860static void qcom_geni_serial_start_rx(struct uart_port *uport)
861{
862 uport->ops->start_rx(uport);
863}
864
865static void qcom_geni_serial_stop_rx(struct uart_port *uport)
866{
867 uport->ops->stop_rx(uport);
868}
869
870static void qcom_geni_serial_stop_tx(struct uart_port *uport)
871{
872 uport->ops->stop_tx(uport);
873}
874
Bartosz Golaszewskibd795582022-12-29 16:50:26 +0100875static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport,
Douglas Anderson3d9319c22024-03-04 17:49:53 -0800876 unsigned int chunk)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600877{
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100878 struct qcom_geni_serial_port *port = to_dev_port(uport);
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200879 unsigned int tx_bytes, remaining = chunk;
Bartosz Golaszewskibd795582022-12-29 16:50:26 +0100880 u8 buf[BYTES_PER_FIFO_WORD];
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600881
Bartosz Golaszewskibd795582022-12-29 16:50:26 +0100882 while (remaining) {
Dan Carpenter3550f892020-06-24 16:27:44 +0300883 memset(buf, 0, sizeof(buf));
Bartosz Golaszewskibd795582022-12-29 16:50:26 +0100884 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD);
Matthias Kaehlcke3c66eb42018-12-19 10:17:47 -0800885
Johan Hovold2ac33972024-07-04 12:18:05 +0200886 uart_fifo_out(uport, buf, tx_bytes);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600887
Karthikeyan Ramasubramanian69736b52018-05-03 14:14:38 -0600888 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600889
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600890 remaining -= tx_bytes;
Ryan Casea1fee892018-11-29 18:18:40 -0800891 port->tx_remaining -= tx_bytes;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600892 }
Bartosz Golaszewskid420fb492022-12-29 16:50:25 +0100893}
894
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100895static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport,
896 bool done, bool active)
Bartosz Golaszewskid420fb492022-12-29 16:50:25 +0100897{
898 struct qcom_geni_serial_port *port = to_dev_port(uport);
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200899 struct tty_port *tport = &uport->state->port;
Bartosz Golaszewskid420fb492022-12-29 16:50:25 +0100900 size_t avail;
901 size_t pending;
902 u32 status;
903 u32 irq_en;
904 unsigned int chunk;
905
906 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
907
908 /* Complete the current tx command before taking newly added data */
909 if (active)
910 pending = port->tx_remaining;
911 else
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200912 pending = kfifo_len(&tport->xmit_fifo);
Bartosz Golaszewskid420fb492022-12-29 16:50:25 +0100913
Johan Hovold507786c2024-07-04 12:18:04 +0200914 /* All data has been transmitted or command has been cancelled */
915 if (!pending && done) {
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100916 qcom_geni_serial_stop_tx_fifo(uport);
Bartosz Golaszewskid420fb492022-12-29 16:50:25 +0100917 goto out_write_wakeup;
918 }
919
Johan Hovold507786c2024-07-04 12:18:04 +0200920 if (active)
921 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
922 else
923 avail = port->tx_fifo_depth;
924
Bartosz Golaszewskid420fb492022-12-29 16:50:25 +0100925 avail *= BYTES_PER_FIFO_WORD;
926
927 chunk = min(avail, pending);
928 if (!chunk)
929 goto out_write_wakeup;
930
Johan Hovold63d14d92024-09-06 15:13:36 +0200931 if (!active) {
Bartosz Golaszewskid420fb492022-12-29 16:50:25 +0100932 qcom_geni_serial_setup_tx(uport, pending);
933 port->tx_remaining = pending;
Johan Hovoldcc4a0e52024-09-06 15:13:34 +0200934 port->tx_queued = 0;
Bartosz Golaszewskid420fb492022-12-29 16:50:25 +0100935
936 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
937 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
938 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
939 uport->membase + SE_GENI_M_IRQ_EN);
940 }
941
Bartosz Golaszewskibd795582022-12-29 16:50:26 +0100942 qcom_geni_serial_send_chunk_fifo(uport, chunk);
Johan Hovoldcc4a0e52024-09-06 15:13:34 +0200943 port->tx_queued += chunk;
Ryan Case64a42802018-12-13 11:43:20 -0800944
945 /*
946 * The tx fifo watermark is level triggered and latched. Though we had
947 * cleared it in qcom_geni_serial_isr it will have already reasserted
948 * so we must clear it again here after our writes.
949 */
Ryan Case9e06d552019-01-07 17:58:35 -0800950 writel(M_TX_FIFO_WATERMARK_EN,
Ryan Case64a42802018-12-13 11:43:20 -0800951 uport->membase + SE_GENI_M_IRQ_CLEAR);
952
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600953out_write_wakeup:
Ryan Case64a42802018-12-13 11:43:20 -0800954 if (!port->tx_remaining) {
Ryan Case9e06d552019-01-07 17:58:35 -0800955 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
Ryan Case64a42802018-12-13 11:43:20 -0800956 if (irq_en & M_TX_FIFO_WATERMARK_EN)
Ryan Case9e06d552019-01-07 17:58:35 -0800957 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
Ryan Case64a42802018-12-13 11:43:20 -0800958 uport->membase + SE_GENI_M_IRQ_EN);
959 }
960
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200961 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
Evan Green638a6f42018-05-09 13:44:29 -0700962 uart_write_wakeup(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600963}
964
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100965static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport)
966{
967 struct qcom_geni_serial_port *port = to_dev_port(uport);
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200968 struct tty_port *tport = &uport->state->port;
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100969
970 uart_xmit_advance(uport, port->tx_remaining);
971 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining);
972 port->tx_dma_addr = 0;
973 port->tx_remaining = 0;
974
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200975 if (!kfifo_is_empty(&tport->xmit_fifo))
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100976 qcom_geni_serial_start_tx_dma(uport);
977
Jiri Slaby (SUSE)1788cf6a2024-04-05 08:08:23 +0200978 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100979 uart_write_wakeup(uport);
980}
981
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600982static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
983{
Ryan Case385298a2019-01-07 17:58:38 -0800984 u32 m_irq_en;
985 u32 m_irq_status;
986 u32 s_irq_status;
987 u32 geni_status;
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +0100988 u32 dma;
989 u32 dma_tx_status;
990 u32 dma_rx_status;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600991 struct uart_port *uport = dev;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600992 bool drop_rx = false;
993 struct tty_port *tport = &uport->state->port;
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +0100994 struct qcom_geni_serial_port *port = to_dev_port(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600995
996 if (uport->suspended)
Karthikeyan Ramasubramanianec91df82018-05-03 14:14:39 -0600997 return IRQ_NONE;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -0600998
Thomas Gleixnerb8ba915d2023-09-14 20:44:06 +0206999 uart_port_lock(uport);
Johan Hovold75f4e832021-04-16 16:05:55 +02001000
Ryan Case9e06d552019-01-07 17:58:35 -08001001 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
1002 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001003 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT);
1004 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT);
Ryan Case9e06d552019-01-07 17:58:35 -08001005 geni_status = readl(uport->membase + SE_GENI_STATUS);
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001006 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN);
Ryan Case9e06d552019-01-07 17:58:35 -08001007 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
1008 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
1009 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001010 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR);
1011 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001012
1013 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
1014 goto out_unlock;
1015
1016 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
1017 uport->icount.overrun++;
1018 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1019 }
1020
Bartosz Golaszewskife6a00e2022-12-29 16:50:23 +01001021 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) {
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001022 if (s_irq_status & S_GP_IRQ_0_EN)
1023 uport->icount.parity++;
1024 drop_rx = true;
Bartosz Golaszewskife6a00e2022-12-29 16:50:23 +01001025 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) {
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001026 uport->icount.brk++;
1027 port->brk = true;
1028 }
1029
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001030 if (dma) {
1031 if (dma_tx_status & TX_DMA_DONE)
1032 qcom_geni_serial_handle_tx_dma(uport);
1033
1034 if (dma_rx_status) {
1035 if (dma_rx_status & RX_RESET_DONE)
1036 goto out_unlock;
1037
1038 if (dma_rx_status & RX_DMA_PARITY_ERR) {
1039 uport->icount.parity++;
1040 drop_rx = true;
1041 }
1042
1043 if (dma_rx_status & RX_DMA_BREAK)
1044 uport->icount.brk++;
1045
1046 if (dma_rx_status & (RX_DMA_DONE | RX_EOT))
1047 qcom_geni_serial_handle_rx_dma(uport, drop_rx);
1048 }
1049 } else {
1050 if (m_irq_status & m_irq_en &
1051 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
1052 qcom_geni_serial_handle_tx_fifo(uport,
1053 m_irq_status & M_CMD_DONE_EN,
1054 geni_status & M_GENI_CMD_ACTIVE);
1055
1056 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN))
1057 qcom_geni_serial_handle_rx_fifo(uport, drop_rx);
1058 }
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001059
1060out_unlock:
Johan Hovold75f4e832021-04-16 16:05:55 +02001061 uart_unlock_and_check_sysrq(uport);
Douglas Anderson336447b2018-10-30 15:11:05 -07001062
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001063 return IRQ_HANDLED;
1064}
1065
Krzysztof Kozlowskib8caf692022-12-21 17:40:22 +01001066static int setup_fifos(struct qcom_geni_serial_port *port)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001067{
1068 struct uart_port *uport;
Krzysztof Kozlowskib8caf692022-12-21 17:40:22 +01001069 u32 old_rx_fifo_depth = port->rx_fifo_depth;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001070
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001071 uport = &port->uport;
1072 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
1073 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
1074 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
1075 uport->fifosize =
1076 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
Krzysztof Kozlowskib8caf692022-12-21 17:40:22 +01001077
Ilpo Järvinena3cf6b92023-01-23 19:38:56 +02001078 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) {
James Clark9e6aa7c2023-05-09 10:49:41 +01001079 /*
1080 * Use krealloc rather than krealloc_array because rx_buf is
1081 * accessed as 1 byte entries as well as 4 byte entries so it's
1082 * not necessarily an array.
1083 */
Ilpo Järvinena3cf6b92023-01-23 19:38:56 +02001084 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf,
1085 port->rx_fifo_depth * sizeof(u32),
1086 GFP_KERNEL);
1087 if (!port->rx_buf)
Krzysztof Kozlowskib8caf692022-12-21 17:40:22 +01001088 return -ENOMEM;
1089 }
1090
1091 return 0;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001092}
1093
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001094
1095static void qcom_geni_serial_shutdown(struct uart_port *uport)
1096{
Akash Asthana3e4aaea2019-10-10 15:16:03 +05301097 disable_irq(uport->irq);
Johan Hovold9aff74c2023-03-07 17:44:02 +01001098
Bartosz Golaszewskid8aca2f2022-12-29 16:50:17 +01001099 qcom_geni_serial_stop_tx(uport);
1100 qcom_geni_serial_stop_rx(uport);
Johan Hovold947cc4e2024-07-04 12:18:03 +02001101
1102 qcom_geni_serial_cancel_tx_cmd(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001103}
1104
Johan Hovold507786c2024-07-04 12:18:04 +02001105static void qcom_geni_serial_flush_buffer(struct uart_port *uport)
1106{
1107 qcom_geni_serial_cancel_tx_cmd(uport);
1108}
1109
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001110static int qcom_geni_serial_port_setup(struct uart_port *uport)
1111{
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +01001112 struct qcom_geni_serial_port *port = to_dev_port(uport);
Ryan Case385298a2019-01-07 17:58:38 -08001113 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
Douglas Andersonc3622722018-09-05 13:11:46 -07001114 u32 proto;
Roja Rani Yarubandi9fa3c4b2020-03-04 16:52:03 +05301115 u32 pin_swap;
Krzysztof Kozlowskib8caf692022-12-21 17:40:22 +01001116 int ret;
Douglas Andersonc3622722018-09-05 13:11:46 -07001117
Douglas Andersonc3622722018-09-05 13:11:46 -07001118 proto = geni_se_read_proto(&port->se);
1119 if (proto != GENI_SE_UART) {
1120 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
1121 return -ENXIO;
1122 }
1123
1124 qcom_geni_serial_stop_rx(uport);
1125
Krzysztof Kozlowskib8caf692022-12-21 17:40:22 +01001126 ret = setup_fifos(port);
1127 if (ret)
1128 return ret;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001129
Ryan Case9e06d552019-01-07 17:58:35 -08001130 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
Roja Rani Yarubandi9fa3c4b2020-03-04 16:52:03 +05301131
1132 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
1133 if (port->rx_tx_swap) {
1134 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
1135 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
1136 }
1137 if (port->cts_rts_swap) {
1138 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
1139 pin_swap |= IO_MACRO_IO0_SEL;
1140 }
1141 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
1142 if (port->rx_tx_swap || port->cts_rts_swap)
1143 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
1144
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001145 /*
1146 * Make an unconditional cancel on the main sequencer to reset
1147 * it else we could end up in data loss scenarios.
1148 */
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001149 if (uart_console(uport))
1150 qcom_geni_serial_poll_tx_done(uport);
Douglas Anderson650c8bd2020-06-26 13:00:33 -07001151 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1152 false, true, true);
Ryan Casea85fb9c2019-01-07 17:58:36 -08001153 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001154 geni_se_select_mode(&port->se, port->dev_data->mode);
Aniket Randive35781d82022-10-07 11:53:00 +05301155 qcom_geni_serial_start_rx(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001156 port->setup = true;
Douglas Andersonc3622722018-09-05 13:11:46 -07001157
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001158 return 0;
1159}
1160
1161static int qcom_geni_serial_startup(struct uart_port *uport)
1162{
1163 int ret;
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +01001164 struct qcom_geni_serial_port *port = to_dev_port(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001165
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001166 if (!port->setup) {
1167 ret = qcom_geni_serial_port_setup(uport);
1168 if (ret)
1169 return ret;
1170 }
Akash Asthana3e4aaea2019-10-10 15:16:03 +05301171 enable_irq(uport->irq);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001172
Akash Asthana3e4aaea2019-10-10 15:16:03 +05301173 return 0;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001174}
1175
Vijaya Krishna Nivarthic474c772022-07-16 00:25:43 +05301176static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk,
1177 unsigned int *clk_div, unsigned int percent_tol)
1178{
1179 unsigned long freq;
1180 unsigned long div, maxdiv;
1181 u64 mult;
1182 unsigned long offset, abs_tol, achieved;
1183
1184 abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
1185 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
1186 div = 1;
1187 while (div <= maxdiv) {
1188 mult = (u64)div * desired_clk;
1189 if (mult != (unsigned long)mult)
1190 break;
1191
1192 offset = div * abs_tol;
1193 freq = clk_round_rate(clk, mult - offset);
1194
1195 /* Can only get lower if we're done */
1196 if (freq < mult - offset)
1197 break;
1198
1199 /*
1200 * Re-calculate div in case rounding skipped rates but we
1201 * ended up at a good one, then check for a match.
1202 */
1203 div = DIV_ROUND_CLOSEST(freq, desired_clk);
1204 achieved = DIV_ROUND_CLOSEST(freq, div);
1205 if (achieved <= desired_clk + abs_tol &&
1206 achieved >= desired_clk - abs_tol) {
1207 *clk_div = div;
1208 return freq;
1209 }
1210
1211 div = DIV_ROUND_UP(freq, desired_clk);
1212 }
1213
1214 return 0;
1215}
1216
Vijaya Krishna Nivarthic2194bc2022-05-16 16:08:30 +05301217static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
Vivek Gautamce734602019-08-01 17:41:53 +05301218 unsigned int sampling_rate, unsigned int *clk_div)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001219{
1220 unsigned long ser_clk;
1221 unsigned long desired_clk;
1222
Vivek Gautamce734602019-08-01 17:41:53 +05301223 desired_clk = baud * sampling_rate;
Vijaya Krishna Nivarthic474c772022-07-16 00:25:43 +05301224 if (!desired_clk)
Vijaya Krishna Nivarthic2194bc2022-05-16 16:08:30 +05301225 return 0;
Vijaya Krishna Nivarthic2194bc2022-05-16 16:08:30 +05301226
Vijaya Krishna Nivarthic474c772022-07-16 00:25:43 +05301227 /*
1228 * try to find a clock rate within 2% tolerance, then within 5%
1229 */
1230 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2);
1231 if (!ser_clk)
1232 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5);
Vijaya Krishna Nivarthic2194bc2022-05-16 16:08:30 +05301233
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001234 return ser_clk;
1235}
1236
1237static void qcom_geni_serial_set_termios(struct uart_port *uport,
Ilpo Järvinenbec5b812022-08-16 14:57:37 +03001238 struct ktermios *termios,
1239 const struct ktermios *old)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001240{
1241 unsigned int baud;
Ryan Case385298a2019-01-07 17:58:38 -08001242 u32 bits_per_char;
1243 u32 tx_trans_cfg;
1244 u32 tx_parity_cfg;
1245 u32 rx_trans_cfg;
1246 u32 rx_parity_cfg;
1247 u32 stop_bit_len;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001248 unsigned int clk_div;
Ryan Case385298a2019-01-07 17:58:38 -08001249 u32 ser_clk_cfg;
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +01001250 struct qcom_geni_serial_port *port = to_dev_port(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001251 unsigned long clk_rate;
Vivek Gautamce734602019-08-01 17:41:53 +05301252 u32 ver, sampling_rate;
Akash Asthana7cf563b2020-06-23 16:08:53 +05301253 unsigned int avg_bw_core;
Johan Hovoldc80ee362024-09-06 15:13:29 +02001254 unsigned long timeout;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001255
1256 qcom_geni_serial_stop_rx(uport);
1257 /* baud rate */
1258 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
Vivek Gautamce734602019-08-01 17:41:53 +05301259
1260 sampling_rate = UART_OVERSAMPLING;
1261 /* Sampling rate is halved for IP versions >= 2.5 */
1262 ver = geni_se_get_qup_hw_version(&port->se);
Paras Sharmac9ca43d2020-09-30 11:35:26 +05301263 if (ver >= QUP_SE_VERSION_2_5)
Vivek Gautamce734602019-08-01 17:41:53 +05301264 sampling_rate /= 2;
1265
Vijaya Krishna Nivarthic2194bc2022-05-16 16:08:30 +05301266 clk_rate = get_clk_div_rate(port->se.clk, baud,
1267 sampling_rate, &clk_div);
Vijaya Krishna Nivarthic474c772022-07-16 00:25:43 +05301268 if (!clk_rate) {
1269 dev_err(port->se.dev,
Douglas Anderson0fec5182022-08-02 13:23:09 -07001270 "Couldn't find suitable clock rate for %u\n",
Vijaya Krishna Nivarthic474c772022-07-16 00:25:43 +05301271 baud * sampling_rate);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001272 goto out_restart_rx;
Vijaya Krishna Nivarthic474c772022-07-16 00:25:43 +05301273 }
1274
Johan Hovold18536cc2023-07-14 15:02:14 +02001275 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",
Vijaya Krishna Nivarthic474c772022-07-16 00:25:43 +05301276 baud * sampling_rate, clk_rate, clk_div);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001277
1278 uport->uartclk = clk_rate;
Johan Hovold8ece7b72023-07-14 15:02:13 +02001279 port->clk_rate = clk_rate;
Rajendra Nayaka5819b52020-06-15 17:32:39 +05301280 dev_pm_opp_set_rate(uport->dev, clk_rate);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001281 ser_clk_cfg = SER_CLK_EN;
1282 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1283
Akash Asthana7cf563b2020-06-23 16:08:53 +05301284 /*
1285 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1286 * only.
1287 */
1288 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1289 : GENI_DEFAULT_BW;
1290 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1291 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1292 geni_icc_set_bw(&port->se);
1293
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001294 /* parity */
Ryan Case9e06d552019-01-07 17:58:35 -08001295 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1296 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1297 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1298 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001299 if (termios->c_cflag & PARENB) {
1300 tx_trans_cfg |= UART_TX_PAR_EN;
1301 rx_trans_cfg |= UART_RX_PAR_EN;
1302 tx_parity_cfg |= PAR_CALC_EN;
1303 rx_parity_cfg |= PAR_CALC_EN;
1304 if (termios->c_cflag & PARODD) {
1305 tx_parity_cfg |= PAR_ODD;
1306 rx_parity_cfg |= PAR_ODD;
1307 } else if (termios->c_cflag & CMSPAR) {
1308 tx_parity_cfg |= PAR_SPACE;
1309 rx_parity_cfg |= PAR_SPACE;
1310 } else {
1311 tx_parity_cfg |= PAR_EVEN;
1312 rx_parity_cfg |= PAR_EVEN;
1313 }
1314 } else {
1315 tx_trans_cfg &= ~UART_TX_PAR_EN;
1316 rx_trans_cfg &= ~UART_RX_PAR_EN;
1317 tx_parity_cfg &= ~PAR_CALC_EN;
1318 rx_parity_cfg &= ~PAR_CALC_EN;
1319 }
1320
1321 /* bits per char */
Jiri Slaby3ec2ff32021-06-10 11:02:47 +02001322 bits_per_char = tty_get_char_size(termios->c_cflag);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001323
1324 /* stop bits */
1325 if (termios->c_cflag & CSTOPB)
1326 stop_bit_len = TX_STOP_BIT_LEN_2;
1327 else
1328 stop_bit_len = TX_STOP_BIT_LEN_1;
1329
1330 /* flow control, clear the CTS_MASK bit if using flow control. */
1331 if (termios->c_cflag & CRTSCTS)
1332 tx_trans_cfg &= ~UART_CTS_MASK;
1333 else
1334 tx_trans_cfg |= UART_CTS_MASK;
1335
Johan Hovoldc80ee362024-09-06 15:13:29 +02001336 if (baud) {
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001337 uart_update_timeout(uport, termios->c_cflag, baud);
1338
Johan Hovoldc80ee362024-09-06 15:13:29 +02001339 /*
1340 * Make sure that qcom_geni_serial_poll_bitfield() waits for
1341 * the FIFO, two-word intermediate transfer register and shift
1342 * register to clear.
1343 *
1344 * Note that uart_fifo_timeout() also adds a 20 ms margin.
1345 */
1346 timeout = jiffies_to_usecs(uart_fifo_timeout(uport));
1347 timeout += 3 * timeout / port->tx_fifo_depth;
1348 WRITE_ONCE(port->poll_timeout_us, timeout);
1349 }
1350
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001351 if (!uart_console(uport))
Ryan Case9e06d552019-01-07 17:58:35 -08001352 writel(port->loopback,
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001353 uport->membase + SE_UART_LOOPBACK_CFG);
Ryan Case9e06d552019-01-07 17:58:35 -08001354 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1355 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1356 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1357 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1358 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1359 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1360 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1361 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1362 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001363out_restart_rx:
1364 qcom_geni_serial_start_rx(uport);
1365}
1366
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001367#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
John Stultz975efc62020-08-11 02:50:44 +00001368static int qcom_geni_console_setup(struct console *co, char *options)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001369{
1370 struct uart_port *uport;
1371 struct qcom_geni_serial_port *port;
Douglas Anderson2ec812a2020-09-11 08:00:57 -07001372 int baud = 115200;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001373 int bits = 8;
1374 int parity = 'n';
1375 int flow = 'n';
Douglas Andersonc3622722018-09-05 13:11:46 -07001376 int ret;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001377
1378 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1379 return -ENXIO;
1380
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001381 port = get_port_from_line(co->index, true);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001382 if (IS_ERR(port)) {
Karthikeyan Ramasubramanian6a106352018-05-03 14:14:34 -06001383 pr_err("Invalid line %d\n", co->index);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001384 return PTR_ERR(port);
1385 }
1386
1387 uport = &port->uport;
1388
1389 if (unlikely(!uport->membase))
1390 return -ENXIO;
1391
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001392 if (!port->setup) {
Douglas Andersonc3622722018-09-05 13:11:46 -07001393 ret = qcom_geni_serial_port_setup(uport);
1394 if (ret)
1395 return ret;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001396 }
1397
1398 if (options)
1399 uart_parse_options(options, &baud, &parity, &bits, &flow);
1400
1401 return uart_set_options(uport, co, baud, parity, bits, flow);
1402}
1403
Karthikeyan Ramasubramanian43f18312018-05-03 14:14:40 -06001404static void qcom_geni_serial_earlycon_write(struct console *con,
1405 const char *s, unsigned int n)
1406{
1407 struct earlycon_device *dev = con->data;
1408
1409 __qcom_geni_serial_console_write(&dev->port, s, n);
1410}
1411
Douglas Anderson205b5bd2020-05-07 13:08:48 -07001412#ifdef CONFIG_CONSOLE_POLL
1413static int qcom_geni_serial_earlycon_read(struct console *con,
1414 char *s, unsigned int n)
1415{
1416 struct earlycon_device *dev = con->data;
1417 struct uart_port *uport = &dev->port;
1418 int num_read = 0;
1419 int ch;
1420
1421 while (num_read < n) {
1422 ch = qcom_geni_serial_get_char(uport);
1423 if (ch == NO_POLL_CHAR)
1424 break;
1425 s[num_read++] = ch;
1426 }
1427
1428 return num_read;
1429}
1430
1431static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1432 struct console *con)
1433{
1434 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1435 con->read = qcom_geni_serial_earlycon_read;
1436}
1437#else
1438static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1439 struct console *con) { }
1440#endif
1441
Douglas Andersone42d6c32020-06-26 13:00:32 -07001442static struct qcom_geni_private_data earlycon_private_data;
1443
Karthikeyan Ramasubramanian43f18312018-05-03 14:14:40 -06001444static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1445 const char *opt)
1446{
1447 struct uart_port *uport = &dev->port;
1448 u32 tx_trans_cfg;
1449 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1450 u32 rx_trans_cfg = 0;
1451 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1452 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1453 u32 bits_per_char;
1454 struct geni_se se;
1455
1456 if (!uport->membase)
1457 return -EINVAL;
1458
Douglas Andersone42d6c32020-06-26 13:00:32 -07001459 uport->private_data = &earlycon_private_data;
1460
Karthikeyan Ramasubramanian43f18312018-05-03 14:14:40 -06001461 memset(&se, 0, sizeof(se));
1462 se.base = uport->membase;
1463 if (geni_se_read_proto(&se) != GENI_SE_UART)
1464 return -ENXIO;
1465 /*
1466 * Ignore Flow control.
1467 * n = 8.
1468 */
1469 tx_trans_cfg = UART_CTS_MASK;
1470 bits_per_char = BITS_PER_BYTE;
1471
1472 /*
1473 * Make an unconditional cancel on the main sequencer to reset
1474 * it else we could end up in data loss scenarios.
1475 */
1476 qcom_geni_serial_poll_tx_done(uport);
1477 qcom_geni_serial_abort_rx(uport);
Douglas Anderson650c8bd2020-06-26 13:00:33 -07001478 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1479 false, true, true);
Karthikeyan Ramasubramanian43f18312018-05-03 14:14:40 -06001480 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1481 geni_se_select_mode(&se, GENI_SE_FIFO);
1482
Ryan Case9e06d552019-01-07 17:58:35 -08001483 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1484 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1485 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1486 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1487 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1488 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1489 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
Karthikeyan Ramasubramanian43f18312018-05-03 14:14:40 -06001490
1491 dev->con->write = qcom_geni_serial_earlycon_write;
1492 dev->con->setup = NULL;
Douglas Anderson205b5bd2020-05-07 13:08:48 -07001493 qcom_geni_serial_enable_early_read(&se, dev->con);
1494
Karthikeyan Ramasubramanian43f18312018-05-03 14:14:40 -06001495 return 0;
1496}
1497OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1498 qcom_geni_serial_earlycon_setup);
1499
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001500static int __init console_register(struct uart_driver *drv)
1501{
1502 return uart_register_driver(drv);
1503}
1504
1505static void console_unregister(struct uart_driver *drv)
1506{
1507 uart_unregister_driver(drv);
1508}
1509
1510static struct console cons_ops = {
1511 .name = "ttyMSM",
1512 .write = qcom_geni_serial_console_write,
1513 .device = uart_console_device,
1514 .setup = qcom_geni_console_setup,
1515 .flags = CON_PRINTBUFFER,
1516 .index = -1,
1517 .data = &qcom_geni_console_driver,
1518};
1519
1520static struct uart_driver qcom_geni_console_driver = {
1521 .owner = THIS_MODULE,
1522 .driver_name = "qcom_geni_console",
1523 .dev_name = "ttyMSM",
1524 .nr = GENI_UART_CONS_PORTS,
1525 .cons = &cons_ops,
1526};
1527#else
1528static int console_register(struct uart_driver *drv)
1529{
1530 return 0;
1531}
1532
1533static void console_unregister(struct uart_driver *drv)
1534{
1535}
1536#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1537
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001538static struct uart_driver qcom_geni_uart_driver = {
1539 .owner = THIS_MODULE,
1540 .driver_name = "qcom_geni_uart",
1541 .dev_name = "ttyHS",
1542 .nr = GENI_UART_PORTS,
1543};
1544
1545static void qcom_geni_serial_pm(struct uart_port *uport,
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001546 unsigned int new_state, unsigned int old_state)
1547{
Bartosz Golaszewski00ce7c62022-12-29 16:50:21 +01001548 struct qcom_geni_serial_port *port = to_dev_port(uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001549
Douglas Andersonc3622722018-09-05 13:11:46 -07001550 /* If we've never been called, treat it as off */
1551 if (old_state == UART_PM_STATE_UNDEFINED)
1552 old_state = UART_PM_STATE_OFF;
1553
Akash Asthana7cf563b2020-06-23 16:08:53 +05301554 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1555 geni_icc_enable(&port->se);
Johan Hovold8ece7b72023-07-14 15:02:13 +02001556 if (port->clk_rate)
1557 dev_pm_opp_set_rate(uport->dev, port->clk_rate);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001558 geni_se_resources_on(&port->se);
Akash Asthana7cf563b2020-06-23 16:08:53 +05301559 } else if (new_state == UART_PM_STATE_OFF &&
1560 old_state == UART_PM_STATE_ON) {
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001561 geni_se_resources_off(&port->se);
Johan Hovold8ece7b72023-07-14 15:02:13 +02001562 dev_pm_opp_set_rate(uport->dev, 0);
Akash Asthana7cf563b2020-06-23 16:08:53 +05301563 geni_icc_disable(&port->se);
1564 }
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001565}
1566
1567static const struct uart_ops qcom_geni_console_pops = {
1568 .tx_empty = qcom_geni_serial_tx_empty,
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001569 .stop_tx = qcom_geni_serial_stop_tx_fifo,
1570 .start_tx = qcom_geni_serial_start_tx_fifo,
1571 .stop_rx = qcom_geni_serial_stop_rx_fifo,
1572 .start_rx = qcom_geni_serial_start_rx_fifo,
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001573 .set_termios = qcom_geni_serial_set_termios,
1574 .startup = qcom_geni_serial_startup,
1575 .request_port = qcom_geni_serial_request_port,
1576 .config_port = qcom_geni_serial_config_port,
1577 .shutdown = qcom_geni_serial_shutdown,
Johan Hovold507786c2024-07-04 12:18:04 +02001578 .flush_buffer = qcom_geni_serial_flush_buffer,
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001579 .type = qcom_geni_serial_get_type,
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001580 .set_mctrl = qcom_geni_serial_set_mctrl,
1581 .get_mctrl = qcom_geni_serial_get_mctrl,
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001582#ifdef CONFIG_CONSOLE_POLL
1583 .poll_get_char = qcom_geni_serial_get_char,
1584 .poll_put_char = qcom_geni_serial_poll_put_char,
Douglas Andersond8851a92023-03-16 13:20:57 -07001585 .poll_init = qcom_geni_serial_port_setup,
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001586#endif
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001587 .pm = qcom_geni_serial_pm,
1588};
1589
1590static const struct uart_ops qcom_geni_uart_pops = {
1591 .tx_empty = qcom_geni_serial_tx_empty,
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001592 .stop_tx = qcom_geni_serial_stop_tx_dma,
1593 .start_tx = qcom_geni_serial_start_tx_dma,
1594 .start_rx = qcom_geni_serial_start_rx_dma,
1595 .stop_rx = qcom_geni_serial_stop_rx_dma,
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001596 .set_termios = qcom_geni_serial_set_termios,
1597 .startup = qcom_geni_serial_startup,
1598 .request_port = qcom_geni_serial_request_port,
1599 .config_port = qcom_geni_serial_config_port,
1600 .shutdown = qcom_geni_serial_shutdown,
1601 .type = qcom_geni_serial_get_type,
1602 .set_mctrl = qcom_geni_serial_set_mctrl,
1603 .get_mctrl = qcom_geni_serial_get_mctrl,
1604 .pm = qcom_geni_serial_pm,
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001605};
1606
1607static int qcom_geni_serial_probe(struct platform_device *pdev)
1608{
1609 int ret = 0;
Colin Ian King71581242021-04-23 09:13:17 +01001610 int line;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001611 struct qcom_geni_serial_port *port;
1612 struct uart_port *uport;
1613 struct resource *res;
Karthikeyan Ramasubramanian066cd1c2018-04-06 18:49:00 -06001614 int irq;
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001615 struct uart_driver *drv;
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001616 const struct qcom_geni_device_data *data;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001617
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001618 data = of_device_get_match_data(&pdev->dev);
1619 if (!data)
1620 return -EINVAL;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001621
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001622 if (data->console) {
Geert Uytterhoeven2843cbb2018-08-23 23:30:27 +02001623 drv = &qcom_geni_console_driver;
1624 line = of_alias_get_id(pdev->dev.of_node, "serial");
1625 } else {
1626 drv = &qcom_geni_uart_driver;
Dmitry Baryshkov08b0adb2021-06-22 00:15:28 +03001627 line = of_alias_get_id(pdev->dev.of_node, "serial");
1628 if (line == -ENODEV) /* compat with non-standard aliases */
1629 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001630 }
1631
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001632 port = get_port_from_line(line, data->console);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001633 if (IS_ERR(port)) {
Karthikeyan Ramasubramanian6a106352018-05-03 14:14:34 -06001634 dev_err(&pdev->dev, "Invalid line %d\n", line);
1635 return PTR_ERR(port);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001636 }
1637
1638 uport = &port->uport;
1639 /* Don't allow 2 drivers to access the same port */
1640 if (uport->private_data)
1641 return -ENODEV;
1642
1643 uport->dev = &pdev->dev;
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001644 port->dev_data = data;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001645 port->se.dev = &pdev->dev;
1646 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1647 port->se.clk = devm_clk_get(&pdev->dev, "se");
1648 if (IS_ERR(port->se.clk)) {
1649 ret = PTR_ERR(port->se.clk);
1650 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1651 return ret;
1652 }
1653
1654 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Wei Yongjun7693b332018-03-22 02:25:07 +00001655 if (!res)
1656 return -EINVAL;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001657 uport->mapbase = res->start;
1658
1659 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1660 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1661 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1662
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001663 if (!data->console) {
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001664 port->rx_buf = devm_kzalloc(uport->dev,
1665 DMA_RX_BUF_SIZE, GFP_KERNEL);
1666 if (!port->rx_buf)
satya priyaf9d690b2020-03-06 12:17:07 +05301667 return -ENOMEM;
1668 }
1669
Akash Asthana7cf563b2020-06-23 16:08:53 +05301670 ret = geni_icc_get(&port->se, NULL);
1671 if (ret)
1672 return ret;
1673 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1674 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1675
1676 /* Set BW for register access */
1677 ret = geni_icc_set_bw(&port->se);
1678 if (ret)
1679 return ret;
1680
Akash Asthanaf3974412020-01-06 20:15:04 +05301681 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1682 "qcom_geni_serial_%s%d",
1683 uart_console(uport) ? "console" : "uart", uport->line);
1684 if (!port->name)
1685 return -ENOMEM;
1686
Karthikeyan Ramasubramanian066cd1c2018-04-06 18:49:00 -06001687 irq = platform_get_irq(pdev, 0);
Stephen Boyd1df21782019-07-30 11:15:44 -07001688 if (irq < 0)
Karthikeyan Ramasubramanian066cd1c2018-04-06 18:49:00 -06001689 return irq;
Karthikeyan Ramasubramanian066cd1c2018-04-06 18:49:00 -06001690 uport->irq = irq;
Dmitry Safonov8f122692019-12-13 00:06:34 +00001691 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001692
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001693 if (!data->console)
Akash Asthanaf3974412020-01-06 20:15:04 +05301694 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
Akash Asthana3e4aaea2019-10-10 15:16:03 +05301695
Roja Rani Yarubandi9fa3c4b2020-03-04 16:52:03 +05301696 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1697 port->rx_tx_swap = true;
1698
1699 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1700 port->cts_rts_swap = true;
1701
Yangtao Li300894a62021-03-14 19:34:00 +03001702 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1703 if (ret)
1704 return ret;
Rajendra Nayaka5819b52020-06-15 17:32:39 +05301705 /* OPP table is optional */
Yangtao Li300894a62021-03-14 19:34:00 +03001706 ret = devm_pm_opp_of_add_table(&pdev->dev);
Viresh Kumarc7ac46d2020-08-28 11:37:52 +05301707 if (ret && ret != -ENODEV) {
Rajendra Nayaka5819b52020-06-15 17:32:39 +05301708 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
Yangtao Li300894a62021-03-14 19:34:00 +03001709 return ret;
Rajendra Nayaka5819b52020-06-15 17:32:39 +05301710 }
1711
Douglas Andersone42d6c32020-06-26 13:00:32 -07001712 port->private_data.drv = drv;
1713 uport->private_data = &port->private_data;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001714 platform_set_drvdata(pdev, port);
Akash Asthanaf3974412020-01-06 20:15:04 +05301715
Akash Asthanaf3974412020-01-06 20:15:04 +05301716 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1717 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1718 IRQF_TRIGGER_HIGH, port->name, uport);
1719 if (ret) {
1720 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
Yangtao Li300894a62021-03-14 19:34:00 +03001721 return ret;
Akash Asthanaf3974412020-01-06 20:15:04 +05301722 }
1723
Krzysztof Kozlowski5f949f12023-05-05 17:23:01 +02001724 ret = uart_add_one_port(drv, uport);
1725 if (ret)
1726 return ret;
1727
Akash Asthanaf3974412020-01-06 20:15:04 +05301728 if (port->wakeup_irq > 0) {
1729 device_init_wakeup(&pdev->dev, true);
1730 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1731 port->wakeup_irq);
1732 if (ret) {
1733 device_init_wakeup(&pdev->dev, false);
1734 uart_remove_one_port(drv, uport);
Yangtao Li300894a62021-03-14 19:34:00 +03001735 return ret;
Akash Asthanaf3974412020-01-06 20:15:04 +05301736 }
1737 }
1738
1739 return 0;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001740}
1741
Uwe Kleine-Königdd4d4492023-11-10 16:29:59 +01001742static void qcom_geni_serial_remove(struct platform_device *pdev)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001743{
1744 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
Douglas Andersone42d6c32020-06-26 13:00:32 -07001745 struct uart_driver *drv = port->private_data.drv;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001746
Akash Asthanaf3974412020-01-06 20:15:04 +05301747 dev_pm_clear_wake_irq(&pdev->dev);
1748 device_init_wakeup(&pdev->dev, false);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001749 uart_remove_one_port(drv, &port->uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001750}
1751
Arnd Bergmann5342ab02022-12-15 17:54:24 +01001752static int qcom_geni_serial_sys_suspend(struct device *dev)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001753{
Wolfram Sanga406c4b2018-04-19 16:06:23 +02001754 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001755 struct uart_port *uport = &port->uport;
Douglas Andersone42d6c32020-06-26 13:00:32 -07001756 struct qcom_geni_private_data *private_data = uport->private_data;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001757
Rajendra Nayak4a3107f2020-07-14 11:01:49 +05301758 /*
1759 * This is done so we can hit the lowest possible state in suspend
1760 * even with no_console_suspend
1761 */
1762 if (uart_console(uport)) {
Vijaya Krishna Nivarthi408e5322022-09-07 21:01:42 +05301763 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);
Rajendra Nayak4a3107f2020-07-14 11:01:49 +05301764 geni_icc_set_bw(&port->se);
1765 }
Douglas Andersone42d6c32020-06-26 13:00:32 -07001766 return uart_suspend_port(private_data->drv, uport);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001767}
1768
Arnd Bergmann5342ab02022-12-15 17:54:24 +01001769static int qcom_geni_serial_sys_resume(struct device *dev)
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001770{
Rajendra Nayak4a3107f2020-07-14 11:01:49 +05301771 int ret;
Wolfram Sanga406c4b2018-04-19 16:06:23 +02001772 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001773 struct uart_port *uport = &port->uport;
Douglas Andersone42d6c32020-06-26 13:00:32 -07001774 struct qcom_geni_private_data *private_data = uport->private_data;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001775
Rajendra Nayak4a3107f2020-07-14 11:01:49 +05301776 ret = uart_resume_port(private_data->drv, uport);
1777 if (uart_console(uport)) {
Vijaya Krishna Nivarthi408e5322022-09-07 21:01:42 +05301778 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
Rajendra Nayak4a3107f2020-07-14 11:01:49 +05301779 geni_icc_set_bw(&port->se);
1780 }
1781 return ret;
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001782}
1783
Aniket Randive35781d82022-10-07 11:53:00 +05301784static int qcom_geni_serial_sys_hib_resume(struct device *dev)
1785{
1786 int ret = 0;
1787 struct uart_port *uport;
1788 struct qcom_geni_private_data *private_data;
1789 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1790
1791 uport = &port->uport;
1792 private_data = uport->private_data;
1793
1794 if (uart_console(uport)) {
Johan Hovold51273792023-07-11 18:05:16 +02001795 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
Aniket Randive35781d82022-10-07 11:53:00 +05301796 geni_icc_set_bw(&port->se);
1797 ret = uart_resume_port(private_data->drv, uport);
1798 /*
1799 * For hibernation usecase clients for
1800 * console UART won't call port setup during restore,
1801 * hence call port setup for console uart.
1802 */
1803 qcom_geni_serial_port_setup(uport);
1804 } else {
1805 /*
1806 * Peripheral register settings are lost during hibernation.
1807 * Update setup flag such that port setup happens again
1808 * during next session. Clients of HS-UART will close and
1809 * open the port during hibernation.
1810 */
1811 port->setup = false;
1812 }
1813 return ret;
1814}
1815
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001816static const struct qcom_geni_device_data qcom_geni_console_data = {
1817 .console = true,
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001818 .mode = GENI_SE_FIFO,
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001819};
1820
1821static const struct qcom_geni_device_data qcom_geni_uart_data = {
1822 .console = false,
Bartosz Golaszewski2aaa43c2022-12-29 16:50:30 +01001823 .mode = GENI_SE_DMA,
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001824};
1825
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001826static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
Arnd Bergmann5342ab02022-12-15 17:54:24 +01001827 .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1828 .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume),
1829 .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1830 .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1831 .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume),
1832 .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume),
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001833};
1834
1835static const struct of_device_id qcom_geni_serial_match_table[] = {
Bartosz Golaszewski40ec6d42022-12-29 16:50:28 +01001836 {
1837 .compatible = "qcom,geni-debug-uart",
1838 .data = &qcom_geni_console_data,
1839 },
1840 {
1841 .compatible = "qcom,geni-uart",
1842 .data = &qcom_geni_uart_data,
1843 },
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001844 {}
1845};
1846MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1847
1848static struct platform_driver qcom_geni_serial_platform_driver = {
Uwe Kleine-Königdd4d4492023-11-10 16:29:59 +01001849 .remove_new = qcom_geni_serial_remove,
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001850 .probe = qcom_geni_serial_probe,
1851 .driver = {
1852 .name = "qcom_geni_serial",
1853 .of_match_table = qcom_geni_serial_match_table,
1854 .pm = &qcom_geni_serial_pm_ops,
1855 },
1856};
1857
1858static int __init qcom_geni_serial_init(void)
1859{
1860 int ret;
1861
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001862 ret = console_register(&qcom_geni_console_driver);
1863 if (ret)
1864 return ret;
1865
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001866 ret = uart_register_driver(&qcom_geni_uart_driver);
1867 if (ret) {
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001868 console_unregister(&qcom_geni_console_driver);
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001869 return ret;
1870 }
1871
1872 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1873 if (ret) {
1874 console_unregister(&qcom_geni_console_driver);
1875 uart_unregister_driver(&qcom_geni_uart_driver);
1876 }
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001877 return ret;
1878}
1879module_init(qcom_geni_serial_init);
1880
1881static void __exit qcom_geni_serial_exit(void)
1882{
1883 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1884 console_unregister(&qcom_geni_console_driver);
Girish Mahadevan8a8a66a2018-07-13 16:17:35 -06001885 uart_unregister_driver(&qcom_geni_uart_driver);
Karthikeyan Ramasubramanianc4f52872018-03-14 17:58:49 -06001886}
1887module_exit(qcom_geni_serial_exit);
1888
1889MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1890MODULE_LICENSE("GPL v2");