David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 1 | /* |
David Hardeman | abda5c8 | 2005-09-01 22:34:53 +0200 | [diff] [blame] | 2 | * i6300esb: Watchdog timer driver for Intel 6300ESB chipset |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 3 | * |
| 4 | * (c) Copyright 2004 Google Inc. |
Jan Engelhardt | 96de0e2 | 2007-10-19 23:21:04 +0200 | [diff] [blame] | 5 | * (c) Copyright 2005 David Härdeman <david@2gen.com> |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License |
| 9 | * as published by the Free Software Foundation; either version |
| 10 | * 2 of the License, or (at your option) any later version. |
| 11 | * |
Wim Van Sebroeck | 7944d3a | 2008-08-06 20:19:41 +0000 | [diff] [blame] | 12 | * based on i810-tco.c which is in turn based on softdog.c |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 13 | * |
Wim Van Sebroeck | 7944d3a | 2008-08-06 20:19:41 +0000 | [diff] [blame] | 14 | * The timer is implemented in the following I/O controller hubs: |
| 15 | * (See the intel documentation on http://developer.intel.com.) |
Wim Van Sebroeck | 0426fd0 | 2009-03-19 19:02:44 +0000 | [diff] [blame] | 16 | * 6300ESB chip : document number 300641-004 |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 17 | * |
| 18 | * 2004YYZZ Ross Biro |
| 19 | * Initial version 0.01 |
| 20 | * 2004YYZZ Ross Biro |
Wim Van Sebroeck | 7944d3a | 2008-08-06 20:19:41 +0000 | [diff] [blame] | 21 | * Version 0.02 |
Jan Engelhardt | 96de0e2 | 2007-10-19 23:21:04 +0200 | [diff] [blame] | 22 | * 20050210 David Härdeman <david@2gen.com> |
Wim Van Sebroeck | 7944d3a | 2008-08-06 20:19:41 +0000 | [diff] [blame] | 23 | * Ported driver to kernel 2.6 |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 24 | * 20171016 Radu Rendec <rrendec@arista.com> |
| 25 | * Change driver to use the watchdog subsystem |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 26 | * Add support for multiple 6300ESB devices |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 27 | */ |
| 28 | |
| 29 | /* |
| 30 | * Includes, defines, variables, module parameters, ... |
| 31 | */ |
| 32 | |
| 33 | #include <linux/module.h> |
| 34 | #include <linux/types.h> |
| 35 | #include <linux/kernel.h> |
| 36 | #include <linux/fs.h> |
| 37 | #include <linux/mm.h> |
| 38 | #include <linux/miscdevice.h> |
| 39 | #include <linux/watchdog.h> |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 40 | #include <linux/pci.h> |
| 41 | #include <linux/ioport.h> |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 42 | #include <linux/uaccess.h> |
| 43 | #include <linux/io.h> |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 44 | |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 45 | /* Module and version information */ |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 46 | #define ESB_MODULE_NAME "i6300ESB timer" |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 47 | |
David Hardeman | abda5c8 | 2005-09-01 22:34:53 +0200 | [diff] [blame] | 48 | /* PCI configuration registers */ |
| 49 | #define ESB_CONFIG_REG 0x60 /* Config register */ |
| 50 | #define ESB_LOCK_REG 0x68 /* WDT lock register */ |
| 51 | |
| 52 | /* Memory mapped registers */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 53 | #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */ |
| 54 | #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */ |
| 55 | #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */ |
| 56 | #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */ |
David Hardeman | abda5c8 | 2005-09-01 22:34:53 +0200 | [diff] [blame] | 57 | |
| 58 | /* Lock register bits */ |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 59 | #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */ |
| 60 | #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */ |
| 61 | #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */ |
David Hardeman | abda5c8 | 2005-09-01 22:34:53 +0200 | [diff] [blame] | 62 | |
| 63 | /* Config register bits */ |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 64 | #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */ |
| 65 | #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */ |
Wim Van Sebroeck | 39f3be7 | 2010-03-08 11:02:38 +0000 | [diff] [blame] | 66 | #define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */ |
David Hardeman | abda5c8 | 2005-09-01 22:34:53 +0200 | [diff] [blame] | 67 | |
| 68 | /* Reload register bits */ |
Wim Van Sebroeck | 31838d9d | 2009-03-25 19:14:45 +0000 | [diff] [blame] | 69 | #define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */ |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 70 | #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */ |
David Hardeman | abda5c8 | 2005-09-01 22:34:53 +0200 | [diff] [blame] | 71 | |
| 72 | /* Magic constants */ |
| 73 | #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ |
| 74 | #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */ |
| 75 | |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 76 | /* module parameters */ |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 77 | /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */ |
Radu Rendec | 568d601 | 2017-10-26 17:10:15 +0100 | [diff] [blame] | 78 | #define ESB_HEARTBEAT_MIN 1 |
| 79 | #define ESB_HEARTBEAT_MAX 2046 |
| 80 | #define ESB_HEARTBEAT_DEFAULT 30 |
| 81 | #define ESB_HEARTBEAT_RANGE __MODULE_STRING(ESB_HEARTBEAT_MIN) \ |
| 82 | "<heartbeat<" __MODULE_STRING(ESB_HEARTBEAT_MAX) |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 83 | static int heartbeat; /* in seconds */ |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 84 | module_param(heartbeat, int, 0); |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 85 | MODULE_PARM_DESC(heartbeat, |
Radu Rendec | 568d601 | 2017-10-26 17:10:15 +0100 | [diff] [blame] | 86 | "Watchdog heartbeat in seconds. (" ESB_HEARTBEAT_RANGE |
| 87 | ", default=" __MODULE_STRING(ESB_HEARTBEAT_DEFAULT) ")"); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 88 | |
Wim Van Sebroeck | 86a1e18 | 2012-03-05 16:51:11 +0100 | [diff] [blame] | 89 | static bool nowayout = WATCHDOG_NOWAYOUT; |
| 90 | module_param(nowayout, bool, 0); |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 91 | MODULE_PARM_DESC(nowayout, |
| 92 | "Watchdog cannot be stopped once started (default=" |
| 93 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 94 | |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 95 | /* internal variables */ |
| 96 | struct esb_dev { |
| 97 | struct watchdog_device wdd; |
| 98 | void __iomem *base; |
| 99 | struct pci_dev *pdev; |
| 100 | }; |
| 101 | |
| 102 | #define to_esb_dev(wptr) container_of(wptr, struct esb_dev, wdd) |
| 103 | |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 104 | /* |
| 105 | * Some i6300ESB specific functions |
| 106 | */ |
| 107 | |
| 108 | /* |
| 109 | * Prepare for reloading the timer by unlocking the proper registers. |
| 110 | * This is performed by first writing 0x80 followed by 0x86 to the |
| 111 | * reload register. After this the appropriate registers can be written |
| 112 | * to once before they need to be unlocked again. |
| 113 | */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 114 | static inline void esb_unlock_registers(struct esb_dev *edev) |
Wim Van Sebroeck | 7944d3a | 2008-08-06 20:19:41 +0000 | [diff] [blame] | 115 | { |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 116 | writew(ESB_UNLOCK1, ESB_RELOAD_REG(edev)); |
| 117 | writew(ESB_UNLOCK2, ESB_RELOAD_REG(edev)); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 118 | } |
| 119 | |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 120 | static int esb_timer_start(struct watchdog_device *wdd) |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 121 | { |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 122 | struct esb_dev *edev = to_esb_dev(wdd); |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 123 | int _wdd_nowayout = test_bit(WDOG_NO_WAY_OUT, &wdd->status); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 124 | u8 val; |
| 125 | |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 126 | esb_unlock_registers(edev); |
| 127 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev)); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 128 | /* Enable or Enable + Lock? */ |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 129 | val = ESB_WDT_ENABLE | (_wdd_nowayout ? ESB_WDT_LOCK : 0x00); |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 130 | pci_write_config_byte(edev->pdev, ESB_LOCK_REG, val); |
Wim Van Sebroeck | 3b9d49e | 2009-03-23 13:50:38 +0000 | [diff] [blame] | 131 | return 0; |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 132 | } |
| 133 | |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 134 | static int esb_timer_stop(struct watchdog_device *wdd) |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 135 | { |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 136 | struct esb_dev *edev = to_esb_dev(wdd); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 137 | u8 val; |
| 138 | |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 139 | /* First, reset timers as suggested by the docs */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 140 | esb_unlock_registers(edev); |
| 141 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev)); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 142 | /* Then disable the WDT */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 143 | pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x0); |
| 144 | pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 145 | |
| 146 | /* Returns 0 if the timer was disabled, non-zero otherwise */ |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 147 | return val & ESB_WDT_ENABLE; |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 148 | } |
| 149 | |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 150 | static int esb_timer_keepalive(struct watchdog_device *wdd) |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 151 | { |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 152 | struct esb_dev *edev = to_esb_dev(wdd); |
| 153 | |
| 154 | esb_unlock_registers(edev); |
| 155 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev)); |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 156 | /* FIXME: Do we need to flush anything here? */ |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 157 | return 0; |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 158 | } |
| 159 | |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 160 | static int esb_timer_set_heartbeat(struct watchdog_device *wdd, |
| 161 | unsigned int time) |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 162 | { |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 163 | struct esb_dev *edev = to_esb_dev(wdd); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 164 | u32 val; |
| 165 | |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 166 | /* We shift by 9, so if we are passed a value of 1 sec, |
| 167 | * val will be 1 << 9 = 512, then write that to two |
| 168 | * timers => 2 * 512 = 1024 (which is decremented at 1KHz) |
| 169 | */ |
| 170 | val = time << 9; |
| 171 | |
| 172 | /* Write timer 1 */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 173 | esb_unlock_registers(edev); |
| 174 | writel(val, ESB_TIMER1_REG(edev)); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 175 | |
| 176 | /* Write timer 2 */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 177 | esb_unlock_registers(edev); |
| 178 | writel(val, ESB_TIMER2_REG(edev)); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 179 | |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 180 | /* Reload */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 181 | esb_unlock_registers(edev); |
| 182 | writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev)); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 183 | |
| 184 | /* FIXME: Do we need to flush everything out? */ |
| 185 | |
| 186 | /* Done */ |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 187 | wdd->timeout = time; |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 188 | return 0; |
| 189 | } |
| 190 | |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 191 | /* |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 192 | * Watchdog Subsystem Interfaces |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 193 | */ |
| 194 | |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 195 | static struct watchdog_info esb_info = { |
| 196 | .identity = ESB_MODULE_NAME, |
| 197 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 198 | }; |
| 199 | |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 200 | static const struct watchdog_ops esb_ops = { |
| 201 | .owner = THIS_MODULE, |
| 202 | .start = esb_timer_start, |
| 203 | .stop = esb_timer_stop, |
| 204 | .set_timeout = esb_timer_set_heartbeat, |
| 205 | .ping = esb_timer_keepalive, |
| 206 | }; |
| 207 | |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 208 | /* |
| 209 | * Data for PCI driver interface |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 210 | */ |
Jingoo Han | bc17f9d | 2013-12-03 08:30:22 +0900 | [diff] [blame] | 211 | static const struct pci_device_id esb_pci_tbl[] = { |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 212 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), }, |
| 213 | { 0, }, /* End of list */ |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 214 | }; |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 215 | MODULE_DEVICE_TABLE(pci, esb_pci_tbl); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 216 | |
| 217 | /* |
| 218 | * Init & exit routines |
| 219 | */ |
| 220 | |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 221 | static unsigned char esb_getdevice(struct esb_dev *edev) |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 222 | { |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 223 | if (pci_enable_device(edev->pdev)) { |
| 224 | dev_err(&edev->pdev->dev, "failed to enable device\n"); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 225 | goto err_devput; |
| 226 | } |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 227 | |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 228 | if (pci_request_region(edev->pdev, 0, ESB_MODULE_NAME)) { |
| 229 | dev_err(&edev->pdev->dev, "failed to request region\n"); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 230 | goto err_disable; |
| 231 | } |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 232 | |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 233 | edev->base = pci_ioremap_bar(edev->pdev, 0); |
| 234 | if (edev->base == NULL) { |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 235 | /* Something's wrong here, BASEADDR has to be set */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 236 | dev_err(&edev->pdev->dev, "failed to get BASEADDR\n"); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 237 | goto err_release; |
| 238 | } |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 239 | |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 240 | /* Done */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 241 | dev_set_drvdata(&edev->pdev->dev, edev); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 242 | return 1; |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 243 | |
| 244 | err_release: |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 245 | pci_release_region(edev->pdev, 0); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 246 | err_disable: |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 247 | pci_disable_device(edev->pdev); |
Naveen Gupta | 811f999 | 2005-08-21 13:02:41 +0200 | [diff] [blame] | 248 | err_devput: |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 249 | return 0; |
| 250 | } |
| 251 | |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 252 | static void esb_initdevice(struct esb_dev *edev) |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 253 | { |
| 254 | u8 val1; |
| 255 | u16 val2; |
| 256 | |
| 257 | /* |
| 258 | * Config register: |
| 259 | * Bit 5 : 0 = Enable WDT_OUTPUT |
| 260 | * Bit 2 : 0 = set the timer frequency to the PCI clock |
| 261 | * divided by 2^15 (approx 1KHz). |
| 262 | * Bits 1:0 : 11 = WDT_INT_TYPE Disabled. |
| 263 | * The watchdog has two timers, it can be setup so that the |
| 264 | * expiry of timer1 results in an interrupt and the expiry of |
| 265 | * timer2 results in a reboot. We set it to not generate |
| 266 | * any interrupts as there is not much we can do with it |
| 267 | * right now. |
| 268 | */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 269 | pci_write_config_word(edev->pdev, ESB_CONFIG_REG, 0x0003); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 270 | |
| 271 | /* Check that the WDT isn't already locked */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 272 | pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val1); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 273 | if (val1 & ESB_WDT_LOCK) |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 274 | dev_warn(&edev->pdev->dev, "nowayout already set\n"); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 275 | |
| 276 | /* Set the timer to watchdog mode and disable it for now */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 277 | pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x00); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 278 | |
| 279 | /* Check if the watchdog was previously triggered */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 280 | esb_unlock_registers(edev); |
| 281 | val2 = readw(ESB_RELOAD_REG(edev)); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 282 | if (val2 & ESB_WDT_TIMEOUT) |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 283 | edev->wdd.bootstatus = WDIOF_CARDRESET; |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 284 | |
| 285 | /* Reset WDT_TIMEOUT flag and timers */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 286 | esb_unlock_registers(edev); |
| 287 | writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG(edev)); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 288 | |
| 289 | /* And set the correct timeout value */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 290 | esb_timer_set_heartbeat(&edev->wdd, edev->wdd.timeout); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 291 | } |
| 292 | |
Bill Pemberton | 2d991a1 | 2012-11-19 13:21:41 -0500 | [diff] [blame] | 293 | static int esb_probe(struct pci_dev *pdev, |
Wim Van Sebroeck | 2786095 | 2010-03-08 13:48:01 +0000 | [diff] [blame] | 294 | const struct pci_device_id *ent) |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 295 | { |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 296 | struct esb_dev *edev; |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 297 | int ret; |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 298 | |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 299 | edev = devm_kzalloc(&pdev->dev, sizeof(*edev), GFP_KERNEL); |
| 300 | if (!edev) |
| 301 | return -ENOMEM; |
Wim Van Sebroeck | 2786095 | 2010-03-08 13:48:01 +0000 | [diff] [blame] | 302 | |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 303 | /* Check whether or not the hardware watchdog is there */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 304 | edev->pdev = pdev; |
| 305 | if (!esb_getdevice(edev)) |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 306 | return -ENODEV; |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 307 | |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 308 | /* Initialize the watchdog and make sure it does not run */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 309 | edev->wdd.info = &esb_info; |
| 310 | edev->wdd.ops = &esb_ops; |
Radu Rendec | 568d601 | 2017-10-26 17:10:15 +0100 | [diff] [blame] | 311 | edev->wdd.min_timeout = ESB_HEARTBEAT_MIN; |
| 312 | edev->wdd.max_timeout = ESB_HEARTBEAT_MAX; |
| 313 | edev->wdd.timeout = ESB_HEARTBEAT_DEFAULT; |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 314 | if (watchdog_init_timeout(&edev->wdd, heartbeat, NULL)) |
| 315 | dev_info(&pdev->dev, |
Radu Rendec | 568d601 | 2017-10-26 17:10:15 +0100 | [diff] [blame] | 316 | "heartbeat value must be " ESB_HEARTBEAT_RANGE |
| 317 | ", using %u\n", edev->wdd.timeout); |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 318 | watchdog_set_nowayout(&edev->wdd, nowayout); |
| 319 | watchdog_stop_on_reboot(&edev->wdd); |
| 320 | watchdog_stop_on_unregister(&edev->wdd); |
| 321 | esb_initdevice(edev); |
Wim Van Sebroeck | fc8a9d8 | 2009-03-25 19:16:28 +0000 | [diff] [blame] | 322 | |
| 323 | /* Register the watchdog so that userspace has access to it */ |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 324 | ret = watchdog_register_device(&edev->wdd); |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 325 | if (ret != 0) { |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 326 | dev_err(&pdev->dev, |
| 327 | "cannot register watchdog device (err=%d)\n", ret); |
Wim Van Sebroeck | 0426fd0 | 2009-03-19 19:02:44 +0000 | [diff] [blame] | 328 | goto err_unmap; |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 329 | } |
Radu Rendec | 7af4ac8 | 2017-10-26 17:10:13 +0100 | [diff] [blame] | 330 | dev_info(&pdev->dev, |
| 331 | "initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n", |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 332 | edev->base, edev->wdd.timeout, nowayout); |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 333 | return 0; |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 334 | |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 335 | err_unmap: |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 336 | iounmap(edev->base); |
| 337 | pci_release_region(edev->pdev, 0); |
| 338 | pci_disable_device(edev->pdev); |
Alan Cox | 0829291 | 2008-05-19 14:05:57 +0100 | [diff] [blame] | 339 | return ret; |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 340 | } |
| 341 | |
Bill Pemberton | 4b12b89 | 2012-11-19 13:26:24 -0500 | [diff] [blame] | 342 | static void esb_remove(struct pci_dev *pdev) |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 343 | { |
Radu Rendec | cf73120 | 2017-10-26 17:10:14 +0100 | [diff] [blame] | 344 | struct esb_dev *edev = dev_get_drvdata(&pdev->dev); |
| 345 | |
| 346 | watchdog_unregister_device(&edev->wdd); |
| 347 | iounmap(edev->base); |
| 348 | pci_release_region(edev->pdev, 0); |
| 349 | pci_disable_device(edev->pdev); |
Wim Van Sebroeck | 0426fd0 | 2009-03-19 19:02:44 +0000 | [diff] [blame] | 350 | } |
| 351 | |
Wim Van Sebroeck | 2786095 | 2010-03-08 13:48:01 +0000 | [diff] [blame] | 352 | static struct pci_driver esb_driver = { |
| 353 | .name = ESB_MODULE_NAME, |
| 354 | .id_table = esb_pci_tbl, |
Wim Van Sebroeck | 0426fd0 | 2009-03-19 19:02:44 +0000 | [diff] [blame] | 355 | .probe = esb_probe, |
Bill Pemberton | 8226871 | 2012-11-19 13:21:12 -0500 | [diff] [blame] | 356 | .remove = esb_remove, |
Wim Van Sebroeck | 0426fd0 | 2009-03-19 19:02:44 +0000 | [diff] [blame] | 357 | }; |
| 358 | |
Wim Van Sebroeck | 5ce9c37 | 2012-05-04 14:43:25 +0200 | [diff] [blame] | 359 | module_pci_driver(esb_driver); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 360 | |
Jan Engelhardt | 96de0e2 | 2007-10-19 23:21:04 +0200 | [diff] [blame] | 361 | MODULE_AUTHOR("Ross Biro and David Härdeman"); |
David Hardeman | cc90ef0 | 2005-08-17 09:07:44 +0200 | [diff] [blame] | 362 | MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets"); |
| 363 | MODULE_LICENSE("GPL"); |