blob: 950c71a8bb22fdfe5d6902df618ab5de6f8e8c1e [file] [log] [blame]
David Hardemancc90ef02005-08-17 09:07:44 +02001/*
David Hardemanabda5c82005-09-01 22:34:53 +02002 * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
David Hardemancc90ef02005-08-17 09:07:44 +02003 *
4 * (c) Copyright 2004 Google Inc.
Jan Engelhardt96de0e22007-10-19 23:21:04 +02005 * (c) Copyright 2005 David Härdeman <david@2gen.com>
David Hardemancc90ef02005-08-17 09:07:44 +02006 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
Wim Van Sebroeck7944d3a2008-08-06 20:19:41 +000012 * based on i810-tco.c which is in turn based on softdog.c
David Hardemancc90ef02005-08-17 09:07:44 +020013 *
Wim Van Sebroeck7944d3a2008-08-06 20:19:41 +000014 * The timer is implemented in the following I/O controller hubs:
15 * (See the intel documentation on http://developer.intel.com.)
Wim Van Sebroeck0426fd02009-03-19 19:02:44 +000016 * 6300ESB chip : document number 300641-004
David Hardemancc90ef02005-08-17 09:07:44 +020017 *
18 * 2004YYZZ Ross Biro
19 * Initial version 0.01
20 * 2004YYZZ Ross Biro
Wim Van Sebroeck7944d3a2008-08-06 20:19:41 +000021 * Version 0.02
Jan Engelhardt96de0e22007-10-19 23:21:04 +020022 * 20050210 David Härdeman <david@2gen.com>
Wim Van Sebroeck7944d3a2008-08-06 20:19:41 +000023 * Ported driver to kernel 2.6
Radu Rendec7af4ac82017-10-26 17:10:13 +010024 * 20171016 Radu Rendec <rrendec@arista.com>
25 * Change driver to use the watchdog subsystem
Radu Rendeccf731202017-10-26 17:10:14 +010026 * Add support for multiple 6300ESB devices
David Hardemancc90ef02005-08-17 09:07:44 +020027 */
28
29/*
30 * Includes, defines, variables, module parameters, ...
31 */
32
33#include <linux/module.h>
34#include <linux/types.h>
35#include <linux/kernel.h>
36#include <linux/fs.h>
37#include <linux/mm.h>
38#include <linux/miscdevice.h>
39#include <linux/watchdog.h>
David Hardemancc90ef02005-08-17 09:07:44 +020040#include <linux/pci.h>
41#include <linux/ioport.h>
Alan Cox08292912008-05-19 14:05:57 +010042#include <linux/uaccess.h>
43#include <linux/io.h>
David Hardemancc90ef02005-08-17 09:07:44 +020044
David Hardemancc90ef02005-08-17 09:07:44 +020045/* Module and version information */
David Hardemancc90ef02005-08-17 09:07:44 +020046#define ESB_MODULE_NAME "i6300ESB timer"
David Hardemancc90ef02005-08-17 09:07:44 +020047
David Hardemanabda5c82005-09-01 22:34:53 +020048/* PCI configuration registers */
49#define ESB_CONFIG_REG 0x60 /* Config register */
50#define ESB_LOCK_REG 0x68 /* WDT lock register */
51
52/* Memory mapped registers */
Radu Rendeccf731202017-10-26 17:10:14 +010053#define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
54#define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
55#define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
56#define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
David Hardemanabda5c82005-09-01 22:34:53 +020057
58/* Lock register bits */
Alan Cox08292912008-05-19 14:05:57 +010059#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
60#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
61#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
David Hardemanabda5c82005-09-01 22:34:53 +020062
63/* Config register bits */
Alan Cox08292912008-05-19 14:05:57 +010064#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
65#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
Wim Van Sebroeck39f3be72010-03-08 11:02:38 +000066#define ESB_WDT_INTTYPE (0x03 << 0) /* Interrupt type on timer1 timeout */
David Hardemanabda5c82005-09-01 22:34:53 +020067
68/* Reload register bits */
Wim Van Sebroeck31838d9d2009-03-25 19:14:45 +000069#define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */
Alan Cox08292912008-05-19 14:05:57 +010070#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
David Hardemanabda5c82005-09-01 22:34:53 +020071
72/* Magic constants */
73#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
74#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
75
David Hardemancc90ef02005-08-17 09:07:44 +020076/* module parameters */
Alan Cox08292912008-05-19 14:05:57 +010077/* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
Radu Rendec568d6012017-10-26 17:10:15 +010078#define ESB_HEARTBEAT_MIN 1
79#define ESB_HEARTBEAT_MAX 2046
80#define ESB_HEARTBEAT_DEFAULT 30
81#define ESB_HEARTBEAT_RANGE __MODULE_STRING(ESB_HEARTBEAT_MIN) \
82 "<heartbeat<" __MODULE_STRING(ESB_HEARTBEAT_MAX)
Radu Rendec7af4ac82017-10-26 17:10:13 +010083static int heartbeat; /* in seconds */
David Hardemancc90ef02005-08-17 09:07:44 +020084module_param(heartbeat, int, 0);
Alan Cox08292912008-05-19 14:05:57 +010085MODULE_PARM_DESC(heartbeat,
Radu Rendec568d6012017-10-26 17:10:15 +010086 "Watchdog heartbeat in seconds. (" ESB_HEARTBEAT_RANGE
87 ", default=" __MODULE_STRING(ESB_HEARTBEAT_DEFAULT) ")");
David Hardemancc90ef02005-08-17 09:07:44 +020088
Wim Van Sebroeck86a1e182012-03-05 16:51:11 +010089static bool nowayout = WATCHDOG_NOWAYOUT;
90module_param(nowayout, bool, 0);
Alan Cox08292912008-05-19 14:05:57 +010091MODULE_PARM_DESC(nowayout,
92 "Watchdog cannot be stopped once started (default="
93 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
David Hardemancc90ef02005-08-17 09:07:44 +020094
Radu Rendeccf731202017-10-26 17:10:14 +010095/* internal variables */
96struct esb_dev {
97 struct watchdog_device wdd;
98 void __iomem *base;
99 struct pci_dev *pdev;
100};
101
102#define to_esb_dev(wptr) container_of(wptr, struct esb_dev, wdd)
103
David Hardemancc90ef02005-08-17 09:07:44 +0200104/*
105 * Some i6300ESB specific functions
106 */
107
108/*
109 * Prepare for reloading the timer by unlocking the proper registers.
110 * This is performed by first writing 0x80 followed by 0x86 to the
111 * reload register. After this the appropriate registers can be written
112 * to once before they need to be unlocked again.
113 */
Radu Rendeccf731202017-10-26 17:10:14 +0100114static inline void esb_unlock_registers(struct esb_dev *edev)
Wim Van Sebroeck7944d3a2008-08-06 20:19:41 +0000115{
Radu Rendeccf731202017-10-26 17:10:14 +0100116 writew(ESB_UNLOCK1, ESB_RELOAD_REG(edev));
117 writew(ESB_UNLOCK2, ESB_RELOAD_REG(edev));
David Hardemancc90ef02005-08-17 09:07:44 +0200118}
119
Radu Rendec7af4ac82017-10-26 17:10:13 +0100120static int esb_timer_start(struct watchdog_device *wdd)
David Hardemancc90ef02005-08-17 09:07:44 +0200121{
Radu Rendeccf731202017-10-26 17:10:14 +0100122 struct esb_dev *edev = to_esb_dev(wdd);
Radu Rendec7af4ac82017-10-26 17:10:13 +0100123 int _wdd_nowayout = test_bit(WDOG_NO_WAY_OUT, &wdd->status);
David Hardemancc90ef02005-08-17 09:07:44 +0200124 u8 val;
125
Radu Rendeccf731202017-10-26 17:10:14 +0100126 esb_unlock_registers(edev);
127 writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
David Hardemancc90ef02005-08-17 09:07:44 +0200128 /* Enable or Enable + Lock? */
Radu Rendec7af4ac82017-10-26 17:10:13 +0100129 val = ESB_WDT_ENABLE | (_wdd_nowayout ? ESB_WDT_LOCK : 0x00);
Radu Rendeccf731202017-10-26 17:10:14 +0100130 pci_write_config_byte(edev->pdev, ESB_LOCK_REG, val);
Wim Van Sebroeck3b9d49e2009-03-23 13:50:38 +0000131 return 0;
David Hardemancc90ef02005-08-17 09:07:44 +0200132}
133
Radu Rendec7af4ac82017-10-26 17:10:13 +0100134static int esb_timer_stop(struct watchdog_device *wdd)
David Hardemancc90ef02005-08-17 09:07:44 +0200135{
Radu Rendeccf731202017-10-26 17:10:14 +0100136 struct esb_dev *edev = to_esb_dev(wdd);
David Hardemancc90ef02005-08-17 09:07:44 +0200137 u8 val;
138
David Hardemancc90ef02005-08-17 09:07:44 +0200139 /* First, reset timers as suggested by the docs */
Radu Rendeccf731202017-10-26 17:10:14 +0100140 esb_unlock_registers(edev);
141 writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
David Hardemancc90ef02005-08-17 09:07:44 +0200142 /* Then disable the WDT */
Radu Rendeccf731202017-10-26 17:10:14 +0100143 pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x0);
144 pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val);
David Hardemancc90ef02005-08-17 09:07:44 +0200145
146 /* Returns 0 if the timer was disabled, non-zero otherwise */
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000147 return val & ESB_WDT_ENABLE;
David Hardemancc90ef02005-08-17 09:07:44 +0200148}
149
Radu Rendec7af4ac82017-10-26 17:10:13 +0100150static int esb_timer_keepalive(struct watchdog_device *wdd)
David Hardemancc90ef02005-08-17 09:07:44 +0200151{
Radu Rendeccf731202017-10-26 17:10:14 +0100152 struct esb_dev *edev = to_esb_dev(wdd);
153
154 esb_unlock_registers(edev);
155 writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
Alan Cox08292912008-05-19 14:05:57 +0100156 /* FIXME: Do we need to flush anything here? */
Radu Rendec7af4ac82017-10-26 17:10:13 +0100157 return 0;
David Hardemancc90ef02005-08-17 09:07:44 +0200158}
159
Radu Rendec7af4ac82017-10-26 17:10:13 +0100160static int esb_timer_set_heartbeat(struct watchdog_device *wdd,
161 unsigned int time)
David Hardemancc90ef02005-08-17 09:07:44 +0200162{
Radu Rendeccf731202017-10-26 17:10:14 +0100163 struct esb_dev *edev = to_esb_dev(wdd);
David Hardemancc90ef02005-08-17 09:07:44 +0200164 u32 val;
165
David Hardemancc90ef02005-08-17 09:07:44 +0200166 /* We shift by 9, so if we are passed a value of 1 sec,
167 * val will be 1 << 9 = 512, then write that to two
168 * timers => 2 * 512 = 1024 (which is decremented at 1KHz)
169 */
170 val = time << 9;
171
172 /* Write timer 1 */
Radu Rendeccf731202017-10-26 17:10:14 +0100173 esb_unlock_registers(edev);
174 writel(val, ESB_TIMER1_REG(edev));
David Hardemancc90ef02005-08-17 09:07:44 +0200175
176 /* Write timer 2 */
Radu Rendeccf731202017-10-26 17:10:14 +0100177 esb_unlock_registers(edev);
178 writel(val, ESB_TIMER2_REG(edev));
David Hardemancc90ef02005-08-17 09:07:44 +0200179
Alan Cox08292912008-05-19 14:05:57 +0100180 /* Reload */
Radu Rendeccf731202017-10-26 17:10:14 +0100181 esb_unlock_registers(edev);
182 writew(ESB_WDT_RELOAD, ESB_RELOAD_REG(edev));
David Hardemancc90ef02005-08-17 09:07:44 +0200183
184 /* FIXME: Do we need to flush everything out? */
185
186 /* Done */
Radu Rendec7af4ac82017-10-26 17:10:13 +0100187 wdd->timeout = time;
David Hardemancc90ef02005-08-17 09:07:44 +0200188 return 0;
189}
190
David Hardemancc90ef02005-08-17 09:07:44 +0200191/*
Radu Rendec7af4ac82017-10-26 17:10:13 +0100192 * Watchdog Subsystem Interfaces
David Hardemancc90ef02005-08-17 09:07:44 +0200193 */
194
Radu Rendec7af4ac82017-10-26 17:10:13 +0100195static struct watchdog_info esb_info = {
196 .identity = ESB_MODULE_NAME,
197 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
David Hardemancc90ef02005-08-17 09:07:44 +0200198};
199
Radu Rendec7af4ac82017-10-26 17:10:13 +0100200static const struct watchdog_ops esb_ops = {
201 .owner = THIS_MODULE,
202 .start = esb_timer_start,
203 .stop = esb_timer_stop,
204 .set_timeout = esb_timer_set_heartbeat,
205 .ping = esb_timer_keepalive,
206};
207
David Hardemancc90ef02005-08-17 09:07:44 +0200208/*
209 * Data for PCI driver interface
David Hardemancc90ef02005-08-17 09:07:44 +0200210 */
Jingoo Hanbc17f9d2013-12-03 08:30:22 +0900211static const struct pci_device_id esb_pci_tbl[] = {
Alan Cox08292912008-05-19 14:05:57 +0100212 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
213 { 0, }, /* End of list */
David Hardemancc90ef02005-08-17 09:07:44 +0200214};
Alan Cox08292912008-05-19 14:05:57 +0100215MODULE_DEVICE_TABLE(pci, esb_pci_tbl);
David Hardemancc90ef02005-08-17 09:07:44 +0200216
217/*
218 * Init & exit routines
219 */
220
Radu Rendeccf731202017-10-26 17:10:14 +0100221static unsigned char esb_getdevice(struct esb_dev *edev)
David Hardemancc90ef02005-08-17 09:07:44 +0200222{
Radu Rendeccf731202017-10-26 17:10:14 +0100223 if (pci_enable_device(edev->pdev)) {
224 dev_err(&edev->pdev->dev, "failed to enable device\n");
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000225 goto err_devput;
226 }
David Hardemancc90ef02005-08-17 09:07:44 +0200227
Radu Rendeccf731202017-10-26 17:10:14 +0100228 if (pci_request_region(edev->pdev, 0, ESB_MODULE_NAME)) {
229 dev_err(&edev->pdev->dev, "failed to request region\n");
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000230 goto err_disable;
231 }
David Hardemancc90ef02005-08-17 09:07:44 +0200232
Radu Rendeccf731202017-10-26 17:10:14 +0100233 edev->base = pci_ioremap_bar(edev->pdev, 0);
234 if (edev->base == NULL) {
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000235 /* Something's wrong here, BASEADDR has to be set */
Radu Rendeccf731202017-10-26 17:10:14 +0100236 dev_err(&edev->pdev->dev, "failed to get BASEADDR\n");
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000237 goto err_release;
238 }
David Hardemancc90ef02005-08-17 09:07:44 +0200239
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000240 /* Done */
Radu Rendeccf731202017-10-26 17:10:14 +0100241 dev_set_drvdata(&edev->pdev->dev, edev);
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000242 return 1;
David Hardemancc90ef02005-08-17 09:07:44 +0200243
244err_release:
Radu Rendeccf731202017-10-26 17:10:14 +0100245 pci_release_region(edev->pdev, 0);
David Hardemancc90ef02005-08-17 09:07:44 +0200246err_disable:
Radu Rendeccf731202017-10-26 17:10:14 +0100247 pci_disable_device(edev->pdev);
Naveen Gupta811f9992005-08-21 13:02:41 +0200248err_devput:
David Hardemancc90ef02005-08-17 09:07:44 +0200249 return 0;
250}
251
Radu Rendeccf731202017-10-26 17:10:14 +0100252static void esb_initdevice(struct esb_dev *edev)
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000253{
254 u8 val1;
255 u16 val2;
256
257 /*
258 * Config register:
259 * Bit 5 : 0 = Enable WDT_OUTPUT
260 * Bit 2 : 0 = set the timer frequency to the PCI clock
261 * divided by 2^15 (approx 1KHz).
262 * Bits 1:0 : 11 = WDT_INT_TYPE Disabled.
263 * The watchdog has two timers, it can be setup so that the
264 * expiry of timer1 results in an interrupt and the expiry of
265 * timer2 results in a reboot. We set it to not generate
266 * any interrupts as there is not much we can do with it
267 * right now.
268 */
Radu Rendeccf731202017-10-26 17:10:14 +0100269 pci_write_config_word(edev->pdev, ESB_CONFIG_REG, 0x0003);
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000270
271 /* Check that the WDT isn't already locked */
Radu Rendeccf731202017-10-26 17:10:14 +0100272 pci_read_config_byte(edev->pdev, ESB_LOCK_REG, &val1);
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000273 if (val1 & ESB_WDT_LOCK)
Radu Rendeccf731202017-10-26 17:10:14 +0100274 dev_warn(&edev->pdev->dev, "nowayout already set\n");
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000275
276 /* Set the timer to watchdog mode and disable it for now */
Radu Rendeccf731202017-10-26 17:10:14 +0100277 pci_write_config_byte(edev->pdev, ESB_LOCK_REG, 0x00);
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000278
279 /* Check if the watchdog was previously triggered */
Radu Rendeccf731202017-10-26 17:10:14 +0100280 esb_unlock_registers(edev);
281 val2 = readw(ESB_RELOAD_REG(edev));
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000282 if (val2 & ESB_WDT_TIMEOUT)
Radu Rendeccf731202017-10-26 17:10:14 +0100283 edev->wdd.bootstatus = WDIOF_CARDRESET;
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000284
285 /* Reset WDT_TIMEOUT flag and timers */
Radu Rendeccf731202017-10-26 17:10:14 +0100286 esb_unlock_registers(edev);
287 writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG(edev));
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000288
289 /* And set the correct timeout value */
Radu Rendeccf731202017-10-26 17:10:14 +0100290 esb_timer_set_heartbeat(&edev->wdd, edev->wdd.timeout);
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000291}
292
Bill Pemberton2d991a12012-11-19 13:21:41 -0500293static int esb_probe(struct pci_dev *pdev,
Wim Van Sebroeck27860952010-03-08 13:48:01 +0000294 const struct pci_device_id *ent)
David Hardemancc90ef02005-08-17 09:07:44 +0200295{
Radu Rendeccf731202017-10-26 17:10:14 +0100296 struct esb_dev *edev;
Alan Cox08292912008-05-19 14:05:57 +0100297 int ret;
David Hardemancc90ef02005-08-17 09:07:44 +0200298
Radu Rendeccf731202017-10-26 17:10:14 +0100299 edev = devm_kzalloc(&pdev->dev, sizeof(*edev), GFP_KERNEL);
300 if (!edev)
301 return -ENOMEM;
Wim Van Sebroeck27860952010-03-08 13:48:01 +0000302
Alan Cox08292912008-05-19 14:05:57 +0100303 /* Check whether or not the hardware watchdog is there */
Radu Rendeccf731202017-10-26 17:10:14 +0100304 edev->pdev = pdev;
305 if (!esb_getdevice(edev))
Alan Cox08292912008-05-19 14:05:57 +0100306 return -ENODEV;
David Hardemancc90ef02005-08-17 09:07:44 +0200307
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000308 /* Initialize the watchdog and make sure it does not run */
Radu Rendeccf731202017-10-26 17:10:14 +0100309 edev->wdd.info = &esb_info;
310 edev->wdd.ops = &esb_ops;
Radu Rendec568d6012017-10-26 17:10:15 +0100311 edev->wdd.min_timeout = ESB_HEARTBEAT_MIN;
312 edev->wdd.max_timeout = ESB_HEARTBEAT_MAX;
313 edev->wdd.timeout = ESB_HEARTBEAT_DEFAULT;
Radu Rendeccf731202017-10-26 17:10:14 +0100314 if (watchdog_init_timeout(&edev->wdd, heartbeat, NULL))
315 dev_info(&pdev->dev,
Radu Rendec568d6012017-10-26 17:10:15 +0100316 "heartbeat value must be " ESB_HEARTBEAT_RANGE
317 ", using %u\n", edev->wdd.timeout);
Radu Rendeccf731202017-10-26 17:10:14 +0100318 watchdog_set_nowayout(&edev->wdd, nowayout);
319 watchdog_stop_on_reboot(&edev->wdd);
320 watchdog_stop_on_unregister(&edev->wdd);
321 esb_initdevice(edev);
Wim Van Sebroeckfc8a9d82009-03-25 19:16:28 +0000322
323 /* Register the watchdog so that userspace has access to it */
Radu Rendeccf731202017-10-26 17:10:14 +0100324 ret = watchdog_register_device(&edev->wdd);
Alan Cox08292912008-05-19 14:05:57 +0100325 if (ret != 0) {
Radu Rendec7af4ac82017-10-26 17:10:13 +0100326 dev_err(&pdev->dev,
327 "cannot register watchdog device (err=%d)\n", ret);
Wim Van Sebroeck0426fd02009-03-19 19:02:44 +0000328 goto err_unmap;
Alan Cox08292912008-05-19 14:05:57 +0100329 }
Radu Rendec7af4ac82017-10-26 17:10:13 +0100330 dev_info(&pdev->dev,
331 "initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
Radu Rendeccf731202017-10-26 17:10:14 +0100332 edev->base, edev->wdd.timeout, nowayout);
Alan Cox08292912008-05-19 14:05:57 +0100333 return 0;
David Hardemancc90ef02005-08-17 09:07:44 +0200334
David Hardemancc90ef02005-08-17 09:07:44 +0200335err_unmap:
Radu Rendeccf731202017-10-26 17:10:14 +0100336 iounmap(edev->base);
337 pci_release_region(edev->pdev, 0);
338 pci_disable_device(edev->pdev);
Alan Cox08292912008-05-19 14:05:57 +0100339 return ret;
David Hardemancc90ef02005-08-17 09:07:44 +0200340}
341
Bill Pemberton4b12b892012-11-19 13:26:24 -0500342static void esb_remove(struct pci_dev *pdev)
David Hardemancc90ef02005-08-17 09:07:44 +0200343{
Radu Rendeccf731202017-10-26 17:10:14 +0100344 struct esb_dev *edev = dev_get_drvdata(&pdev->dev);
345
346 watchdog_unregister_device(&edev->wdd);
347 iounmap(edev->base);
348 pci_release_region(edev->pdev, 0);
349 pci_disable_device(edev->pdev);
Wim Van Sebroeck0426fd02009-03-19 19:02:44 +0000350}
351
Wim Van Sebroeck27860952010-03-08 13:48:01 +0000352static struct pci_driver esb_driver = {
353 .name = ESB_MODULE_NAME,
354 .id_table = esb_pci_tbl,
Wim Van Sebroeck0426fd02009-03-19 19:02:44 +0000355 .probe = esb_probe,
Bill Pemberton82268712012-11-19 13:21:12 -0500356 .remove = esb_remove,
Wim Van Sebroeck0426fd02009-03-19 19:02:44 +0000357};
358
Wim Van Sebroeck5ce9c372012-05-04 14:43:25 +0200359module_pci_driver(esb_driver);
David Hardemancc90ef02005-08-17 09:07:44 +0200360
Jan Engelhardt96de0e22007-10-19 23:21:04 +0200361MODULE_AUTHOR("Ross Biro and David Härdeman");
David Hardemancc90ef02005-08-17 09:07:44 +0200362MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
363MODULE_LICENSE("GPL");