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Krzysztof Kozlowskicc4637f2017-12-25 11:40:09 +01001// SPDX-License-Identifier: GPL-2.0
Tomasz Figa5a992a92014-05-15 06:01:27 +09002/*
3 * Samsung's Exynos3250 SoC device tree source
4 *
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file.
Tomasz Figa5a992a92014-05-15 06:01:27 +090015 */
16
Lukasz Majewski9843a222015-01-30 08:26:03 +090017#include "exynos4-cpu-thermal.dtsi"
Tomasz Figa5a992a92014-05-15 06:01:27 +090018#include <dt-bindings/clock/exynos3250.h>
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +020019#include <dt-bindings/interrupt-controller/arm-gic.h>
Krzysztof Kozlowski89be8512016-09-16 21:42:46 +020020#include <dt-bindings/interrupt-controller/irq.h>
Tomasz Figa5a992a92014-05-15 06:01:27 +090021
22/ {
23 compatible = "samsung,exynos3250";
24 interrupt-parent = <&gic>;
Javier Martinez Canillas33c3de72016-09-01 11:06:51 +020025 #address-cells = <1>;
26 #size-cells = <1>;
Tomasz Figa5a992a92014-05-15 06:01:27 +090027
28 aliases {
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
31 mshc0 = &mshc_0;
32 mshc1 = &mshc_1;
Chanwoo Choi92173e62016-03-31 11:48:03 +090033 mshc2 = &mshc_2;
Tomasz Figa5a992a92014-05-15 06:01:27 +090034 spi0 = &spi_0;
35 spi1 = &spi_1;
36 i2c0 = &i2c_0;
37 i2c1 = &i2c_1;
38 i2c2 = &i2c_2;
39 i2c3 = &i2c_3;
40 i2c4 = &i2c_4;
41 i2c5 = &i2c_5;
42 i2c6 = &i2c_6;
43 i2c7 = &i2c_7;
Tomasz Figa1e64f482014-06-26 13:24:35 +020044 serial0 = &serial_0;
45 serial1 = &serial_1;
Pankaj Dubeyecaba512016-03-31 11:48:01 +090046 serial2 = &serial_2;
Tomasz Figa5a992a92014-05-15 06:01:27 +090047 };
48
49 cpus {
50 #address-cells = <1>;
51 #size-cells = <0>;
52
Krzysztof Kozlowskia2798e32021-07-31 11:24:02 +020053 cpu-map {
54 cluster0 {
55 core0 {
56 cpu = <&cpu0>;
57 };
58 core1 {
59 cpu = <&cpu1>;
60 };
61 };
62 };
63
Tomasz Figa5a992a92014-05-15 06:01:27 +090064 cpu0: cpu@0 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a7";
67 reg = <0>;
68 clock-frequency = <1000000000>;
Chanwoo Choi48816af2015-07-24 12:55:21 +090069 clocks = <&cmu CLK_ARM_CLK>;
70 clock-names = "cpu";
Chanwoo Choi5600f8c2015-07-30 23:02:22 +090071 #cooling-cells = <2>;
Chanwoo Choi48816af2015-07-24 12:55:21 +090072
73 operating-points = <
74 1000000 1150000
75 900000 1112500
76 800000 1075000
77 700000 1037500
78 600000 1000000
79 500000 962500
80 400000 925000
81 300000 887500
82 200000 850000
83 100000 850000
84 >;
Tomasz Figa5a992a92014-05-15 06:01:27 +090085 };
86
87 cpu1: cpu@1 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a7";
90 reg = <1>;
91 clock-frequency = <1000000000>;
Viresh Kumar672f3312018-05-25 16:01:53 +053092 clocks = <&cmu CLK_ARM_CLK>;
93 clock-names = "cpu";
94 #cooling-cells = <2>;
95
96 operating-points = <
97 1000000 1150000
98 900000 1112500
99 800000 1075000
100 700000 1037500
101 600000 1000000
102 500000 962500
103 400000 925000
104 300000 887500
105 200000 850000
106 100000 850000
107 >;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900108 };
109 };
110
Krzysztof Kozlowski68f4bab2020-08-29 19:25:30 +0200111 xusbxti: clock-0 {
112 compatible = "fixed-clock";
113 clock-frequency = <0>;
114 #clock-cells = <0>;
115 clock-output-names = "xusbxti";
116 };
Krzysztof Kozlowski1e440c22019-04-15 20:05:09 +0200117
Krzysztof Kozlowski68f4bab2020-08-29 19:25:30 +0200118 xxti: clock-1 {
119 compatible = "fixed-clock";
120 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-output-names = "xxti";
123 };
Krzysztof Kozlowski1e440c22019-04-15 20:05:09 +0200124
Krzysztof Kozlowski68f4bab2020-08-29 19:25:30 +0200125 xtcxo: clock-2 {
126 compatible = "fixed-clock";
127 clock-frequency = <0>;
128 #clock-cells = <0>;
129 clock-output-names = "xtcxo";
Krzysztof Kozlowski1e440c22019-04-15 20:05:09 +0200130 };
131
Krzysztof Kozlowskibe003002019-04-15 20:05:07 +0200132 pmu {
133 compatible = "arm,cortex-a7-pmu";
134 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
136 };
137
Tomasz Figa5a992a92014-05-15 06:01:27 +0900138 soc: soc {
139 compatible = "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges;
143
Krzysztof Kozlowski56c126e2019-10-02 18:43:09 +0200144 sram@2020000 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900145 compatible = "mmio-sram";
146 reg = <0x02020000 0x40000>;
147 #address-cells = <1>;
148 #size-cells = <1>;
149 ranges = <0 0x02020000 0x40000>;
150
Krzysztof Kozlowskib6df5e22019-10-21 17:14:40 +0200151 smp-sram@0 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900152 compatible = "samsung,exynos4210-sysram";
153 reg = <0x0 0x1000>;
154 };
155
Krzysztof Kozlowskib6df5e22019-10-21 17:14:40 +0200156 smp-sram@3f000 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900157 compatible = "samsung,exynos4210-sysram-ns";
158 reg = <0x3f000 0x1000>;
159 };
160 };
161
162 chipid@10000000 {
163 compatible = "samsung,exynos4210-chipid";
164 reg = <0x10000000 0x100>;
165 };
166
167 sys_reg: syscon@10010000 {
168 compatible = "samsung,exynos3-sysreg", "syscon";
169 reg = <0x10010000 0x400>;
170 };
171
Chanwoo Choi25023922014-05-31 02:17:22 +0900172 pmu_system_controller: system-controller@10020000 {
173 compatible = "samsung,exynos3250-pmu", "syscon";
174 reg = <0x10020000 0x4000>;
Marc Zyngier8b283c02015-03-11 15:44:52 +0000175 interrupt-controller;
176 #interrupt-cells = <3>;
177 interrupt-parent = <&gic>;
Marek Szyprowskia66352e2019-02-15 11:36:50 +0100178 clock-names = "clkout8";
179 clocks = <&cmu CLK_FIN_PLL>;
180 #clock-cells = <1>;
Chanwoo Choi25023922014-05-31 02:17:22 +0900181 };
182
Krzysztof Kozlowskibb72cad2016-04-06 11:00:41 +0900183 mipi_phy: video-phy {
Inki Dae9fab9d62014-08-13 20:46:12 +0900184 compatible = "samsung,s5pv210-mipi-video-phy";
Inki Dae9fab9d62014-08-13 20:46:12 +0900185 #phy-cells = <1>;
Beata Michalska1342ff42015-06-15 10:12:46 +0200186 syscon = <&pmu_system_controller>;
Inki Dae9fab9d62014-08-13 20:46:12 +0900187 };
188
Marek Szyprowski68912272018-02-21 11:25:15 +0100189 pd_cam: power-domain@10023c00 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900190 compatible = "samsung,exynos4210-pd";
191 reg = <0x10023C00 0x20>;
Marek Szyprowski0da65872015-01-24 13:16:15 +0900192 #power-domain-cells = <0>;
Marek Szyprowski68912272018-02-21 11:25:15 +0100193 label = "CAM";
Tomasz Figa5a992a92014-05-15 06:01:27 +0900194 };
195
Marek Szyprowski68912272018-02-21 11:25:15 +0100196 pd_mfc: power-domain@10023c40 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900197 compatible = "samsung,exynos4210-pd";
198 reg = <0x10023C40 0x20>;
Marek Szyprowski0da65872015-01-24 13:16:15 +0900199 #power-domain-cells = <0>;
Marek Szyprowski68912272018-02-21 11:25:15 +0100200 label = "MFC";
Tomasz Figa5a992a92014-05-15 06:01:27 +0900201 };
202
Marek Szyprowski68912272018-02-21 11:25:15 +0100203 pd_g3d: power-domain@10023c60 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900204 compatible = "samsung,exynos4210-pd";
205 reg = <0x10023C60 0x20>;
Marek Szyprowski0da65872015-01-24 13:16:15 +0900206 #power-domain-cells = <0>;
Marek Szyprowski68912272018-02-21 11:25:15 +0100207 label = "G3D";
Tomasz Figa5a992a92014-05-15 06:01:27 +0900208 };
209
Marek Szyprowski68912272018-02-21 11:25:15 +0100210 pd_lcd0: power-domain@10023c80 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900211 compatible = "samsung,exynos4210-pd";
212 reg = <0x10023C80 0x20>;
Marek Szyprowski0da65872015-01-24 13:16:15 +0900213 #power-domain-cells = <0>;
Marek Szyprowski68912272018-02-21 11:25:15 +0100214 label = "LCD0";
Tomasz Figa5a992a92014-05-15 06:01:27 +0900215 };
216
Marek Szyprowski68912272018-02-21 11:25:15 +0100217 pd_isp: power-domain@10023ca0 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900218 compatible = "samsung,exynos4210-pd";
219 reg = <0x10023CA0 0x20>;
Marek Szyprowski0da65872015-01-24 13:16:15 +0900220 #power-domain-cells = <0>;
Marek Szyprowski68912272018-02-21 11:25:15 +0100221 label = "ISP";
Tomasz Figa5a992a92014-05-15 06:01:27 +0900222 };
223
224 cmu: clock-controller@10030000 {
225 compatible = "samsung,exynos3250-cmu";
226 reg = <0x10030000 0x20000>;
227 #clock-cells = <1>;
Beata Michalska52005de2015-03-18 00:21:46 +0900228 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
229 <&cmu CLK_MOUT_ACLK_266_SUB>;
230 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
231 <&cmu CLK_FIN_PLL>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900232 };
233
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100234 cmu_dmc: clock-controller@105c0000 {
Krzysztof Kozlowskid0e73ea2014-09-02 15:21:16 +0200235 compatible = "samsung,exynos3250-cmu-dmc";
236 reg = <0x105C0000 0x2000>;
237 #clock-cells = <1>;
238 };
239
Tomasz Figa5a992a92014-05-15 06:01:27 +0900240 rtc: rtc@10070000 {
Krzysztof Kozlowski062f49c2015-05-02 14:33:55 +0900241 compatible = "samsung,s3c6410-rtc";
Tomasz Figa5a992a92014-05-15 06:01:27 +0900242 reg = <0x10070000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200243 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
Marc Zyngier8b283c02015-03-11 15:44:52 +0000245 interrupt-parent = <&pmu_system_controller>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900246 status = "disabled";
247 };
248
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100249 tmu: tmu@100c0000 {
Chanwoo Choi9dfb3342014-07-30 07:57:24 +0900250 compatible = "samsung,exynos3250-tmu";
251 reg = <0x100C0000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200252 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
Chanwoo Choi9dfb3342014-07-30 07:57:24 +0900253 clocks = <&cmu CLK_TMU_APBIF>;
254 clock-names = "tmu_apbif";
Bartlomiej Zolnierkiewiczc05b7992018-06-21 12:35:30 +0200255 #thermal-sensor-cells = <0>;
Chanwoo Choi9dfb3342014-07-30 07:57:24 +0900256 status = "disabled";
257 };
258
Tomasz Figa5a992a92014-05-15 06:01:27 +0900259 gic: interrupt-controller@10481000 {
260 compatible = "arm,cortex-a15-gic";
261 #interrupt-cells = <3>;
262 interrupt-controller;
263 reg = <0x10481000 0x1000>,
Marc Zyngier387720c2017-01-18 09:27:28 +0000264 <0x10482000 0x2000>,
Tomasz Figa5a992a92014-05-15 06:01:27 +0900265 <0x10484000 0x2000>,
266 <0x10486000 0x2000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200267 interrupts = <GIC_PPI 9
268 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900269 };
270
Krzysztof Kozlowskif859a032019-09-23 18:15:07 +0200271 timer@10050000 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900272 compatible = "samsung,exynos4210-mct";
273 reg = <0x10050000 0x800>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200274 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900282 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
283 clock-names = "fin_pll", "mct";
284 };
285
286 pinctrl_1: pinctrl@11000000 {
287 compatible = "samsung,exynos3250-pinctrl";
288 reg = <0x11000000 0x1000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200289 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900290
291 wakeup-interrupt-controller {
292 compatible = "samsung,exynos4210-wakeup-eint";
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200293 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900294 };
295 };
296
297 pinctrl_0: pinctrl@11400000 {
298 compatible = "samsung,exynos3250-pinctrl";
299 reg = <0x11400000 0x1000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200300 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900301 };
302
Jacek Anaszewskic9c1adf2015-05-09 02:26:45 +0900303 jpeg: codec@11830000 {
304 compatible = "samsung,exynos3250-jpeg";
305 reg = <0x11830000 0x1000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200306 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
Jacek Anaszewskic9c1adf2015-05-09 02:26:45 +0900307 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
308 clock-names = "jpeg", "sclk";
309 power-domains = <&pd_cam>;
310 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
311 assigned-clock-rates = <0>, <150000000>;
312 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
Marek Szyprowskif5976ce2015-06-04 08:09:41 +0900313 iommus = <&sysmmu_jpeg>;
Jacek Anaszewskic9c1adf2015-05-09 02:26:45 +0900314 status = "disabled";
315 };
316
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100317 sysmmu_jpeg: sysmmu@11a60000 {
Marek Szyprowskif5976ce2015-06-04 08:09:41 +0900318 compatible = "samsung,exynos-sysmmu";
319 reg = <0x11a60000 0x1000>;
Maciej Falkowski937683d2019-09-19 15:45:47 +0200320 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
Marek Szyprowskif5976ce2015-06-04 08:09:41 +0900321 clock-names = "sysmmu", "master";
322 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
323 power-domains = <&pd_cam>;
324 #iommu-cells = <0>;
325 };
326
Inki Dae03b86c792014-08-13 20:37:53 +0900327 fimd: fimd@11c00000 {
328 compatible = "samsung,exynos3250-fimd";
329 reg = <0x11c00000 0x30000>;
330 interrupt-names = "fifo", "vsync", "lcd_sys";
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200331 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Inki Dae03b86c792014-08-13 20:37:53 +0900334 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
335 clock-names = "sclk_fimd", "fimd";
Marek Szyprowski0da65872015-01-24 13:16:15 +0900336 power-domains = <&pd_lcd0>;
Marek Szyprowskif5976ce2015-06-04 08:09:41 +0900337 iommus = <&sysmmu_fimd0>;
Inki Dae03b86c792014-08-13 20:37:53 +0900338 samsung,sysreg = <&sys_reg>;
339 status = "disabled";
340 };
341
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100342 dsi_0: dsi@11c80000 {
Inki Dae025d8e12014-08-13 20:53:47 +0900343 compatible = "samsung,exynos3250-mipi-dsi";
344 reg = <0x11C80000 0x10000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200345 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
Inki Dae025d8e12014-08-13 20:53:47 +0900346 samsung,phy-type = <0>;
Marek Szyprowski0da65872015-01-24 13:16:15 +0900347 power-domains = <&pd_lcd0>;
Inki Dae025d8e12014-08-13 20:53:47 +0900348 phys = <&mipi_phy 1>;
349 phy-names = "dsim";
350 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
351 clock-names = "bus_clk", "pll_clk";
352 #address-cells = <1>;
353 #size-cells = <0>;
354 status = "disabled";
355 };
356
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100357 sysmmu_fimd0: sysmmu@11e20000 {
Marek Szyprowskif5976ce2015-06-04 08:09:41 +0900358 compatible = "samsung,exynos-sysmmu";
359 reg = <0x11e20000 0x1000>;
Maciej Falkowski937683d2019-09-19 15:45:47 +0200360 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
Marek Szyprowskif5976ce2015-06-04 08:09:41 +0900361 clock-names = "sysmmu", "master";
362 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
363 power-domains = <&pd_lcd0>;
364 #iommu-cells = <0>;
365 };
366
Jaewon Kime0c6e922015-01-12 17:54:54 +0900367 hsotg: hsotg@12480000 {
Krzysztof Kozlowskide653d02020-08-29 19:25:32 +0200368 compatible = "samsung,s3c6400-hsotg";
Jaewon Kime0c6e922015-01-12 17:54:54 +0900369 reg = <0x12480000 0x20000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200370 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
Jaewon Kime0c6e922015-01-12 17:54:54 +0900371 clocks = <&cmu CLK_USBOTG>;
372 clock-names = "otg";
373 phys = <&exynos_usbphy 0>;
374 phy-names = "usb2-phy";
375 status = "disabled";
376 };
377
Tomasz Figa5a992a92014-05-15 06:01:27 +0900378 mshc_0: mshc@12510000 {
Jaehoon Chungb29dd5f2015-10-24 03:42:02 +0900379 compatible = "samsung,exynos5420-dw-mshc";
Tomasz Figa5a992a92014-05-15 06:01:27 +0900380 reg = <0x12510000 0x1000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200381 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900382 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
383 clock-names = "biu", "ciu";
384 fifo-depth = <0x80>;
385 #address-cells = <1>;
386 #size-cells = <0>;
387 status = "disabled";
388 };
389
390 mshc_1: mshc@12520000 {
Jaehoon Chungb29dd5f2015-10-24 03:42:02 +0900391 compatible = "samsung,exynos5420-dw-mshc";
Tomasz Figa5a992a92014-05-15 06:01:27 +0900392 reg = <0x12520000 0x1000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200393 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900394 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
395 clock-names = "biu", "ciu";
396 fifo-depth = <0x80>;
397 #address-cells = <1>;
398 #size-cells = <0>;
399 status = "disabled";
400 };
401
Chanwoo Choi92173e62016-03-31 11:48:03 +0900402 mshc_2: mshc@12530000 {
403 compatible = "samsung,exynos5250-dw-mshc";
404 reg = <0x12530000 0x1000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200405 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
Chanwoo Choi92173e62016-03-31 11:48:03 +0900406 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
407 clock-names = "biu", "ciu";
408 fifo-depth = <0x80>;
409 #address-cells = <1>;
410 #size-cells = <0>;
411 status = "disabled";
412 };
413
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100414 exynos_usbphy: exynos-usbphy@125b0000 {
Jaewon Kim11ab02b2015-01-12 17:54:54 +0900415 compatible = "samsung,exynos3250-usb2-phy";
416 reg = <0x125B0000 0x100>;
417 samsung,pmureg-phandle = <&pmu_system_controller>;
418 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
419 clock-names = "phy", "ref";
420 #phy-cells = <1>;
421 status = "disabled";
422 };
423
Alim Akhtarcfeb53a2022-01-30 13:25:18 +0530424 pdma0: dma-controller@12680000 {
Krzysztof Kozlowskif91423e2020-07-05 20:17:54 +0200425 compatible = "arm,pl330", "arm,primecell";
426 reg = <0x12680000 0x1000>;
427 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&cmu CLK_PDMA0>;
429 clock-names = "apb_pclk";
430 #dma-cells = <1>;
431 #dma-channels = <8>;
432 #dma-requests = <32>;
433 };
Tomasz Figa5a992a92014-05-15 06:01:27 +0900434
Alim Akhtarcfeb53a2022-01-30 13:25:18 +0530435 pdma1: dma-controller@12690000 {
Krzysztof Kozlowskif91423e2020-07-05 20:17:54 +0200436 compatible = "arm,pl330", "arm,primecell";
437 reg = <0x12690000 0x1000>;
438 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&cmu CLK_PDMA1>;
440 clock-names = "apb_pclk";
441 #dma-cells = <1>;
442 #dma-channels = <8>;
443 #dma-requests = <32>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900444 };
445
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100446 adc: adc@126c0000 {
Krzysztof Kozlowski2cf842ba2019-08-23 16:53:56 +0200447 compatible = "samsung,exynos3250-adc";
Naveen Krishna Chatradhidb9bf4d2014-09-16 09:58:00 +0100448 reg = <0x126C0000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200449 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
Chanwoo Choie6ca2d82014-07-22 03:04:00 +0100450 clock-names = "adc", "sclk";
Tomasz Figa5a992a92014-05-15 06:01:27 +0900451 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
452 #io-channel-cells = <1>;
Naveen Krishna Chatradhidb9bf4d2014-09-16 09:58:00 +0100453 samsung,syscon-phandle = <&pmu_system_controller>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900454 status = "disabled";
455 };
456
Marek Szyprowski8386e6a2019-06-27 13:57:25 +0200457 gpu: gpu@13000000 {
458 compatible = "samsung,exynos4210-mali", "arm,mali-400";
459 reg = <0x13000000 0x10000>;
460 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
471 interrupt-names = "gp",
472 "gpmmu",
473 "pp0",
474 "ppmmu0",
475 "pp1",
476 "ppmmu1",
477 "pp2",
478 "ppmmu2",
479 "pp3",
480 "ppmmu3",
481 "pmu";
482 clocks = <&cmu CLK_G3D>,
483 <&cmu CLK_SCLK_G3D>;
484 clock-names = "bus", "core";
485 power-domains = <&pd_g3d>;
486 status = "disabled";
487 /* TODO: operating points for DVFS, assigned clock as 134 MHz */
488 };
489
Jacek Anaszewski752d3a22014-09-24 01:33:23 +0900490 mfc: codec@13400000 {
491 compatible = "samsung,mfc-v7";
492 reg = <0x13400000 0x10000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200493 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
Jacek Anaszewski752d3a22014-09-24 01:33:23 +0900494 clock-names = "mfc", "sclk_mfc";
495 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
Marek Szyprowski0da65872015-01-24 13:16:15 +0900496 power-domains = <&pd_mfc>;
Marek Szyprowskif5976ce2015-06-04 08:09:41 +0900497 iommus = <&sysmmu_mfc>;
Jacek Anaszewski752d3a22014-09-24 01:33:23 +0900498 };
499
Marek Szyprowskif5976ce2015-06-04 08:09:41 +0900500 sysmmu_mfc: sysmmu@13620000 {
501 compatible = "samsung,exynos-sysmmu";
502 reg = <0x13620000 0x1000>;
Maciej Falkowski937683d2019-09-19 15:45:47 +0200503 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
Marek Szyprowskif5976ce2015-06-04 08:09:41 +0900504 clock-names = "sysmmu", "master";
505 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
506 power-domains = <&pd_mfc>;
507 #iommu-cells = <0>;
508 };
509
Tomasz Figa5a992a92014-05-15 06:01:27 +0900510 serial_0: serial@13800000 {
511 compatible = "samsung,exynos4210-uart";
512 reg = <0x13800000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200513 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900514 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
515 clock-names = "uart", "clk_uart_baud0";
Chanwoo Choia9408a62014-07-30 07:57:32 +0900516 pinctrl-names = "default";
517 pinctrl-0 = <&uart0_data &uart0_fctl>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900518 status = "disabled";
519 };
520
521 serial_1: serial@13810000 {
522 compatible = "samsung,exynos4210-uart";
523 reg = <0x13810000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200524 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900525 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
526 clock-names = "uart", "clk_uart_baud0";
Chanwoo Choia9408a62014-07-30 07:57:32 +0900527 pinctrl-names = "default";
528 pinctrl-0 = <&uart1_data>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900529 status = "disabled";
530 };
531
Pankaj Dubeyecaba512016-03-31 11:48:01 +0900532 serial_2: serial@13820000 {
533 compatible = "samsung,exynos4210-uart";
534 reg = <0x13820000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200535 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
Pankaj Dubeyecaba512016-03-31 11:48:01 +0900536 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
537 clock-names = "uart", "clk_uart_baud0";
538 pinctrl-names = "default";
539 pinctrl-0 = <&uart2_data>;
540 status = "disabled";
541 };
542
Tomasz Figa5a992a92014-05-15 06:01:27 +0900543 i2c_0: i2c@13860000 {
544 #address-cells = <1>;
545 #size-cells = <0>;
546 compatible = "samsung,s3c2440-i2c";
547 reg = <0x13860000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200548 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900549 clocks = <&cmu CLK_I2C0>;
550 clock-names = "i2c";
551 pinctrl-names = "default";
552 pinctrl-0 = <&i2c0_bus>;
553 status = "disabled";
554 };
555
556 i2c_1: i2c@13870000 {
557 #address-cells = <1>;
558 #size-cells = <0>;
559 compatible = "samsung,s3c2440-i2c";
560 reg = <0x13870000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200561 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900562 clocks = <&cmu CLK_I2C1>;
563 clock-names = "i2c";
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c1_bus>;
566 status = "disabled";
567 };
568
569 i2c_2: i2c@13880000 {
570 #address-cells = <1>;
571 #size-cells = <0>;
572 compatible = "samsung,s3c2440-i2c";
573 reg = <0x13880000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200574 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900575 clocks = <&cmu CLK_I2C2>;
576 clock-names = "i2c";
577 pinctrl-names = "default";
578 pinctrl-0 = <&i2c2_bus>;
579 status = "disabled";
580 };
581
582 i2c_3: i2c@13890000 {
583 #address-cells = <1>;
584 #size-cells = <0>;
585 compatible = "samsung,s3c2440-i2c";
586 reg = <0x13890000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200587 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900588 clocks = <&cmu CLK_I2C3>;
589 clock-names = "i2c";
590 pinctrl-names = "default";
591 pinctrl-0 = <&i2c3_bus>;
592 status = "disabled";
593 };
594
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100595 i2c_4: i2c@138a0000 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900596 #address-cells = <1>;
597 #size-cells = <0>;
598 compatible = "samsung,s3c2440-i2c";
599 reg = <0x138A0000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200600 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900601 clocks = <&cmu CLK_I2C4>;
602 clock-names = "i2c";
603 pinctrl-names = "default";
604 pinctrl-0 = <&i2c4_bus>;
605 status = "disabled";
606 };
607
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100608 i2c_5: i2c@138b0000 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900609 #address-cells = <1>;
610 #size-cells = <0>;
611 compatible = "samsung,s3c2440-i2c";
612 reg = <0x138B0000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200613 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900614 clocks = <&cmu CLK_I2C5>;
615 clock-names = "i2c";
616 pinctrl-names = "default";
617 pinctrl-0 = <&i2c5_bus>;
618 status = "disabled";
619 };
620
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100621 i2c_6: i2c@138c0000 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900622 #address-cells = <1>;
623 #size-cells = <0>;
624 compatible = "samsung,s3c2440-i2c";
625 reg = <0x138C0000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200626 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900627 clocks = <&cmu CLK_I2C6>;
628 clock-names = "i2c";
629 pinctrl-names = "default";
630 pinctrl-0 = <&i2c6_bus>;
631 status = "disabled";
632 };
633
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100634 i2c_7: i2c@138d0000 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900635 #address-cells = <1>;
636 #size-cells = <0>;
637 compatible = "samsung,s3c2440-i2c";
638 reg = <0x138D0000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200639 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900640 clocks = <&cmu CLK_I2C7>;
641 clock-names = "i2c";
642 pinctrl-names = "default";
643 pinctrl-0 = <&i2c7_bus>;
644 status = "disabled";
645 };
646
647 spi_0: spi@13920000 {
648 compatible = "samsung,exynos4210-spi";
649 reg = <0x13920000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200650 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900651 dmas = <&pdma0 7>, <&pdma0 6>;
652 dma-names = "tx", "rx";
653 #address-cells = <1>;
654 #size-cells = <0>;
655 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
656 clock-names = "spi", "spi_busclk0";
657 samsung,spi-src-clk = <0>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&spi0_bus>;
660 status = "disabled";
661 };
662
663 spi_1: spi@13930000 {
664 compatible = "samsung,exynos4210-spi";
665 reg = <0x13930000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200666 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900667 dmas = <&pdma1 7>, <&pdma1 6>;
668 dma-names = "tx", "rx";
669 #address-cells = <1>;
670 #size-cells = <0>;
671 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
672 clock-names = "spi", "spi_busclk0";
673 samsung,spi-src-clk = <0>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&spi1_bus>;
676 status = "disabled";
677 };
678
Tomasz Figaccaba452014-07-19 04:10:44 +0900679 i2s2: i2s@13970000 {
680 compatible = "samsung,s3c6410-i2s";
681 reg = <0x13970000 0x100>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200682 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figaccaba452014-07-19 04:10:44 +0900683 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
684 clock-names = "iis", "i2s_opclk0";
685 dmas = <&pdma0 14>, <&pdma0 13>;
686 dma-names = "tx", "rx";
687 pinctrl-0 = <&i2s2_bus>;
688 pinctrl-names = "default";
689 status = "disabled";
690 };
691
Krzysztof Kozlowski3be1ecf2017-12-14 21:54:30 +0100692 pwm: pwm@139d0000 {
Tomasz Figa5a992a92014-05-15 06:01:27 +0900693 compatible = "samsung,exynos4210-pwm";
694 reg = <0x139D0000 0x1000>;
Krzysztof Kozlowski9645ab22016-09-16 23:41:57 +0200695 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
Tomasz Figa5a992a92014-05-15 06:01:27 +0900700 #pwm-cells = <3>;
701 status = "disabled";
702 };
703
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100704 ppmu_dmc0: ppmu@106a0000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900705 compatible = "samsung,exynos-ppmu";
706 reg = <0x106a0000 0x2000>;
707 status = "disabled";
708 };
709
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100710 ppmu_dmc1: ppmu@106b0000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900711 compatible = "samsung,exynos-ppmu";
712 reg = <0x106b0000 0x2000>;
713 status = "disabled";
714 };
715
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100716 ppmu_cpu: ppmu@106c0000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900717 compatible = "samsung,exynos-ppmu";
718 reg = <0x106c0000 0x2000>;
719 status = "disabled";
720 };
721
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100722 ppmu_rightbus: ppmu@112a0000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900723 compatible = "samsung,exynos-ppmu";
724 reg = <0x112a0000 0x2000>;
725 clocks = <&cmu CLK_PPMURIGHT>;
726 clock-names = "ppmu";
727 status = "disabled";
728 };
729
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100730 ppmu_leftbus: ppmu@116a0000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900731 compatible = "samsung,exynos-ppmu";
732 reg = <0x116a0000 0x2000>;
733 clocks = <&cmu CLK_PPMULEFT>;
734 clock-names = "ppmu";
735 status = "disabled";
736 };
737
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100738 ppmu_camif: ppmu@11ac0000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900739 compatible = "samsung,exynos-ppmu";
740 reg = <0x11ac0000 0x2000>;
741 clocks = <&cmu CLK_PPMUCAMIF>;
742 clock-names = "ppmu";
743 status = "disabled";
744 };
745
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100746 ppmu_lcd0: ppmu@11e40000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900747 compatible = "samsung,exynos-ppmu";
748 reg = <0x11e40000 0x2000>;
749 clocks = <&cmu CLK_PPMULCD0>;
750 clock-names = "ppmu";
751 status = "disabled";
752 };
753
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100754 ppmu_fsys: ppmu@12630000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900755 compatible = "samsung,exynos-ppmu";
756 reg = <0x12630000 0x2000>;
757 clocks = <&cmu CLK_PPMUFILE>;
758 clock-names = "ppmu";
759 status = "disabled";
760 };
761
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100762 ppmu_g3d: ppmu@13220000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900763 compatible = "samsung,exynos-ppmu";
764 reg = <0x13220000 0x2000>;
765 clocks = <&cmu CLK_PPMUG3D>;
766 clock-names = "ppmu";
767 status = "disabled";
768 };
769
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100770 ppmu_mfc: ppmu@13660000 {
Chanwoo Choie4502362015-02-04 08:10:58 +0900771 compatible = "samsung,exynos-ppmu";
772 reg = <0x13660000 0x2000>;
773 clocks = <&cmu CLK_PPMUMFC_L>;
774 clock-names = "ppmu";
775 status = "disabled";
776 };
Chanwoo Choi6b088a62016-04-11 12:57:49 +0900777
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100778 bus_dmc: bus-dmc {
Chanwoo Choi6b088a62016-04-11 12:57:49 +0900779 compatible = "samsung,exynos-bus";
780 clocks = <&cmu_dmc CLK_DIV_DMC>;
781 clock-names = "bus";
782 operating-points-v2 = <&bus_dmc_opp_table>;
783 status = "disabled";
784 };
785
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100786 bus_dmc_opp_table: opp-table1 {
Chanwoo Choi6b088a62016-04-11 12:57:49 +0900787 compatible = "operating-points-v2";
Chanwoo Choi6b088a62016-04-11 12:57:49 +0900788
Viresh Kumar6a611d12017-04-20 16:25:07 +0530789 opp-50000000 {
Chanwoo Choi6b088a62016-04-11 12:57:49 +0900790 opp-hz = /bits/ 64 <50000000>;
791 opp-microvolt = <800000>;
792 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530793 opp-100000000 {
Chanwoo Choi6b088a62016-04-11 12:57:49 +0900794 opp-hz = /bits/ 64 <100000000>;
795 opp-microvolt = <800000>;
796 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530797 opp-134000000 {
Chanwoo Choi6b088a62016-04-11 12:57:49 +0900798 opp-hz = /bits/ 64 <134000000>;
799 opp-microvolt = <800000>;
800 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530801 opp-200000000 {
Chanwoo Choi6b088a62016-04-11 12:57:49 +0900802 opp-hz = /bits/ 64 <200000000>;
803 opp-microvolt = <825000>;
804 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530805 opp-400000000 {
Chanwoo Choi6b088a62016-04-11 12:57:49 +0900806 opp-hz = /bits/ 64 <400000000>;
807 opp-microvolt = <875000>;
808 };
809 };
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900810
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100811 bus_leftbus: bus-leftbus {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900812 compatible = "samsung,exynos-bus";
813 clocks = <&cmu CLK_DIV_GDL>;
814 clock-names = "bus";
815 operating-points-v2 = <&bus_leftbus_opp_table>;
816 status = "disabled";
817 };
818
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100819 bus_rightbus: bus-rightbus {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900820 compatible = "samsung,exynos-bus";
821 clocks = <&cmu CLK_DIV_GDR>;
822 clock-names = "bus";
823 operating-points-v2 = <&bus_leftbus_opp_table>;
824 status = "disabled";
825 };
826
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100827 bus_lcd0: bus-lcd0 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900828 compatible = "samsung,exynos-bus";
829 clocks = <&cmu CLK_DIV_ACLK_160>;
830 clock-names = "bus";
831 operating-points-v2 = <&bus_leftbus_opp_table>;
832 status = "disabled";
833 };
834
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100835 bus_fsys: bus-fsys {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900836 compatible = "samsung,exynos-bus";
837 clocks = <&cmu CLK_DIV_ACLK_200>;
838 clock-names = "bus";
839 operating-points-v2 = <&bus_leftbus_opp_table>;
840 status = "disabled";
841 };
842
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100843 bus_mcuisp: bus-mcuisp {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900844 compatible = "samsung,exynos-bus";
845 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
846 clock-names = "bus";
847 operating-points-v2 = <&bus_mcuisp_opp_table>;
848 status = "disabled";
849 };
850
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100851 bus_isp: bus-isp {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900852 compatible = "samsung,exynos-bus";
853 clocks = <&cmu CLK_DIV_ACLK_266>;
854 clock-names = "bus";
855 operating-points-v2 = <&bus_isp_opp_table>;
856 status = "disabled";
857 };
858
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100859 bus_peril: bus-peril {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900860 compatible = "samsung,exynos-bus";
861 clocks = <&cmu CLK_DIV_ACLK_100>;
862 clock-names = "bus";
863 operating-points-v2 = <&bus_peril_opp_table>;
864 status = "disabled";
865 };
866
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100867 bus_mfc: bus-mfc {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900868 compatible = "samsung,exynos-bus";
869 clocks = <&cmu CLK_SCLK_MFC>;
870 clock-names = "bus";
871 operating-points-v2 = <&bus_leftbus_opp_table>;
872 status = "disabled";
873 };
874
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100875 bus_leftbus_opp_table: opp-table2 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900876 compatible = "operating-points-v2";
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900877
Viresh Kumar6a611d12017-04-20 16:25:07 +0530878 opp-50000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900879 opp-hz = /bits/ 64 <50000000>;
880 opp-microvolt = <900000>;
881 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530882 opp-80000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900883 opp-hz = /bits/ 64 <80000000>;
884 opp-microvolt = <900000>;
885 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530886 opp-100000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900887 opp-hz = /bits/ 64 <100000000>;
888 opp-microvolt = <1000000>;
889 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530890 opp-134000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900891 opp-hz = /bits/ 64 <134000000>;
892 opp-microvolt = <1000000>;
893 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530894 opp-200000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900895 opp-hz = /bits/ 64 <200000000>;
896 opp-microvolt = <1000000>;
897 };
898 };
899
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100900 bus_mcuisp_opp_table: opp-table3 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900901 compatible = "operating-points-v2";
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900902
Viresh Kumar6a611d12017-04-20 16:25:07 +0530903 opp-50000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900904 opp-hz = /bits/ 64 <50000000>;
905 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530906 opp-80000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900907 opp-hz = /bits/ 64 <80000000>;
908 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530909 opp-100000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900910 opp-hz = /bits/ 64 <100000000>;
911 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530912 opp-200000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900913 opp-hz = /bits/ 64 <200000000>;
914 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530915 opp-400000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900916 opp-hz = /bits/ 64 <400000000>;
917 };
918 };
919
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100920 bus_isp_opp_table: opp-table4 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900921 compatible = "operating-points-v2";
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900922
Viresh Kumar6a611d12017-04-20 16:25:07 +0530923 opp-50000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900924 opp-hz = /bits/ 64 <50000000>;
925 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530926 opp-80000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900927 opp-hz = /bits/ 64 <80000000>;
928 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530929 opp-100000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900930 opp-hz = /bits/ 64 <100000000>;
931 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530932 opp-200000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900933 opp-hz = /bits/ 64 <200000000>;
934 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530935 opp-300000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900936 opp-hz = /bits/ 64 <300000000>;
937 };
938 };
939
Krzysztof Kozlowskib357e6a2020-11-05 19:41:08 +0100940 bus_peril_opp_table: opp-table5 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900941 compatible = "operating-points-v2";
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900942
Viresh Kumar6a611d12017-04-20 16:25:07 +0530943 opp-50000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900944 opp-hz = /bits/ 64 <50000000>;
945 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530946 opp-80000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900947 opp-hz = /bits/ 64 <80000000>;
948 };
Viresh Kumar6a611d12017-04-20 16:25:07 +0530949 opp-100000000 {
Chanwoo Choi304d10a2016-04-11 12:57:51 +0900950 opp-hz = /bits/ 64 <100000000>;
951 };
952 };
Tomasz Figa5a992a92014-05-15 06:01:27 +0900953 };
954};
955
956#include "exynos3250-pinctrl.dtsi"
Krzysztof Kozlowskia03e9da2018-04-16 20:11:25 +0200957#include "exynos-syscon-restart.dtsi"