Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __PXAFB_H__ |
| 2 | #define __PXAFB_H__ |
| 3 | |
| 4 | /* |
| 5 | * linux/drivers/video/pxafb.h |
| 6 | * -- Intel PXA250/210 LCD Controller Frame Buffer Device |
| 7 | * |
| 8 | * Copyright (C) 1999 Eric A. Thomas. |
| 9 | * Copyright (C) 2004 Jean-Frederic Clere. |
| 10 | * Copyright (C) 2004 Ian Campbell. |
| 11 | * Copyright (C) 2004 Jeff Lackey. |
| 12 | * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas |
| 13 | * which in turn is |
| 14 | * Based on acornfb.c Copyright (C) Russell King. |
| 15 | * |
| 16 | * 2001-08-03: Cliff Brake <cbrake@acclent.com> |
| 17 | * - ported SA1100 code to PXA |
| 18 | * |
| 19 | * This file is subject to the terms and conditions of the GNU General Public |
| 20 | * License. See the file COPYING in the main directory of this archive |
| 21 | * for more details. |
| 22 | */ |
| 23 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | /* PXA LCD DMA descriptor */ |
| 25 | struct pxafb_dma_descriptor { |
| 26 | unsigned int fdadr; |
| 27 | unsigned int fsadr; |
| 28 | unsigned int fidr; |
| 29 | unsigned int ldcmd; |
| 30 | }; |
| 31 | |
eric miao | 2c42dd8 | 2008-04-30 00:52:21 -0700 | [diff] [blame] | 32 | enum { |
| 33 | PAL_NONE = -1, |
| 34 | PAL_BASE = 0, |
| 35 | PAL_OV1 = 1, |
| 36 | PAL_OV2 = 2, |
| 37 | PAL_MAX, |
| 38 | }; |
| 39 | |
| 40 | enum { |
| 41 | DMA_BASE = 0, |
| 42 | DMA_UPPER = 0, |
| 43 | DMA_LOWER = 1, |
| 44 | DMA_OV1 = 1, |
| 45 | DMA_OV2_Y = 2, |
| 46 | DMA_OV2_Cb = 3, |
| 47 | DMA_OV2_Cr = 4, |
| 48 | DMA_CURSOR = 5, |
| 49 | DMA_CMD = 6, |
| 50 | DMA_MAX, |
| 51 | }; |
| 52 | |
| 53 | /* maximum palette size - 256 entries, each 4 bytes long */ |
| 54 | #define PALETTE_SIZE (256 * 4) |
Eric Miao | 3c42a44 | 2008-04-30 00:52:26 -0700 | [diff] [blame] | 55 | #define CMD_BUFF_SIZE (1024 * 50) |
eric miao | 2c42dd8 | 2008-04-30 00:52:21 -0700 | [diff] [blame] | 56 | |
Eric Miao | 6e35484 | 2008-12-17 16:50:43 +0800 | [diff] [blame] | 57 | /* NOTE: the palette and frame dma descriptors are doubled to allow |
| 58 | * the 2nd set for branch settings (FBRx) |
| 59 | */ |
eric miao | 2c42dd8 | 2008-04-30 00:52:21 -0700 | [diff] [blame] | 60 | struct pxafb_dma_buff { |
| 61 | unsigned char palette[PAL_MAX * PALETTE_SIZE]; |
Eric Miao | 3c42a44 | 2008-04-30 00:52:26 -0700 | [diff] [blame] | 62 | uint16_t cmd_buff[CMD_BUFF_SIZE]; |
Eric Miao | 6e35484 | 2008-12-17 16:50:43 +0800 | [diff] [blame] | 63 | struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2]; |
| 64 | struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2]; |
eric miao | 2c42dd8 | 2008-04-30 00:52:21 -0700 | [diff] [blame] | 65 | }; |
| 66 | |
Eric Miao | 198fc10 | 2008-12-23 17:49:43 +0800 | [diff] [blame] | 67 | enum { |
| 68 | OVERLAY1, |
| 69 | OVERLAY2, |
| 70 | }; |
| 71 | |
| 72 | enum { |
| 73 | OVERLAY_FORMAT_RGB = 0, |
| 74 | OVERLAY_FORMAT_YUV444_PACKED, |
| 75 | OVERLAY_FORMAT_YUV444_PLANAR, |
| 76 | OVERLAY_FORMAT_YUV422_PLANAR, |
| 77 | OVERLAY_FORMAT_YUV420_PLANAR, |
| 78 | }; |
| 79 | |
| 80 | #define NONSTD_TO_XPOS(x) (((x) >> 0) & 0x3ff) |
| 81 | #define NONSTD_TO_YPOS(x) (((x) >> 10) & 0x3ff) |
| 82 | #define NONSTD_TO_PFOR(x) (((x) >> 20) & 0x7) |
| 83 | |
| 84 | struct pxafb_layer; |
| 85 | |
| 86 | struct pxafb_layer_ops { |
| 87 | void (*enable)(struct pxafb_layer *); |
| 88 | void (*disable)(struct pxafb_layer *); |
| 89 | void (*setup)(struct pxafb_layer *); |
| 90 | }; |
| 91 | |
| 92 | struct pxafb_layer { |
| 93 | struct fb_info fb; |
| 94 | int id; |
Vasily Khoruzhick | 1b98d7c | 2011-03-11 11:20:47 +0200 | [diff] [blame] | 95 | int registered; |
| 96 | uint32_t usage; |
Eric Miao | 198fc10 | 2008-12-23 17:49:43 +0800 | [diff] [blame] | 97 | uint32_t control[2]; |
| 98 | |
| 99 | struct pxafb_layer_ops *ops; |
| 100 | |
| 101 | void __iomem *video_mem; |
| 102 | unsigned long video_mem_phys; |
| 103 | size_t video_mem_size; |
| 104 | struct completion branch_done; |
| 105 | |
| 106 | struct pxafb_info *fbi; |
| 107 | }; |
| 108 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | struct pxafb_info { |
| 110 | struct fb_info fb; |
| 111 | struct device *dev; |
Russell King | 72e3524 | 2007-08-20 10:18:42 +0100 | [diff] [blame] | 112 | struct clk *clk; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 113 | |
eric miao | ce4fb7b | 2008-04-30 00:52:21 -0700 | [diff] [blame] | 114 | void __iomem *mmio_base; |
| 115 | |
eric miao | 2c42dd8 | 2008-04-30 00:52:21 -0700 | [diff] [blame] | 116 | struct pxafb_dma_buff *dma_buff; |
Eric Miao | 77e1967 | 2008-12-16 11:54:34 +0800 | [diff] [blame] | 117 | size_t dma_buff_size; |
eric miao | 2c42dd8 | 2008-04-30 00:52:21 -0700 | [diff] [blame] | 118 | dma_addr_t dma_buff_phys; |
Eric Miao | 6e35484 | 2008-12-17 16:50:43 +0800 | [diff] [blame] | 119 | dma_addr_t fdadr[DMA_MAX * 2]; |
eric miao | 2c42dd8 | 2008-04-30 00:52:21 -0700 | [diff] [blame] | 120 | |
Eric Miao | 77e1967 | 2008-12-16 11:54:34 +0800 | [diff] [blame] | 121 | void __iomem *video_mem; /* virtual address of frame buffer */ |
| 122 | unsigned long video_mem_phys; /* physical address of frame buffer */ |
| 123 | size_t video_mem_size; /* size of the frame buffer */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | u16 * palette_cpu; /* virtual address of palette memory */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | u_int palette_size; |
| 126 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | u_int lccr0; |
| 128 | u_int lccr3; |
Hans J. Koch | 9ffa739 | 2007-10-16 01:28:41 -0700 | [diff] [blame] | 129 | u_int lccr4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | u_int cmap_inverse:1, |
| 131 | cmap_static:1, |
| 132 | unused:30; |
| 133 | |
| 134 | u_int reg_lccr0; |
| 135 | u_int reg_lccr1; |
| 136 | u_int reg_lccr2; |
| 137 | u_int reg_lccr3; |
Hans J. Koch | 9ffa739 | 2007-10-16 01:28:41 -0700 | [diff] [blame] | 138 | u_int reg_lccr4; |
Eric Miao | 3c42a44 | 2008-04-30 00:52:26 -0700 | [diff] [blame] | 139 | u_int reg_cmdcr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | |
Richard Purdie | ba44cd2 | 2005-09-09 13:10:03 -0700 | [diff] [blame] | 141 | unsigned long hsync_time; |
| 142 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 143 | volatile u_char state; |
| 144 | volatile u_char task_state; |
Matthias Kaehlcke | b91dbce | 2008-07-23 21:31:14 -0700 | [diff] [blame] | 145 | struct mutex ctrlr_lock; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | wait_queue_head_t ctrlr_wait; |
| 147 | struct work_struct task; |
| 148 | |
Eric Miao | 2ba162b | 2008-04-30 00:52:24 -0700 | [diff] [blame] | 149 | struct completion disable_done; |
| 150 | |
Eric Miao | 3c42a44 | 2008-04-30 00:52:26 -0700 | [diff] [blame] | 151 | #ifdef CONFIG_FB_PXA_SMARTPANEL |
| 152 | uint16_t *smart_cmds; |
| 153 | size_t n_smart_cmds; |
| 154 | struct completion command_done; |
| 155 | struct completion refresh_done; |
| 156 | struct task_struct *smart_thread; |
| 157 | #endif |
| 158 | |
Eric Miao | 198fc10 | 2008-12-23 17:49:43 +0800 | [diff] [blame] | 159 | #ifdef CONFIG_FB_PXA_OVERLAY |
| 160 | struct pxafb_layer overlay[2]; |
| 161 | #endif |
| 162 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | #ifdef CONFIG_CPU_FREQ |
| 164 | struct notifier_block freq_transition; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 165 | #endif |
Eric Miao | a5718a1 | 2008-11-11 21:50:39 +0800 | [diff] [blame] | 166 | |
Daniel Mack | 31e1391 | 2018-07-24 19:11:26 +0200 | [diff] [blame] | 167 | struct regulator *lcd_supply; |
| 168 | bool lcd_supply_enabled; |
| 169 | |
Eric Miao | a5718a1 | 2008-11-11 21:50:39 +0800 | [diff] [blame] | 170 | void (*lcd_power)(int, struct fb_var_screeninfo *); |
| 171 | void (*backlight_power)(int); |
Robert Jarzmik | f3621a6 | 2015-12-12 22:27:10 +0100 | [diff] [blame] | 172 | |
| 173 | struct pxafb_mach_info *inf; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | }; |
| 175 | |
| 176 | #define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member) |
| 177 | |
| 178 | /* |
| 179 | * These are the actions for set_ctrlr_state |
| 180 | */ |
| 181 | #define C_DISABLE (0) |
| 182 | #define C_ENABLE (1) |
| 183 | #define C_DISABLE_CLKCHANGE (2) |
| 184 | #define C_ENABLE_CLKCHANGE (3) |
| 185 | #define C_REENABLE (4) |
| 186 | #define C_DISABLE_PM (5) |
| 187 | #define C_ENABLE_PM (6) |
| 188 | #define C_STARTUP (7) |
| 189 | |
| 190 | #define PXA_NAME "PXA" |
| 191 | |
| 192 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | * Minimum X and Y resolutions |
| 194 | */ |
| 195 | #define MIN_XRES 64 |
| 196 | #define MIN_YRES 64 |
| 197 | |
Eric Miao | 3f16ff6 | 2008-12-18 22:51:54 +0800 | [diff] [blame] | 198 | /* maximum X and Y resolutions - note these are limits from the register |
| 199 | * bits length instead of the real ones |
| 200 | */ |
| 201 | #define MAX_XRES 1024 |
| 202 | #define MAX_YRES 1024 |
| 203 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | #endif /* __PXAFB_H__ */ |