Thomas Gleixner | 97fb5e8 | 2019-05-29 07:17:58 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 2 | /* |
Yaniv Gardi | 54b879b | 2016-03-10 17:37:05 +0200 | [diff] [blame] | 3 | * Copyright (c) 2013-2016, Linux Foundation. All rights reserved. |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
Lee Jones | e1a7752 | 2019-06-17 12:54:54 +0100 | [diff] [blame] | 6 | #include <linux/acpi.h> |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 7 | #include <linux/time.h> |
Bart Van Assche | 3f06f78 | 2022-04-19 15:58:08 -0700 | [diff] [blame] | 8 | #include <linux/clk.h> |
| 9 | #include <linux/delay.h> |
| 10 | #include <linux/module.h> |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 11 | #include <linux/of.h> |
| 12 | #include <linux/platform_device.h> |
| 13 | #include <linux/phy/phy.h> |
Bjorn Andersson | b8416b2 | 2019-08-28 12:17:55 -0700 | [diff] [blame] | 14 | #include <linux/gpio/consumer.h> |
Evan Green | 12fd5f250 | 2019-03-21 10:17:58 -0700 | [diff] [blame] | 15 | #include <linux/reset-controller.h> |
Asutosh Das | 80b2100 | 2020-03-25 11:29:02 -0700 | [diff] [blame] | 16 | #include <linux/devfreq.h> |
Yaniv Gardi | 4b9ad0b | 2016-03-10 17:37:19 +0200 | [diff] [blame] | 17 | |
Bart Van Assche | dd11376 | 2022-05-11 14:25:52 -0700 | [diff] [blame] | 18 | #include <ufs/ufshcd.h> |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 19 | #include "ufshcd-pltfrm.h" |
Bart Van Assche | dd11376 | 2022-05-11 14:25:52 -0700 | [diff] [blame] | 20 | #include <ufs/unipro.h> |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 21 | #include "ufs-qcom.h" |
Bart Van Assche | dd11376 | 2022-05-11 14:25:52 -0700 | [diff] [blame] | 22 | #include <ufs/ufshci.h> |
| 23 | #include <ufs/ufs_quirks.h> |
Bart Van Assche | 3f06f78 | 2022-04-19 15:58:08 -0700 | [diff] [blame] | 24 | |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 25 | #define MCQ_QCFGPTR_MASK GENMASK(7, 0) |
| 26 | #define MCQ_QCFGPTR_UNIT 0x200 |
| 27 | #define MCQ_SQATTR_OFFSET(c) \ |
| 28 | ((((c) >> 16) & MCQ_QCFGPTR_MASK) * MCQ_QCFGPTR_UNIT) |
| 29 | #define MCQ_QCFG_SIZE 0x40 |
| 30 | |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 31 | enum { |
| 32 | TSTBUS_UAWM, |
| 33 | TSTBUS_UARM, |
| 34 | TSTBUS_TXUC, |
| 35 | TSTBUS_RXUC, |
| 36 | TSTBUS_DFC, |
| 37 | TSTBUS_TRLUT, |
| 38 | TSTBUS_TMRLUT, |
| 39 | TSTBUS_OCSC, |
| 40 | TSTBUS_UTP_HCI, |
| 41 | TSTBUS_COMBINED, |
| 42 | TSTBUS_WRAPPER, |
| 43 | TSTBUS_UNIPRO, |
| 44 | TSTBUS_MAX, |
| 45 | }; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 46 | |
| 47 | static struct ufs_qcom_host *ufs_qcom_hosts[MAX_UFS_QCOM_HOSTS]; |
| 48 | |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 49 | static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 50 | static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, |
| 51 | u32 clk_cycles); |
| 52 | |
Evan Green | 12fd5f250 | 2019-03-21 10:17:58 -0700 | [diff] [blame] | 53 | static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) |
| 54 | { |
| 55 | return container_of(rcd, struct ufs_qcom_host, rcdev); |
| 56 | } |
| 57 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 58 | static int ufs_qcom_host_clk_get(struct device *dev, |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 59 | const char *name, struct clk **clk_out, bool optional) |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 60 | { |
| 61 | struct clk *clk; |
| 62 | int err = 0; |
| 63 | |
| 64 | clk = devm_clk_get(dev, name); |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 65 | if (!IS_ERR(clk)) { |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 66 | *clk_out = clk; |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 67 | return 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 68 | } |
| 69 | |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 70 | err = PTR_ERR(clk); |
| 71 | |
| 72 | if (optional && err == -ENOENT) { |
| 73 | *clk_out = NULL; |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | if (err != -EPROBE_DEFER) |
| 78 | dev_err(dev, "failed to get %s err %d\n", name, err); |
| 79 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 80 | return err; |
| 81 | } |
| 82 | |
| 83 | static int ufs_qcom_host_clk_enable(struct device *dev, |
| 84 | const char *name, struct clk *clk) |
| 85 | { |
| 86 | int err = 0; |
| 87 | |
| 88 | err = clk_prepare_enable(clk); |
| 89 | if (err) |
| 90 | dev_err(dev, "%s: %s enable failed %d\n", __func__, name, err); |
| 91 | |
| 92 | return err; |
| 93 | } |
| 94 | |
| 95 | static void ufs_qcom_disable_lane_clks(struct ufs_qcom_host *host) |
| 96 | { |
| 97 | if (!host->is_lane_clks_enabled) |
| 98 | return; |
| 99 | |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 100 | clk_disable_unprepare(host->tx_l1_sync_clk); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 101 | clk_disable_unprepare(host->tx_l0_sync_clk); |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 102 | clk_disable_unprepare(host->rx_l1_sync_clk); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 103 | clk_disable_unprepare(host->rx_l0_sync_clk); |
| 104 | |
| 105 | host->is_lane_clks_enabled = false; |
| 106 | } |
| 107 | |
| 108 | static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host) |
| 109 | { |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 110 | int err; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 111 | struct device *dev = host->hba->dev; |
| 112 | |
| 113 | if (host->is_lane_clks_enabled) |
| 114 | return 0; |
| 115 | |
| 116 | err = ufs_qcom_host_clk_enable(dev, "rx_lane0_sync_clk", |
| 117 | host->rx_l0_sync_clk); |
| 118 | if (err) |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 119 | return err; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 120 | |
| 121 | err = ufs_qcom_host_clk_enable(dev, "tx_lane0_sync_clk", |
| 122 | host->tx_l0_sync_clk); |
| 123 | if (err) |
| 124 | goto disable_rx_l0; |
| 125 | |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 126 | err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk", |
Yaniv Gardi | 54b879b | 2016-03-10 17:37:05 +0200 | [diff] [blame] | 127 | host->rx_l1_sync_clk); |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 128 | if (err) |
| 129 | goto disable_tx_l0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 130 | |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 131 | err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk", |
Yaniv Gardi | 54b879b | 2016-03-10 17:37:05 +0200 | [diff] [blame] | 132 | host->tx_l1_sync_clk); |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 133 | if (err) |
| 134 | goto disable_rx_l1; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 135 | |
| 136 | host->is_lane_clks_enabled = true; |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 137 | |
| 138 | return 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 139 | |
| 140 | disable_rx_l1: |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 141 | clk_disable_unprepare(host->rx_l1_sync_clk); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 142 | disable_tx_l0: |
| 143 | clk_disable_unprepare(host->tx_l0_sync_clk); |
| 144 | disable_rx_l0: |
| 145 | clk_disable_unprepare(host->rx_l0_sync_clk); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 146 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 147 | return err; |
| 148 | } |
| 149 | |
| 150 | static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host) |
| 151 | { |
| 152 | int err = 0; |
| 153 | struct device *dev = host->hba->dev; |
| 154 | |
Lee Jones | e1a7752 | 2019-06-17 12:54:54 +0100 | [diff] [blame] | 155 | if (has_acpi_companion(dev)) |
| 156 | return 0; |
| 157 | |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 158 | err = ufs_qcom_host_clk_get(dev, "rx_lane0_sync_clk", |
| 159 | &host->rx_l0_sync_clk, false); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 160 | if (err) |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 161 | return err; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 162 | |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 163 | err = ufs_qcom_host_clk_get(dev, "tx_lane0_sync_clk", |
| 164 | &host->tx_l0_sync_clk, false); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 165 | if (err) |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 166 | return err; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 167 | |
Yaniv Gardi | 54b879b | 2016-03-10 17:37:05 +0200 | [diff] [blame] | 168 | /* In case of single lane per direction, don't read lane1 clocks */ |
| 169 | if (host->hba->lanes_per_direction > 1) { |
| 170 | err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk", |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 171 | &host->rx_l1_sync_clk, false); |
Yaniv Gardi | 54b879b | 2016-03-10 17:37:05 +0200 | [diff] [blame] | 172 | if (err) |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 173 | return err; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 174 | |
Yaniv Gardi | 54b879b | 2016-03-10 17:37:05 +0200 | [diff] [blame] | 175 | err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk", |
Venkat Gopalakrishnan | 5adaf1e | 2018-10-12 19:25:02 -0700 | [diff] [blame] | 176 | &host->tx_l1_sync_clk, true); |
Yaniv Gardi | 54b879b | 2016-03-10 17:37:05 +0200 | [diff] [blame] | 177 | } |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 178 | |
| 179 | return 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 180 | } |
| 181 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 182 | static int ufs_qcom_check_hibern8(struct ufs_hba *hba) |
| 183 | { |
| 184 | int err; |
| 185 | u32 tx_fsm_val = 0; |
| 186 | unsigned long timeout = jiffies + msecs_to_jiffies(HBRN8_POLL_TOUT_MS); |
| 187 | |
| 188 | do { |
| 189 | err = ufshcd_dme_get(hba, |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 190 | UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, |
| 191 | UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), |
| 192 | &tx_fsm_val); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 193 | if (err || tx_fsm_val == TX_FSM_HIBERN8) |
| 194 | break; |
| 195 | |
| 196 | /* sleep for max. 200us */ |
| 197 | usleep_range(100, 200); |
| 198 | } while (time_before(jiffies, timeout)); |
| 199 | |
| 200 | /* |
| 201 | * we might have scheduled out for long during polling so |
| 202 | * check the state again. |
| 203 | */ |
| 204 | if (time_after(jiffies, timeout)) |
| 205 | err = ufshcd_dme_get(hba, |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 206 | UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, |
| 207 | UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), |
| 208 | &tx_fsm_val); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 209 | |
| 210 | if (err) { |
| 211 | dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", |
| 212 | __func__, err); |
| 213 | } else if (tx_fsm_val != TX_FSM_HIBERN8) { |
| 214 | err = tx_fsm_val; |
| 215 | dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", |
| 216 | __func__, err); |
| 217 | } |
| 218 | |
| 219 | return err; |
| 220 | } |
| 221 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 222 | static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) |
| 223 | { |
| 224 | ufshcd_rmwl(host->hba, QUNIPRO_SEL, |
| 225 | ufs_qcom_cap_qunipro(host) ? QUNIPRO_SEL : 0, |
| 226 | REG_UFS_CFG1); |
Abel Vesa | 9c02aa2 | 2023-01-19 17:14:05 +0200 | [diff] [blame] | 227 | |
| 228 | if (host->hw_ver.major == 0x05) |
| 229 | ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); |
| 230 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 231 | /* make sure above configuration is applied before we return */ |
| 232 | mb(); |
| 233 | } |
| 234 | |
Lee Jones | bc5b681 | 2020-07-23 13:24:09 +0100 | [diff] [blame] | 235 | /* |
Can Guo | 870b127 | 2019-11-14 22:09:25 -0800 | [diff] [blame] | 236 | * ufs_qcom_host_reset - reset host controller and PHY |
| 237 | */ |
| 238 | static int ufs_qcom_host_reset(struct ufs_hba *hba) |
| 239 | { |
| 240 | int ret = 0; |
| 241 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Nitin Rawat | 4a79157 | 2021-02-23 21:36:48 -0800 | [diff] [blame] | 242 | bool reenable_intr = false; |
Can Guo | 870b127 | 2019-11-14 22:09:25 -0800 | [diff] [blame] | 243 | |
| 244 | if (!host->core_reset) { |
| 245 | dev_warn(hba->dev, "%s: reset control not set\n", __func__); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 246 | return 0; |
Can Guo | 870b127 | 2019-11-14 22:09:25 -0800 | [diff] [blame] | 247 | } |
| 248 | |
Nitin Rawat | 4a79157 | 2021-02-23 21:36:48 -0800 | [diff] [blame] | 249 | reenable_intr = hba->is_irq_enabled; |
| 250 | disable_irq(hba->irq); |
| 251 | hba->is_irq_enabled = false; |
| 252 | |
Can Guo | 870b127 | 2019-11-14 22:09:25 -0800 | [diff] [blame] | 253 | ret = reset_control_assert(host->core_reset); |
| 254 | if (ret) { |
| 255 | dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", |
| 256 | __func__, ret); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 257 | return ret; |
Can Guo | 870b127 | 2019-11-14 22:09:25 -0800 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | /* |
| 261 | * The hardware requirement for delay between assert/deassert |
| 262 | * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to |
| 263 | * ~125us (4/32768). To be on the safe side add 200us delay. |
| 264 | */ |
| 265 | usleep_range(200, 210); |
| 266 | |
| 267 | ret = reset_control_deassert(host->core_reset); |
| 268 | if (ret) |
| 269 | dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", |
| 270 | __func__, ret); |
| 271 | |
| 272 | usleep_range(1000, 1100); |
| 273 | |
Nitin Rawat | 4a79157 | 2021-02-23 21:36:48 -0800 | [diff] [blame] | 274 | if (reenable_intr) { |
| 275 | enable_irq(hba->irq); |
| 276 | hba->is_irq_enabled = true; |
| 277 | } |
| 278 | |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 279 | return 0; |
Can Guo | 870b127 | 2019-11-14 22:09:25 -0800 | [diff] [blame] | 280 | } |
| 281 | |
Manivannan Sadhasivam | c270986 | 2022-12-22 19:39:58 +0530 | [diff] [blame] | 282 | static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) |
| 283 | { |
| 284 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
| 285 | |
| 286 | if (host->hw_ver.major == 0x1) { |
| 287 | /* |
| 288 | * HS-G3 operations may not reliably work on legacy QCOM |
| 289 | * UFS host controller hardware even though capability |
| 290 | * exchange during link startup phase may end up |
| 291 | * negotiating maximum supported gear as G3. |
| 292 | * Hence downgrade the maximum supported gear to HS-G2. |
| 293 | */ |
| 294 | return UFS_HS_G2; |
Manivannan Sadhasivam | 2c407fe | 2022-12-22 19:40:00 +0530 | [diff] [blame] | 295 | } else if (host->hw_ver.major >= 0x4) { |
| 296 | return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); |
Manivannan Sadhasivam | c270986 | 2022-12-22 19:39:58 +0530 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | /* Default is HS-G3 */ |
| 300 | return UFS_HS_G3; |
| 301 | } |
| 302 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 303 | static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) |
| 304 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 305 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 306 | struct phy *phy = host->generic_phy; |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 307 | int ret; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 308 | |
Can Guo | 870b127 | 2019-11-14 22:09:25 -0800 | [diff] [blame] | 309 | /* Reset UFS Host Controller and PHY */ |
| 310 | ret = ufs_qcom_host_reset(hba); |
| 311 | if (ret) |
| 312 | dev_warn(hba->dev, "%s: host reset returned %d\n", |
| 313 | __func__, ret); |
| 314 | |
Vivek Gautam | 052553a | 2017-10-12 11:49:36 +0530 | [diff] [blame] | 315 | /* phy initialization - calibrate the phy */ |
| 316 | ret = phy_init(phy); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 317 | if (ret) { |
Vivek Gautam | 052553a | 2017-10-12 11:49:36 +0530 | [diff] [blame] | 318 | dev_err(hba->dev, "%s: phy init failed, ret = %d\n", |
Yaniv Gardi | 4b9ad0b | 2016-03-10 17:37:19 +0200 | [diff] [blame] | 319 | __func__, ret); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 320 | return ret; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 321 | } |
| 322 | |
Manivannan Sadhasivam | baf5dda | 2022-12-22 19:39:59 +0530 | [diff] [blame] | 323 | phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); |
| 324 | |
Vivek Gautam | 052553a | 2017-10-12 11:49:36 +0530 | [diff] [blame] | 325 | /* power on phy - start serdes and phy's power and clocks */ |
| 326 | ret = phy_power_on(phy); |
| 327 | if (ret) { |
| 328 | dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 329 | __func__, ret); |
Vivek Gautam | 052553a | 2017-10-12 11:49:36 +0530 | [diff] [blame] | 330 | goto out_disable_phy; |
| 331 | } |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 332 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 333 | ufs_qcom_select_unipro_mode(host); |
| 334 | |
Vivek Gautam | 052553a | 2017-10-12 11:49:36 +0530 | [diff] [blame] | 335 | return 0; |
| 336 | |
| 337 | out_disable_phy: |
Vivek Gautam | 052553a | 2017-10-12 11:49:36 +0530 | [diff] [blame] | 338 | phy_exit(phy); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 339 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 340 | return ret; |
| 341 | } |
| 342 | |
| 343 | /* |
| 344 | * The UTP controller has a number of internal clock gating cells (CGCs). |
| 345 | * Internal hardware sub-modules within the UTP controller control the CGCs. |
| 346 | * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved |
| 347 | * in a specific operation, UTP controller CGCs are by default disabled and |
| 348 | * this function enables them (after every UFS link startup) to save some power |
| 349 | * leakage. |
| 350 | */ |
| 351 | static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba) |
| 352 | { |
| 353 | ufshcd_writel(hba, |
| 354 | ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL, |
| 355 | REG_UFS_CFG2); |
| 356 | |
| 357 | /* Ensure that HW clock gating is enabled before next operations */ |
| 358 | mb(); |
| 359 | } |
| 360 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 361 | static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, |
| 362 | enum ufs_notify_change_status status) |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 363 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 364 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 365 | int err = 0; |
| 366 | |
| 367 | switch (status) { |
| 368 | case PRE_CHANGE: |
| 369 | ufs_qcom_power_up_sequence(hba); |
| 370 | /* |
| 371 | * The PHY PLL output is the source of tx/rx lane symbol |
| 372 | * clocks, hence, enable the lane clocks only after PHY |
| 373 | * is initialized. |
| 374 | */ |
| 375 | err = ufs_qcom_enable_lane_clks(host); |
| 376 | break; |
| 377 | case POST_CHANGE: |
| 378 | /* check if UFS PHY moved from DISABLED to HIBERN8 */ |
| 379 | err = ufs_qcom_check_hibern8(hba); |
| 380 | ufs_qcom_enable_hw_clk_gating(hba); |
Eric Biggers | df4ec2f | 2020-07-10 00:20:12 -0700 | [diff] [blame] | 381 | ufs_qcom_ice_enable(host); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 382 | break; |
| 383 | default: |
| 384 | dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); |
| 385 | err = -EINVAL; |
| 386 | break; |
| 387 | } |
| 388 | return err; |
| 389 | } |
| 390 | |
Lee Jones | bc5b681 | 2020-07-23 13:24:09 +0100 | [diff] [blame] | 391 | /* |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 392 | * Returns zero for success and non-zero in case of a failure |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 393 | */ |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 394 | static int ufs_qcom_cfg_timers(struct ufs_hba *hba, u32 gear, |
| 395 | u32 hs, u32 rate, bool update_link_startup_timer) |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 396 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 397 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 398 | struct ufs_clk_info *clki; |
| 399 | u32 core_clk_period_in_ns; |
| 400 | u32 tx_clk_cycles_per_us = 0; |
| 401 | unsigned long core_clk_rate = 0; |
| 402 | u32 core_clk_cycles_per_us = 0; |
| 403 | |
| 404 | static u32 pwm_fr_table[][2] = { |
| 405 | {UFS_PWM_G1, 0x1}, |
| 406 | {UFS_PWM_G2, 0x1}, |
| 407 | {UFS_PWM_G3, 0x1}, |
| 408 | {UFS_PWM_G4, 0x1}, |
| 409 | }; |
| 410 | |
| 411 | static u32 hs_fr_table_rA[][2] = { |
| 412 | {UFS_HS_G1, 0x1F}, |
| 413 | {UFS_HS_G2, 0x3e}, |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 414 | {UFS_HS_G3, 0x7D}, |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 415 | }; |
| 416 | |
| 417 | static u32 hs_fr_table_rB[][2] = { |
| 418 | {UFS_HS_G1, 0x24}, |
| 419 | {UFS_HS_G2, 0x49}, |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 420 | {UFS_HS_G3, 0x92}, |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 421 | }; |
| 422 | |
Yaniv Gardi | 81c7e06 | 2015-05-17 18:54:58 +0300 | [diff] [blame] | 423 | /* |
| 424 | * The Qunipro controller does not use following registers: |
| 425 | * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG & |
| 426 | * UFS_REG_PA_LINK_STARTUP_TIMER |
| 427 | * But UTP controller uses SYS1CLK_1US_REG register for Interrupt |
| 428 | * Aggregation logic. |
| 429 | */ |
| 430 | if (ufs_qcom_cap_qunipro(host) && !ufshcd_is_intr_aggr_allowed(hba)) |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 431 | return 0; |
Yaniv Gardi | 81c7e06 | 2015-05-17 18:54:58 +0300 | [diff] [blame] | 432 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 433 | if (gear == 0) { |
| 434 | dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 435 | return -EINVAL; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 436 | } |
| 437 | |
| 438 | list_for_each_entry(clki, &hba->clk_list_head, list) { |
| 439 | if (!strcmp(clki->name, "core_clk")) |
| 440 | core_clk_rate = clk_get_rate(clki->clk); |
| 441 | } |
| 442 | |
| 443 | /* If frequency is smaller than 1MHz, set to 1MHz */ |
| 444 | if (core_clk_rate < DEFAULT_CLK_RATE_HZ) |
| 445 | core_clk_rate = DEFAULT_CLK_RATE_HZ; |
| 446 | |
| 447 | core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC; |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 448 | if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { |
| 449 | ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US); |
| 450 | /* |
| 451 | * make sure above write gets applied before we return from |
| 452 | * this function. |
| 453 | */ |
| 454 | mb(); |
| 455 | } |
| 456 | |
| 457 | if (ufs_qcom_cap_qunipro(host)) |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 458 | return 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 459 | |
| 460 | core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate; |
| 461 | core_clk_period_in_ns <<= OFFSET_CLK_NS_REG; |
| 462 | core_clk_period_in_ns &= MASK_CLK_NS_REG; |
| 463 | |
| 464 | switch (hs) { |
| 465 | case FASTAUTO_MODE: |
| 466 | case FAST_MODE: |
| 467 | if (rate == PA_HS_MODE_A) { |
| 468 | if (gear > ARRAY_SIZE(hs_fr_table_rA)) { |
| 469 | dev_err(hba->dev, |
| 470 | "%s: index %d exceeds table size %zu\n", |
| 471 | __func__, gear, |
| 472 | ARRAY_SIZE(hs_fr_table_rA)); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 473 | return -EINVAL; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 474 | } |
| 475 | tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; |
| 476 | } else if (rate == PA_HS_MODE_B) { |
| 477 | if (gear > ARRAY_SIZE(hs_fr_table_rB)) { |
| 478 | dev_err(hba->dev, |
| 479 | "%s: index %d exceeds table size %zu\n", |
| 480 | __func__, gear, |
| 481 | ARRAY_SIZE(hs_fr_table_rB)); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 482 | return -EINVAL; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 483 | } |
| 484 | tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; |
| 485 | } else { |
| 486 | dev_err(hba->dev, "%s: invalid rate = %d\n", |
| 487 | __func__, rate); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 488 | return -EINVAL; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 489 | } |
| 490 | break; |
| 491 | case SLOWAUTO_MODE: |
| 492 | case SLOW_MODE: |
| 493 | if (gear > ARRAY_SIZE(pwm_fr_table)) { |
| 494 | dev_err(hba->dev, |
| 495 | "%s: index %d exceeds table size %zu\n", |
| 496 | __func__, gear, |
| 497 | ARRAY_SIZE(pwm_fr_table)); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 498 | return -EINVAL; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 499 | } |
| 500 | tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; |
| 501 | break; |
| 502 | case UNCHANGED: |
| 503 | default: |
| 504 | dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 505 | return -EINVAL; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 506 | } |
| 507 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 508 | if (ufshcd_readl(hba, REG_UFS_TX_SYMBOL_CLK_NS_US) != |
| 509 | (core_clk_period_in_ns | tx_clk_cycles_per_us)) { |
| 510 | /* this register 2 fields shall be written at once */ |
| 511 | ufshcd_writel(hba, core_clk_period_in_ns | tx_clk_cycles_per_us, |
| 512 | REG_UFS_TX_SYMBOL_CLK_NS_US); |
| 513 | /* |
| 514 | * make sure above write gets applied before we return from |
| 515 | * this function. |
| 516 | */ |
| 517 | mb(); |
| 518 | } |
| 519 | |
Abel Vesa | 9c02aa2 | 2023-01-19 17:14:05 +0200 | [diff] [blame] | 520 | if (update_link_startup_timer && host->hw_ver.major != 0x5) { |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 521 | ufshcd_writel(hba, ((core_clk_rate / MSEC_PER_SEC) * 100), |
Abel Vesa | 9c02aa2 | 2023-01-19 17:14:05 +0200 | [diff] [blame] | 522 | REG_UFS_CFG0); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 523 | /* |
| 524 | * make sure that this configuration is applied before |
| 525 | * we return |
| 526 | */ |
| 527 | mb(); |
| 528 | } |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 529 | |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 530 | return 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 531 | } |
| 532 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 533 | static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, |
| 534 | enum ufs_notify_change_status status) |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 535 | { |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 536 | int err = 0; |
| 537 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 538 | |
| 539 | switch (status) { |
| 540 | case PRE_CHANGE: |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 541 | if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE, |
| 542 | 0, true)) { |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 543 | dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", |
| 544 | __func__); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 545 | return -EINVAL; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 546 | } |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 547 | |
| 548 | if (ufs_qcom_cap_qunipro(host)) |
| 549 | /* |
| 550 | * set unipro core clock cycles to 150 & clear clock |
| 551 | * divider |
| 552 | */ |
| 553 | err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, |
| 554 | 150); |
| 555 | |
Yaniv Gardi | 4b9ad0b | 2016-03-10 17:37:19 +0200 | [diff] [blame] | 556 | /* |
| 557 | * Some UFS devices (and may be host) have issues if LCC is |
| 558 | * enabled. So we are setting PA_Local_TX_LCC_Enable to 0 |
| 559 | * before link startup which will make sure that both host |
| 560 | * and device TX LCC are disabled once link startup is |
| 561 | * completed. |
| 562 | */ |
| 563 | if (ufshcd_get_local_unipro_ver(hba) != UFS_UNIPRO_VER_1_41) |
Stanley Chu | 984eaac | 2020-02-07 15:03:57 +0800 | [diff] [blame] | 564 | err = ufshcd_disable_host_tx_lcc(hba); |
Yaniv Gardi | 4b9ad0b | 2016-03-10 17:37:19 +0200 | [diff] [blame] | 565 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 566 | break; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 567 | default: |
| 568 | break; |
| 569 | } |
| 570 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 571 | return err; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 572 | } |
| 573 | |
Ziqi Chen | b61d041 | 2021-01-08 18:56:25 +0800 | [diff] [blame] | 574 | static void ufs_qcom_device_reset_ctrl(struct ufs_hba *hba, bool asserted) |
| 575 | { |
| 576 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
| 577 | |
| 578 | /* reset gpio is optional */ |
| 579 | if (!host->device_reset) |
| 580 | return; |
| 581 | |
| 582 | gpiod_set_value_cansleep(host->device_reset, asserted); |
| 583 | } |
| 584 | |
Peter Wang | 9561f58 | 2021-10-06 13:47:05 +0800 | [diff] [blame] | 585 | static int ufs_qcom_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, |
| 586 | enum ufs_notify_change_status status) |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 587 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 588 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 589 | struct phy *phy = host->generic_phy; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 590 | |
Peter Wang | 9561f58 | 2021-10-06 13:47:05 +0800 | [diff] [blame] | 591 | if (status == PRE_CHANGE) |
| 592 | return 0; |
| 593 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 594 | if (ufs_qcom_is_link_off(hba)) { |
| 595 | /* |
| 596 | * Disable the tx/rx lane symbol clocks before PHY is |
| 597 | * powered down as the PLL source should be disabled |
| 598 | * after downstream clocks are disabled. |
| 599 | */ |
| 600 | ufs_qcom_disable_lane_clks(host); |
| 601 | phy_power_off(phy); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 602 | |
Ziqi Chen | b61d041 | 2021-01-08 18:56:25 +0800 | [diff] [blame] | 603 | /* reset the connected UFS device during power down */ |
| 604 | ufs_qcom_device_reset_ctrl(hba, true); |
| 605 | |
Evan Green | 3f6d176 | 2019-03-21 10:18:00 -0700 | [diff] [blame] | 606 | } else if (!ufs_qcom_is_link_active(hba)) { |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 607 | ufs_qcom_disable_lane_clks(host); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 608 | } |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 609 | |
Jason Yan | f336c70 | 2020-04-18 15:06:25 +0800 | [diff] [blame] | 610 | return 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 611 | } |
| 612 | |
| 613 | static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) |
| 614 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 615 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 616 | struct phy *phy = host->generic_phy; |
| 617 | int err; |
| 618 | |
Evan Green | 3f6d176 | 2019-03-21 10:18:00 -0700 | [diff] [blame] | 619 | if (ufs_qcom_is_link_off(hba)) { |
| 620 | err = phy_power_on(phy); |
| 621 | if (err) { |
| 622 | dev_err(hba->dev, "%s: failed PHY power on: %d\n", |
| 623 | __func__, err); |
| 624 | return err; |
| 625 | } |
| 626 | |
| 627 | err = ufs_qcom_enable_lane_clks(host); |
| 628 | if (err) |
| 629 | return err; |
| 630 | |
| 631 | } else if (!ufs_qcom_is_link_active(hba)) { |
| 632 | err = ufs_qcom_enable_lane_clks(host); |
| 633 | if (err) |
| 634 | return err; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 635 | } |
| 636 | |
Bart Van Assche | bee40dc | 2022-04-19 15:58:05 -0700 | [diff] [blame] | 637 | return ufs_qcom_ice_resume(host); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 638 | } |
| 639 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 640 | static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable) |
| 641 | { |
| 642 | if (host->dev_ref_clk_ctrl_mmio && |
| 643 | (enable ^ host->is_dev_ref_clk_enabled)) { |
| 644 | u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); |
| 645 | |
| 646 | if (enable) |
| 647 | temp |= host->dev_ref_clk_en_mask; |
| 648 | else |
| 649 | temp &= ~host->dev_ref_clk_en_mask; |
| 650 | |
| 651 | /* |
| 652 | * If we are here to disable this clock it might be immediately |
| 653 | * after entering into hibern8 in which case we need to make |
Can Guo | 1cbadd0 | 2020-02-10 19:40:50 -0800 | [diff] [blame] | 654 | * sure that device ref_clk is active for specific time after |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 655 | * hibern8 enter. |
| 656 | */ |
Can Guo | 1cbadd0 | 2020-02-10 19:40:50 -0800 | [diff] [blame] | 657 | if (!enable) { |
| 658 | unsigned long gating_wait; |
| 659 | |
| 660 | gating_wait = host->hba->dev_info.clk_gating_wait_us; |
| 661 | if (!gating_wait) { |
| 662 | udelay(1); |
| 663 | } else { |
| 664 | /* |
| 665 | * bRefClkGatingWaitTime defines the minimum |
| 666 | * time for which the reference clock is |
| 667 | * required by device during transition from |
| 668 | * HS-MODE to LS-MODE or HIBERN8 state. Give it |
| 669 | * more delay to be on the safe side. |
| 670 | */ |
| 671 | gating_wait += 10; |
| 672 | usleep_range(gating_wait, gating_wait + 10); |
| 673 | } |
| 674 | } |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 675 | |
| 676 | writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); |
| 677 | |
Manivannan Sadhasivam | 8eecddf | 2022-05-04 14:12:10 +0530 | [diff] [blame] | 678 | /* |
| 679 | * Make sure the write to ref_clk reaches the destination and |
| 680 | * not stored in a Write Buffer (WB). |
| 681 | */ |
| 682 | readl(host->dev_ref_clk_ctrl_mmio); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 683 | |
| 684 | /* |
| 685 | * If we call hibern8 exit after this, we need to make sure that |
| 686 | * device ref_clk is stable for at least 1us before the hibern8 |
| 687 | * exit command. |
| 688 | */ |
| 689 | if (enable) |
| 690 | udelay(1); |
| 691 | |
| 692 | host->is_dev_ref_clk_enabled = enable; |
| 693 | } |
| 694 | } |
| 695 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 696 | static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 697 | enum ufs_notify_change_status status, |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 698 | struct ufs_pa_layer_attr *dev_max_params, |
| 699 | struct ufs_pa_layer_attr *dev_req_params) |
| 700 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 701 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Stanley Chu | e4c0ee3 | 2019-03-16 13:04:42 +0800 | [diff] [blame] | 702 | struct ufs_dev_params ufs_qcom_cap; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 703 | int ret = 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 704 | |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 705 | if (!dev_req_params) { |
| 706 | pr_err("%s: incoming dev_req_params is NULL\n", __func__); |
| 707 | return -EINVAL; |
| 708 | } |
| 709 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 710 | switch (status) { |
| 711 | case PRE_CHANGE: |
Stanley Chu | 8beef54 | 2020-11-16 14:50:49 +0800 | [diff] [blame] | 712 | ufshcd_init_pwr_dev_param(&ufs_qcom_cap); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 713 | ufs_qcom_cap.hs_rate = UFS_QCOM_LIMIT_HS_RATE; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 714 | |
Manivannan Sadhasivam | c270986 | 2022-12-22 19:39:58 +0530 | [diff] [blame] | 715 | /* This driver only supports symmetic gear setting i.e., hs_tx_gear == hs_rx_gear */ |
| 716 | ufs_qcom_cap.hs_tx_gear = ufs_qcom_cap.hs_rx_gear = ufs_qcom_get_hs_gear(hba); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 717 | |
Stanley Chu | e4c0ee3 | 2019-03-16 13:04:42 +0800 | [diff] [blame] | 718 | ret = ufshcd_get_pwr_dev_param(&ufs_qcom_cap, |
| 719 | dev_max_params, |
| 720 | dev_req_params); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 721 | if (ret) { |
Andrew Halaney | 1026f7d | 2022-12-01 17:08:10 -0600 | [diff] [blame] | 722 | dev_err(hba->dev, "%s: failed to determine capabilities\n", |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 723 | __func__); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 724 | return ret; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 725 | } |
| 726 | |
Manivannan Sadhasivam | baf5dda | 2022-12-22 19:39:59 +0530 | [diff] [blame] | 727 | /* Use the agreed gear */ |
| 728 | host->hs_gear = dev_req_params->gear_tx; |
| 729 | |
Yaniv Gardi | f37aabc | 2016-03-10 17:37:20 +0200 | [diff] [blame] | 730 | /* enable the device ref clock before changing to HS mode */ |
| 731 | if (!ufshcd_is_hs_mode(&hba->pwr_info) && |
| 732 | ufshcd_is_hs_mode(dev_req_params)) |
| 733 | ufs_qcom_dev_ref_clk_ctrl(host, true); |
Can Guo | 518b32f | 2020-02-11 21:38:29 -0800 | [diff] [blame] | 734 | |
| 735 | if (host->hw_ver.major >= 0x4) { |
Stanley Chu | d9fa1e7 | 2020-11-16 14:50:54 +0800 | [diff] [blame] | 736 | ufshcd_dme_configure_adapt(hba, |
| 737 | dev_req_params->gear_tx, |
| 738 | PA_INITIAL_ADAPT); |
Can Guo | 518b32f | 2020-02-11 21:38:29 -0800 | [diff] [blame] | 739 | } |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 740 | break; |
| 741 | case POST_CHANGE: |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 742 | if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 743 | dev_req_params->pwr_rx, |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 744 | dev_req_params->hs_rate, false)) { |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 745 | dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", |
| 746 | __func__); |
| 747 | /* |
| 748 | * we return error code at the end of the routine, |
| 749 | * but continue to configure UFS_PHY_TX_LANE_ENABLE |
| 750 | * and bus voting as usual |
| 751 | */ |
| 752 | ret = -EINVAL; |
| 753 | } |
| 754 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 755 | /* cache the power mode parameters to use internally */ |
| 756 | memcpy(&host->dev_req_params, |
| 757 | dev_req_params, sizeof(*dev_req_params)); |
Yaniv Gardi | f37aabc | 2016-03-10 17:37:20 +0200 | [diff] [blame] | 758 | |
| 759 | /* disable the device ref clock if entered PWM mode */ |
| 760 | if (ufshcd_is_hs_mode(&hba->pwr_info) && |
| 761 | !ufshcd_is_hs_mode(dev_req_params)) |
| 762 | ufs_qcom_dev_ref_clk_ctrl(host, false); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 763 | break; |
| 764 | default: |
| 765 | ret = -EINVAL; |
| 766 | break; |
| 767 | } |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 768 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 769 | return ret; |
| 770 | } |
| 771 | |
Subhash Jadavani | 56d4a18 | 2016-12-05 19:25:32 -0800 | [diff] [blame] | 772 | static int ufs_qcom_quirk_host_pa_saveconfigtime(struct ufs_hba *hba) |
| 773 | { |
| 774 | int err; |
| 775 | u32 pa_vs_config_reg1; |
| 776 | |
| 777 | err = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), |
| 778 | &pa_vs_config_reg1); |
| 779 | if (err) |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 780 | return err; |
Subhash Jadavani | 56d4a18 | 2016-12-05 19:25:32 -0800 | [diff] [blame] | 781 | |
| 782 | /* Allow extension of MSB bits of PA_SaveConfigTime attribute */ |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 783 | return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), |
Subhash Jadavani | 56d4a18 | 2016-12-05 19:25:32 -0800 | [diff] [blame] | 784 | (pa_vs_config_reg1 | (1 << 12))); |
Subhash Jadavani | 56d4a18 | 2016-12-05 19:25:32 -0800 | [diff] [blame] | 785 | } |
| 786 | |
| 787 | static int ufs_qcom_apply_dev_quirks(struct ufs_hba *hba) |
| 788 | { |
| 789 | int err = 0; |
| 790 | |
| 791 | if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) |
| 792 | err = ufs_qcom_quirk_host_pa_saveconfigtime(hba); |
| 793 | |
Can Guo | 27ff2c6 | 2020-02-23 20:09:22 -0800 | [diff] [blame] | 794 | if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) |
| 795 | hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; |
| 796 | |
Subhash Jadavani | 56d4a18 | 2016-12-05 19:25:32 -0800 | [diff] [blame] | 797 | return err; |
| 798 | } |
| 799 | |
Yaniv Gardi | ae97758 | 2015-05-17 18:55:06 +0300 | [diff] [blame] | 800 | static u32 ufs_qcom_get_ufs_hci_version(struct ufs_hba *hba) |
| 801 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 802 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | ae97758 | 2015-05-17 18:55:06 +0300 | [diff] [blame] | 803 | |
| 804 | if (host->hw_ver.major == 0x1) |
Caleb Connolly | f065aca | 2021-03-10 15:33:51 +0000 | [diff] [blame] | 805 | return ufshci_version(1, 1); |
Yaniv Gardi | ae97758 | 2015-05-17 18:55:06 +0300 | [diff] [blame] | 806 | else |
Caleb Connolly | f065aca | 2021-03-10 15:33:51 +0000 | [diff] [blame] | 807 | return ufshci_version(2, 0); |
Yaniv Gardi | ae97758 | 2015-05-17 18:55:06 +0300 | [diff] [blame] | 808 | } |
| 809 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 810 | /** |
| 811 | * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks |
| 812 | * @hba: host controller instance |
| 813 | * |
| 814 | * QCOM UFS host controller might have some non standard behaviours (quirks) |
| 815 | * than what is specified by UFSHCI specification. Advertise all such |
| 816 | * quirks to standard UFS host controller driver so standard takes them into |
| 817 | * account. |
| 818 | */ |
| 819 | static void ufs_qcom_advertise_quirks(struct ufs_hba *hba) |
| 820 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 821 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 822 | |
Yaniv Gardi | 81c7e06 | 2015-05-17 18:54:58 +0300 | [diff] [blame] | 823 | if (host->hw_ver.major == 0x01) { |
Yaniv Gardi | 8163743 | 2015-05-17 18:55:02 +0300 | [diff] [blame] | 824 | hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS |
Yaniv Gardi | 2c0cc2e | 2015-05-17 18:55:04 +0300 | [diff] [blame] | 825 | | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP |
| 826 | | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 827 | |
Yaniv Gardi | 81c7e06 | 2015-05-17 18:54:58 +0300 | [diff] [blame] | 828 | if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) |
| 829 | hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 830 | |
| 831 | hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; |
Yaniv Gardi | 81c7e06 | 2015-05-17 18:54:58 +0300 | [diff] [blame] | 832 | } |
| 833 | |
Subhash Jadavani | 69a6fff | 2018-05-03 16:37:19 +0530 | [diff] [blame] | 834 | if (host->hw_ver.major == 0x2) { |
Yaniv Gardi | ae97758 | 2015-05-17 18:55:06 +0300 | [diff] [blame] | 835 | hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; |
Yaniv Gardi | 2f01837 | 2015-05-17 18:55:00 +0300 | [diff] [blame] | 836 | |
Yaniv Gardi | cad2e03 | 2015-03-31 17:37:14 +0300 | [diff] [blame] | 837 | if (!ufs_qcom_cap_qunipro(host)) |
| 838 | /* Legacy UniPro mode still need following quirks */ |
Yaniv Gardi | 8163743 | 2015-05-17 18:55:02 +0300 | [diff] [blame] | 839 | hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS |
Yaniv Gardi | 2c0cc2e | 2015-05-17 18:55:04 +0300 | [diff] [blame] | 840 | | UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE |
Yaniv Gardi | 8163743 | 2015-05-17 18:55:02 +0300 | [diff] [blame] | 841 | | UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP); |
Yaniv Gardi | cad2e03 | 2015-03-31 17:37:14 +0300 | [diff] [blame] | 842 | } |
Manivannan Sadhasivam | baf5dda | 2022-12-22 19:39:59 +0530 | [diff] [blame] | 843 | |
| 844 | if (host->hw_ver.major > 0x3) |
| 845 | hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; |
Yaniv Gardi | cad2e03 | 2015-03-31 17:37:14 +0300 | [diff] [blame] | 846 | } |
| 847 | |
| 848 | static void ufs_qcom_set_caps(struct ufs_hba *hba) |
| 849 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 850 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | cad2e03 | 2015-03-31 17:37:14 +0300 | [diff] [blame] | 851 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 852 | hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; |
Peter Wang | 87bd050 | 2022-08-04 10:54:22 +0800 | [diff] [blame] | 853 | hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 854 | hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; |
Asutosh Das | 04ee8a0 | 2020-04-22 14:41:44 -0700 | [diff] [blame] | 855 | hba->caps |= UFSHCD_CAP_WB_EN; |
Eric Biggers | df4ec2f | 2020-07-10 00:20:12 -0700 | [diff] [blame] | 856 | hba->caps |= UFSHCD_CAP_CRYPTO; |
Asutosh Das | 61906fd | 2020-10-27 12:10:37 -0700 | [diff] [blame] | 857 | hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; |
Manivannan Sadhasivam | 6f21d92 | 2022-05-04 14:12:12 +0530 | [diff] [blame] | 858 | hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 859 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 860 | if (host->hw_ver.major >= 0x2) { |
| 861 | host->caps = UFS_QCOM_CAP_QUNIPRO | |
| 862 | UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 863 | } |
| 864 | } |
| 865 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 866 | /** |
| 867 | * ufs_qcom_setup_clocks - enables/disable clocks |
| 868 | * @hba: host controller instance |
| 869 | * @on: If true, enable clocks else disable them. |
Subhash Jadavani | 1e879e8 | 2016-10-06 21:48:22 -0700 | [diff] [blame] | 870 | * @status: PRE_CHANGE or POST_CHANGE notify |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 871 | * |
| 872 | * Returns 0 on success, non-zero on failure. |
| 873 | */ |
Subhash Jadavani | 1e879e8 | 2016-10-06 21:48:22 -0700 | [diff] [blame] | 874 | static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on, |
| 875 | enum ufs_notify_change_status status) |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 876 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 877 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 878 | |
| 879 | /* |
| 880 | * In case ufs_qcom_init() is not yet done, simply ignore. |
| 881 | * This ufs_qcom_setup_clocks() shall be called from |
| 882 | * ufs_qcom_init() after init is done. |
| 883 | */ |
| 884 | if (!host) |
| 885 | return 0; |
| 886 | |
Can Guo | 8240dd9 | 2020-02-10 19:40:46 -0800 | [diff] [blame] | 887 | switch (status) { |
| 888 | case PRE_CHANGE: |
Sai Prakash Ranjan | 68bdb3d | 2020-08-04 21:40:33 +0530 | [diff] [blame] | 889 | if (!on) { |
Can Guo | 8240dd9 | 2020-02-10 19:40:46 -0800 | [diff] [blame] | 890 | if (!ufs_qcom_is_link_active(hba)) { |
| 891 | /* disable device ref_clk */ |
| 892 | ufs_qcom_dev_ref_clk_ctrl(host, false); |
| 893 | } |
Vivek Gautam | feb3d79 | 2016-11-08 15:37:48 +0530 | [diff] [blame] | 894 | } |
Can Guo | 8240dd9 | 2020-02-10 19:40:46 -0800 | [diff] [blame] | 895 | break; |
| 896 | case POST_CHANGE: |
| 897 | if (on) { |
| 898 | /* enable the device ref clock for HS mode*/ |
| 899 | if (ufshcd_is_hs_mode(&hba->pwr_info)) |
| 900 | ufs_qcom_dev_ref_clk_ctrl(host, true); |
Can Guo | 8240dd9 | 2020-02-10 19:40:46 -0800 | [diff] [blame] | 901 | } |
| 902 | break; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 903 | } |
| 904 | |
ChanWoo Lee | c4adf17 | 2021-09-07 13:41:11 +0900 | [diff] [blame] | 905 | return 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 906 | } |
| 907 | |
Evan Green | 12fd5f250 | 2019-03-21 10:17:58 -0700 | [diff] [blame] | 908 | static int |
| 909 | ufs_qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) |
| 910 | { |
| 911 | struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); |
| 912 | |
Evan Green | 12fd5f250 | 2019-03-21 10:17:58 -0700 | [diff] [blame] | 913 | ufs_qcom_assert_reset(host->hba); |
| 914 | /* provide 1ms delay to let the reset pulse propagate. */ |
| 915 | usleep_range(1000, 1100); |
| 916 | return 0; |
| 917 | } |
| 918 | |
| 919 | static int |
| 920 | ufs_qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) |
| 921 | { |
| 922 | struct ufs_qcom_host *host = rcdev_to_ufs_host(rcdev); |
| 923 | |
Evan Green | 12fd5f250 | 2019-03-21 10:17:58 -0700 | [diff] [blame] | 924 | ufs_qcom_deassert_reset(host->hba); |
| 925 | |
| 926 | /* |
| 927 | * after reset deassertion, phy will need all ref clocks, |
| 928 | * voltage, current to settle down before starting serdes. |
| 929 | */ |
| 930 | usleep_range(1000, 1100); |
| 931 | return 0; |
| 932 | } |
| 933 | |
| 934 | static const struct reset_control_ops ufs_qcom_reset_ops = { |
| 935 | .assert = ufs_qcom_reset_assert, |
| 936 | .deassert = ufs_qcom_reset_deassert, |
| 937 | }; |
| 938 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 939 | /** |
| 940 | * ufs_qcom_init - bind phy with controller |
| 941 | * @hba: host controller instance |
| 942 | * |
| 943 | * Binds PHY with controller and powers up PHY enabling clocks |
| 944 | * and regulators. |
| 945 | * |
| 946 | * Returns -EPROBE_DEFER if binding fails, returns negative error |
| 947 | * on phy power up failure and returns zero on success. |
| 948 | */ |
| 949 | static int ufs_qcom_init(struct ufs_hba *hba) |
| 950 | { |
| 951 | int err; |
| 952 | struct device *dev = hba->dev; |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 953 | struct platform_device *pdev = to_platform_device(dev); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 954 | struct ufs_qcom_host *host; |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 955 | struct resource *res; |
Can Guo | 96f08cc | 2020-11-25 18:01:01 -0800 | [diff] [blame] | 956 | struct ufs_clk_info *clki; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 957 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 958 | host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); |
| 959 | if (!host) { |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 960 | dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 961 | return -ENOMEM; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 962 | } |
| 963 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 964 | /* Make a two way bind between the qcom host and the hba */ |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 965 | host->hba = hba; |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 966 | ufshcd_set_variant(hba, host); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 967 | |
Manivannan Sadhasivam | 223b17e | 2022-05-04 14:12:08 +0530 | [diff] [blame] | 968 | /* Setup the optional reset control of HCI */ |
| 969 | host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); |
Can Guo | 870b127 | 2019-11-14 22:09:25 -0800 | [diff] [blame] | 970 | if (IS_ERR(host->core_reset)) { |
Manivannan Sadhasivam | 223b17e | 2022-05-04 14:12:08 +0530 | [diff] [blame] | 971 | err = dev_err_probe(dev, PTR_ERR(host->core_reset), |
| 972 | "Failed to get reset control\n"); |
| 973 | goto out_variant_clear; |
Can Guo | 870b127 | 2019-11-14 22:09:25 -0800 | [diff] [blame] | 974 | } |
| 975 | |
Evan Green | 12fd5f250 | 2019-03-21 10:17:58 -0700 | [diff] [blame] | 976 | /* Fire up the reset controller. Failure here is non-fatal. */ |
| 977 | host->rcdev.of_node = dev->of_node; |
| 978 | host->rcdev.ops = &ufs_qcom_reset_ops; |
| 979 | host->rcdev.owner = dev->driver->owner; |
| 980 | host->rcdev.nr_resets = 1; |
| 981 | err = devm_reset_controller_register(dev, &host->rcdev); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 982 | if (err) |
Evan Green | 12fd5f250 | 2019-03-21 10:17:58 -0700 | [diff] [blame] | 983 | dev_warn(dev, "Failed to register reset controller\n"); |
Evan Green | 12fd5f250 | 2019-03-21 10:17:58 -0700 | [diff] [blame] | 984 | |
Manivannan Sadhasivam | c9ed9a6 | 2022-05-04 14:12:09 +0530 | [diff] [blame] | 985 | if (!has_acpi_companion(dev)) { |
| 986 | host->generic_phy = devm_phy_get(dev, "ufsphy"); |
| 987 | if (IS_ERR(host->generic_phy)) { |
| 988 | err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); |
Lee Jones | e1a7752 | 2019-06-17 12:54:54 +0100 | [diff] [blame] | 989 | goto out_variant_clear; |
| 990 | } |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 991 | } |
| 992 | |
Bjorn Andersson | b8416b2 | 2019-08-28 12:17:55 -0700 | [diff] [blame] | 993 | host->device_reset = devm_gpiod_get_optional(dev, "reset", |
| 994 | GPIOD_OUT_HIGH); |
| 995 | if (IS_ERR(host->device_reset)) { |
| 996 | err = PTR_ERR(host->device_reset); |
| 997 | if (err != -EPROBE_DEFER) |
| 998 | dev_err(dev, "failed to acquire reset gpio: %d\n", err); |
| 999 | goto out_variant_clear; |
| 1000 | } |
| 1001 | |
Yaniv Gardi | bfdbe8b | 2015-03-31 17:37:13 +0300 | [diff] [blame] | 1002 | ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, |
| 1003 | &host->hw_ver.minor, &host->hw_ver.step); |
| 1004 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1005 | /* |
| 1006 | * for newer controllers, device reference clock control bit has |
| 1007 | * moved inside UFS controller register address space itself. |
| 1008 | */ |
| 1009 | if (host->hw_ver.major >= 0x02) { |
| 1010 | host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; |
| 1011 | host->dev_ref_clk_en_mask = BIT(26); |
| 1012 | } else { |
| 1013 | /* "dev_ref_clk_ctrl_mem" is optional resource */ |
Eric Biggers | 083dd78 | 2020-07-10 00:20:09 -0700 | [diff] [blame] | 1014 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
| 1015 | "dev_ref_clk_ctrl_mem"); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1016 | if (res) { |
| 1017 | host->dev_ref_clk_ctrl_mmio = |
| 1018 | devm_ioremap_resource(dev, res); |
Ye Bin | 790f9a4 | 2021-04-09 15:55:22 +0800 | [diff] [blame] | 1019 | if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1020 | host->dev_ref_clk_ctrl_mmio = NULL; |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1021 | host->dev_ref_clk_en_mask = BIT(5); |
| 1022 | } |
| 1023 | } |
| 1024 | |
Can Guo | 96f08cc | 2020-11-25 18:01:01 -0800 | [diff] [blame] | 1025 | list_for_each_entry(clki, &hba->clk_list_head, list) { |
| 1026 | if (!strcmp(clki->name, "core_clk_unipro")) |
| 1027 | clki->keep_link_active = true; |
| 1028 | } |
| 1029 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1030 | err = ufs_qcom_init_lane_clks(host); |
| 1031 | if (err) |
Vivek Gautam | 052553a | 2017-10-12 11:49:36 +0530 | [diff] [blame] | 1032 | goto out_variant_clear; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1033 | |
Yaniv Gardi | cad2e03 | 2015-03-31 17:37:14 +0300 | [diff] [blame] | 1034 | ufs_qcom_set_caps(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1035 | ufs_qcom_advertise_quirks(hba); |
| 1036 | |
Eric Biggers | df4ec2f | 2020-07-10 00:20:12 -0700 | [diff] [blame] | 1037 | err = ufs_qcom_ice_init(host); |
| 1038 | if (err) |
| 1039 | goto out_variant_clear; |
| 1040 | |
Subhash Jadavani | 1e879e8 | 2016-10-06 21:48:22 -0700 | [diff] [blame] | 1041 | ufs_qcom_setup_clocks(hba, true, POST_CHANGE); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1042 | |
| 1043 | if (hba->dev->id < MAX_UFS_QCOM_HOSTS) |
| 1044 | ufs_qcom_hosts[hba->dev->id] = host; |
| 1045 | |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1046 | ufs_qcom_get_default_testbus_cfg(host); |
| 1047 | err = ufs_qcom_testbus_config(host); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 1048 | if (err) |
| 1049 | /* Failure is non-fatal */ |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1050 | dev_warn(dev, "%s: failed to configure the testbus %d\n", |
| 1051 | __func__, err); |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1052 | |
Manivannan Sadhasivam | baf5dda | 2022-12-22 19:39:59 +0530 | [diff] [blame] | 1053 | /* |
| 1054 | * Power up the PHY using the minimum supported gear (UFS_HS_G2). |
| 1055 | * Switching to max gear will be performed during reinit if supported. |
| 1056 | */ |
| 1057 | host->hs_gear = UFS_HS_G2; |
| 1058 | |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 1059 | return 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1060 | |
Bjorn Andersson | a6854df | 2016-11-19 22:34:51 -0800 | [diff] [blame] | 1061 | out_variant_clear: |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 1062 | ufshcd_set_variant(hba, NULL); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 1063 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1064 | return err; |
| 1065 | } |
| 1066 | |
| 1067 | static void ufs_qcom_exit(struct ufs_hba *hba) |
| 1068 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 1069 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1070 | |
| 1071 | ufs_qcom_disable_lane_clks(host); |
| 1072 | phy_power_off(host->generic_phy); |
Vivek Gautam | d7fe6b6 | 2016-11-08 15:37:50 +0530 | [diff] [blame] | 1073 | phy_exit(host->generic_phy); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1074 | } |
| 1075 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1076 | static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba, |
| 1077 | u32 clk_cycles) |
| 1078 | { |
| 1079 | int err; |
| 1080 | u32 core_clk_ctrl_reg; |
| 1081 | |
| 1082 | if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK) |
| 1083 | return -EINVAL; |
| 1084 | |
| 1085 | err = ufshcd_dme_get(hba, |
| 1086 | UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), |
| 1087 | &core_clk_ctrl_reg); |
| 1088 | if (err) |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 1089 | return err; |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1090 | |
| 1091 | core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK; |
| 1092 | core_clk_ctrl_reg |= clk_cycles; |
| 1093 | |
| 1094 | /* Clear CORE_CLK_DIV_EN */ |
| 1095 | core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; |
| 1096 | |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 1097 | return ufshcd_dme_set(hba, |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1098 | UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), |
| 1099 | core_clk_ctrl_reg); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1100 | } |
| 1101 | |
| 1102 | static int ufs_qcom_clk_scale_up_pre_change(struct ufs_hba *hba) |
| 1103 | { |
| 1104 | /* nothing to do as of now */ |
| 1105 | return 0; |
| 1106 | } |
| 1107 | |
| 1108 | static int ufs_qcom_clk_scale_up_post_change(struct ufs_hba *hba) |
| 1109 | { |
| 1110 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
| 1111 | |
| 1112 | if (!ufs_qcom_cap_qunipro(host)) |
| 1113 | return 0; |
| 1114 | |
| 1115 | /* set unipro core clock cycles to 150 and clear clock divider */ |
| 1116 | return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 150); |
| 1117 | } |
| 1118 | |
| 1119 | static int ufs_qcom_clk_scale_down_pre_change(struct ufs_hba *hba) |
| 1120 | { |
| 1121 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
| 1122 | int err; |
| 1123 | u32 core_clk_ctrl_reg; |
| 1124 | |
| 1125 | if (!ufs_qcom_cap_qunipro(host)) |
| 1126 | return 0; |
| 1127 | |
| 1128 | err = ufshcd_dme_get(hba, |
| 1129 | UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), |
| 1130 | &core_clk_ctrl_reg); |
| 1131 | |
| 1132 | /* make sure CORE_CLK_DIV_EN is cleared */ |
| 1133 | if (!err && |
| 1134 | (core_clk_ctrl_reg & DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT)) { |
| 1135 | core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT; |
| 1136 | err = ufshcd_dme_set(hba, |
| 1137 | UIC_ARG_MIB(DME_VS_CORE_CLK_CTRL), |
| 1138 | core_clk_ctrl_reg); |
| 1139 | } |
| 1140 | |
| 1141 | return err; |
| 1142 | } |
| 1143 | |
| 1144 | static int ufs_qcom_clk_scale_down_post_change(struct ufs_hba *hba) |
| 1145 | { |
| 1146 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
| 1147 | |
| 1148 | if (!ufs_qcom_cap_qunipro(host)) |
| 1149 | return 0; |
| 1150 | |
| 1151 | /* set unipro core clock cycles to 75 and clear clock divider */ |
| 1152 | return ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba, 75); |
| 1153 | } |
| 1154 | |
| 1155 | static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, |
| 1156 | bool scale_up, enum ufs_notify_change_status status) |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1157 | { |
Yaniv Gardi | 1ce5898 | 2015-10-28 13:15:47 +0200 | [diff] [blame] | 1158 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1159 | struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params; |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1160 | int err = 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1161 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1162 | if (status == PRE_CHANGE) { |
Asutosh Das | a0cea83 | 2021-09-28 02:06:13 -0700 | [diff] [blame] | 1163 | err = ufshcd_uic_hibern8_enter(hba); |
| 1164 | if (err) |
| 1165 | return err; |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1166 | if (scale_up) |
| 1167 | err = ufs_qcom_clk_scale_up_pre_change(hba); |
| 1168 | else |
| 1169 | err = ufs_qcom_clk_scale_down_pre_change(hba); |
Asutosh Das | a0cea83 | 2021-09-28 02:06:13 -0700 | [diff] [blame] | 1170 | if (err) |
| 1171 | ufshcd_uic_hibern8_exit(hba); |
| 1172 | |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1173 | } else { |
| 1174 | if (scale_up) |
| 1175 | err = ufs_qcom_clk_scale_up_post_change(hba); |
| 1176 | else |
| 1177 | err = ufs_qcom_clk_scale_down_post_change(hba); |
| 1178 | |
Asutosh Das | a0cea83 | 2021-09-28 02:06:13 -0700 | [diff] [blame] | 1179 | |
Dan Carpenter | fa8d327 | 2023-02-27 13:07:26 +0300 | [diff] [blame] | 1180 | if (err) { |
Asutosh Das | a0cea83 | 2021-09-28 02:06:13 -0700 | [diff] [blame] | 1181 | ufshcd_uic_hibern8_exit(hba); |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 1182 | return err; |
Asutosh Das | a0cea83 | 2021-09-28 02:06:13 -0700 | [diff] [blame] | 1183 | } |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1184 | |
| 1185 | ufs_qcom_cfg_timers(hba, |
| 1186 | dev_req_params->gear_rx, |
| 1187 | dev_req_params->pwr_rx, |
| 1188 | dev_req_params->hs_rate, |
| 1189 | false); |
Asutosh Das | a0cea83 | 2021-09-28 02:06:13 -0700 | [diff] [blame] | 1190 | ufshcd_uic_hibern8_exit(hba); |
Yaniv Gardi | f06fcc7 | 2015-10-28 13:15:51 +0200 | [diff] [blame] | 1191 | } |
| 1192 | |
Manivannan Sadhasivam | 031312d | 2022-12-22 19:39:51 +0530 | [diff] [blame] | 1193 | return 0; |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1194 | } |
| 1195 | |
Yaniv Gardi | eba5ed3 | 2016-03-10 17:37:21 +0200 | [diff] [blame] | 1196 | static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host) |
| 1197 | { |
Andrew Halaney | e4ce23f | 2022-12-01 17:08:09 -0600 | [diff] [blame] | 1198 | ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, |
| 1199 | UFS_REG_TEST_BUS_EN, REG_UFS_CFG1); |
| 1200 | ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); |
Yaniv Gardi | eba5ed3 | 2016-03-10 17:37:21 +0200 | [diff] [blame] | 1201 | } |
| 1202 | |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1203 | static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host) |
| 1204 | { |
| 1205 | /* provide a legal default configuration */ |
Venkat Gopalakrishnan | 9c46b86 | 2017-02-03 16:58:12 -0800 | [diff] [blame] | 1206 | host->testbus.select_major = TSTBUS_UNIPRO; |
| 1207 | host->testbus.select_minor = 37; |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1208 | } |
| 1209 | |
| 1210 | static bool ufs_qcom_testbus_cfg_is_ok(struct ufs_qcom_host *host) |
| 1211 | { |
| 1212 | if (host->testbus.select_major >= TSTBUS_MAX) { |
| 1213 | dev_err(host->hba->dev, |
| 1214 | "%s: UFS_CFG1[TEST_BUS_SEL} may not equal 0x%05X\n", |
| 1215 | __func__, host->testbus.select_major); |
| 1216 | return false; |
| 1217 | } |
| 1218 | |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1219 | return true; |
| 1220 | } |
| 1221 | |
| 1222 | int ufs_qcom_testbus_config(struct ufs_qcom_host *host) |
| 1223 | { |
| 1224 | int reg; |
| 1225 | int offset; |
| 1226 | u32 mask = TEST_BUS_SUB_SEL_MASK; |
| 1227 | |
| 1228 | if (!host) |
| 1229 | return -EINVAL; |
| 1230 | |
| 1231 | if (!ufs_qcom_testbus_cfg_is_ok(host)) |
| 1232 | return -EPERM; |
| 1233 | |
| 1234 | switch (host->testbus.select_major) { |
| 1235 | case TSTBUS_UAWM: |
| 1236 | reg = UFS_TEST_BUS_CTRL_0; |
| 1237 | offset = 24; |
| 1238 | break; |
| 1239 | case TSTBUS_UARM: |
| 1240 | reg = UFS_TEST_BUS_CTRL_0; |
| 1241 | offset = 16; |
| 1242 | break; |
| 1243 | case TSTBUS_TXUC: |
| 1244 | reg = UFS_TEST_BUS_CTRL_0; |
| 1245 | offset = 8; |
| 1246 | break; |
| 1247 | case TSTBUS_RXUC: |
| 1248 | reg = UFS_TEST_BUS_CTRL_0; |
| 1249 | offset = 0; |
| 1250 | break; |
| 1251 | case TSTBUS_DFC: |
| 1252 | reg = UFS_TEST_BUS_CTRL_1; |
| 1253 | offset = 24; |
| 1254 | break; |
| 1255 | case TSTBUS_TRLUT: |
| 1256 | reg = UFS_TEST_BUS_CTRL_1; |
| 1257 | offset = 16; |
| 1258 | break; |
| 1259 | case TSTBUS_TMRLUT: |
| 1260 | reg = UFS_TEST_BUS_CTRL_1; |
| 1261 | offset = 8; |
| 1262 | break; |
| 1263 | case TSTBUS_OCSC: |
| 1264 | reg = UFS_TEST_BUS_CTRL_1; |
| 1265 | offset = 0; |
| 1266 | break; |
| 1267 | case TSTBUS_WRAPPER: |
| 1268 | reg = UFS_TEST_BUS_CTRL_2; |
| 1269 | offset = 16; |
| 1270 | break; |
| 1271 | case TSTBUS_COMBINED: |
| 1272 | reg = UFS_TEST_BUS_CTRL_2; |
| 1273 | offset = 8; |
| 1274 | break; |
| 1275 | case TSTBUS_UTP_HCI: |
| 1276 | reg = UFS_TEST_BUS_CTRL_2; |
| 1277 | offset = 0; |
| 1278 | break; |
| 1279 | case TSTBUS_UNIPRO: |
| 1280 | reg = UFS_UNIPRO_CFG; |
Venkat Gopalakrishnan | 9c46b86 | 2017-02-03 16:58:12 -0800 | [diff] [blame] | 1281 | offset = 20; |
| 1282 | mask = 0xFFF; |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1283 | break; |
| 1284 | /* |
| 1285 | * No need for a default case, since |
| 1286 | * ufs_qcom_testbus_cfg_is_ok() checks that the configuration |
| 1287 | * is legal |
| 1288 | */ |
| 1289 | } |
| 1290 | mask <<= offset; |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1291 | ufshcd_rmwl(host->hba, TEST_BUS_SEL, |
| 1292 | (u32)host->testbus.select_major << 19, |
| 1293 | REG_UFS_CFG1); |
| 1294 | ufshcd_rmwl(host->hba, mask, |
| 1295 | (u32)host->testbus.select_minor << offset, |
| 1296 | reg); |
Yaniv Gardi | eba5ed3 | 2016-03-10 17:37:21 +0200 | [diff] [blame] | 1297 | ufs_qcom_enable_test_bus(host); |
Venkat Gopalakrishnan | 9c46b86 | 2017-02-03 16:58:12 -0800 | [diff] [blame] | 1298 | /* |
| 1299 | * Make sure the test bus configuration is |
| 1300 | * committed before returning. |
| 1301 | */ |
| 1302 | mb(); |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1303 | |
| 1304 | return 0; |
| 1305 | } |
| 1306 | |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1307 | static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) |
| 1308 | { |
Andrew Halaney | 50a427a | 2022-12-01 17:08:08 -0600 | [diff] [blame] | 1309 | u32 reg; |
| 1310 | struct ufs_qcom_host *host; |
| 1311 | |
| 1312 | host = ufshcd_get_variant(hba); |
| 1313 | |
Tomas Winkler | ba80917 | 2018-06-14 11:14:09 +0300 | [diff] [blame] | 1314 | ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4, |
| 1315 | "HCI Vendor Specific Registers "); |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1316 | |
Andrew Halaney | 50a427a | 2022-12-01 17:08:08 -0600 | [diff] [blame] | 1317 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC); |
| 1318 | ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC "); |
| 1319 | |
| 1320 | reg = ufshcd_readl(hba, REG_UFS_CFG1); |
| 1321 | reg |= UTP_DBG_RAMS_EN; |
| 1322 | ufshcd_writel(hba, reg, REG_UFS_CFG1); |
| 1323 | |
| 1324 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM); |
| 1325 | ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM "); |
| 1326 | |
| 1327 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM); |
| 1328 | ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM "); |
| 1329 | |
| 1330 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM); |
| 1331 | ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM "); |
| 1332 | |
| 1333 | /* clear bit 17 - UTP_DBG_RAMS_EN */ |
| 1334 | ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); |
| 1335 | |
| 1336 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM); |
| 1337 | ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM "); |
| 1338 | |
| 1339 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM); |
| 1340 | ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM "); |
| 1341 | |
| 1342 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC); |
| 1343 | ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC "); |
| 1344 | |
| 1345 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC); |
| 1346 | ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC "); |
| 1347 | |
| 1348 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC); |
| 1349 | ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC "); |
| 1350 | |
| 1351 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT); |
| 1352 | ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT "); |
| 1353 | |
| 1354 | reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); |
| 1355 | ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1356 | } |
Yaniv Gardi | eba5ed3 | 2016-03-10 17:37:21 +0200 | [diff] [blame] | 1357 | |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1358 | /** |
Bjorn Andersson | b8416b2 | 2019-08-28 12:17:55 -0700 | [diff] [blame] | 1359 | * ufs_qcom_device_reset() - toggle the (optional) device reset line |
| 1360 | * @hba: per-adapter instance |
| 1361 | * |
| 1362 | * Toggles the (optional) reset line to reset the attached device. |
| 1363 | */ |
Adrian Hunter | 151f1b6 | 2020-11-03 16:14:03 +0200 | [diff] [blame] | 1364 | static int ufs_qcom_device_reset(struct ufs_hba *hba) |
Bjorn Andersson | b8416b2 | 2019-08-28 12:17:55 -0700 | [diff] [blame] | 1365 | { |
| 1366 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
| 1367 | |
| 1368 | /* reset gpio is optional */ |
| 1369 | if (!host->device_reset) |
Adrian Hunter | 151f1b6 | 2020-11-03 16:14:03 +0200 | [diff] [blame] | 1370 | return -EOPNOTSUPP; |
Bjorn Andersson | b8416b2 | 2019-08-28 12:17:55 -0700 | [diff] [blame] | 1371 | |
| 1372 | /* |
| 1373 | * The UFS device shall detect reset pulses of 1us, sleep for 10us to |
| 1374 | * be on the safe side. |
| 1375 | */ |
Ziqi Chen | b61d041 | 2021-01-08 18:56:25 +0800 | [diff] [blame] | 1376 | ufs_qcom_device_reset_ctrl(hba, true); |
Bjorn Andersson | b8416b2 | 2019-08-28 12:17:55 -0700 | [diff] [blame] | 1377 | usleep_range(10, 15); |
| 1378 | |
Ziqi Chen | b61d041 | 2021-01-08 18:56:25 +0800 | [diff] [blame] | 1379 | ufs_qcom_device_reset_ctrl(hba, false); |
Bjorn Andersson | b8416b2 | 2019-08-28 12:17:55 -0700 | [diff] [blame] | 1380 | usleep_range(10, 15); |
Adrian Hunter | 151f1b6 | 2020-11-03 16:14:03 +0200 | [diff] [blame] | 1381 | |
| 1382 | return 0; |
Bjorn Andersson | b8416b2 | 2019-08-28 12:17:55 -0700 | [diff] [blame] | 1383 | } |
| 1384 | |
Asutosh Das | 80b2100 | 2020-03-25 11:29:02 -0700 | [diff] [blame] | 1385 | #if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) |
| 1386 | static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, |
Bart Van Assche | c906e83 | 2022-04-19 15:57:57 -0700 | [diff] [blame] | 1387 | struct devfreq_dev_profile *p, |
| 1388 | struct devfreq_simple_ondemand_data *d) |
Asutosh Das | 80b2100 | 2020-03-25 11:29:02 -0700 | [diff] [blame] | 1389 | { |
Asutosh Das | 80b2100 | 2020-03-25 11:29:02 -0700 | [diff] [blame] | 1390 | p->polling_ms = 60; |
| 1391 | d->upthreshold = 70; |
| 1392 | d->downdifferential = 5; |
| 1393 | } |
| 1394 | #else |
| 1395 | static void ufs_qcom_config_scaling_param(struct ufs_hba *hba, |
Bart Van Assche | c906e83 | 2022-04-19 15:57:57 -0700 | [diff] [blame] | 1396 | struct devfreq_dev_profile *p, |
| 1397 | struct devfreq_simple_ondemand_data *data) |
Asutosh Das | 80b2100 | 2020-03-25 11:29:02 -0700 | [diff] [blame] | 1398 | { |
| 1399 | } |
| 1400 | #endif |
| 1401 | |
Manivannan Sadhasivam | baf5dda | 2022-12-22 19:39:59 +0530 | [diff] [blame] | 1402 | static void ufs_qcom_reinit_notify(struct ufs_hba *hba) |
| 1403 | { |
| 1404 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
| 1405 | |
| 1406 | phy_power_off(host->generic_phy); |
| 1407 | } |
| 1408 | |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 1409 | /* Resources */ |
| 1410 | static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { |
| 1411 | {.name = "ufs_mem",}, |
| 1412 | {.name = "mcq",}, |
| 1413 | /* Submission Queue DAO */ |
| 1414 | {.name = "mcq_sqd",}, |
| 1415 | /* Submission Queue Interrupt Status */ |
| 1416 | {.name = "mcq_sqis",}, |
| 1417 | /* Completion Queue DAO */ |
| 1418 | {.name = "mcq_cqd",}, |
| 1419 | /* Completion Queue Interrupt Status */ |
| 1420 | {.name = "mcq_cqis",}, |
| 1421 | /* MCQ vendor specific */ |
| 1422 | {.name = "mcq_vs",}, |
| 1423 | }; |
| 1424 | |
| 1425 | static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) |
| 1426 | { |
| 1427 | struct platform_device *pdev = to_platform_device(hba->dev); |
| 1428 | struct ufshcd_res_info *res; |
| 1429 | struct resource *res_mem, *res_mcq; |
| 1430 | int i, ret = 0; |
| 1431 | |
| 1432 | memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); |
| 1433 | |
| 1434 | for (i = 0; i < RES_MAX; i++) { |
| 1435 | res = &hba->res[i]; |
| 1436 | res->resource = platform_get_resource_byname(pdev, |
| 1437 | IORESOURCE_MEM, |
| 1438 | res->name); |
| 1439 | if (!res->resource) { |
| 1440 | dev_info(hba->dev, "Resource %s not provided\n", res->name); |
| 1441 | if (i == RES_UFS) |
| 1442 | return -ENOMEM; |
| 1443 | continue; |
| 1444 | } else if (i == RES_UFS) { |
| 1445 | res_mem = res->resource; |
| 1446 | res->base = hba->mmio_base; |
| 1447 | continue; |
| 1448 | } |
| 1449 | |
| 1450 | res->base = devm_ioremap_resource(hba->dev, res->resource); |
| 1451 | if (IS_ERR(res->base)) { |
| 1452 | dev_err(hba->dev, "Failed to map res %s, err=%d\n", |
| 1453 | res->name, (int)PTR_ERR(res->base)); |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 1454 | ret = PTR_ERR(res->base); |
Asutosh Das | c8be073 | 2023-03-01 17:41:06 -0800 | [diff] [blame] | 1455 | res->base = NULL; |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 1456 | return ret; |
| 1457 | } |
| 1458 | } |
| 1459 | |
| 1460 | /* MCQ resource provided in DT */ |
| 1461 | res = &hba->res[RES_MCQ]; |
| 1462 | /* Bail if MCQ resource is provided */ |
| 1463 | if (res->base) |
| 1464 | goto out; |
| 1465 | |
| 1466 | /* Explicitly allocate MCQ resource from ufs_mem */ |
| 1467 | res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); |
| 1468 | if (!res_mcq) |
Asutosh Das | c9507ea | 2023-03-01 17:42:56 -0800 | [diff] [blame] | 1469 | return -ENOMEM; |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 1470 | |
| 1471 | res_mcq->start = res_mem->start + |
| 1472 | MCQ_SQATTR_OFFSET(hba->mcq_capabilities); |
| 1473 | res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; |
| 1474 | res_mcq->flags = res_mem->flags; |
| 1475 | res_mcq->name = "mcq"; |
| 1476 | |
| 1477 | ret = insert_resource(&iomem_resource, res_mcq); |
| 1478 | if (ret) { |
| 1479 | dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", |
| 1480 | ret); |
Asutosh Das | c9507ea | 2023-03-01 17:42:56 -0800 | [diff] [blame] | 1481 | return ret; |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 1482 | } |
| 1483 | |
| 1484 | res->base = devm_ioremap_resource(hba->dev, res_mcq); |
| 1485 | if (IS_ERR(res->base)) { |
| 1486 | dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", |
| 1487 | (int)PTR_ERR(res->base)); |
| 1488 | ret = PTR_ERR(res->base); |
| 1489 | goto ioremap_err; |
| 1490 | } |
| 1491 | |
| 1492 | out: |
| 1493 | hba->mcq_base = res->base; |
| 1494 | return 0; |
| 1495 | ioremap_err: |
| 1496 | res->base = NULL; |
| 1497 | remove_resource(res_mcq); |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 1498 | return ret; |
| 1499 | } |
| 1500 | |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1501 | static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) |
| 1502 | { |
| 1503 | struct ufshcd_res_info *mem_res, *sqdao_res; |
| 1504 | struct ufshcd_mcq_opr_info_t *opr; |
| 1505 | int i; |
| 1506 | |
| 1507 | mem_res = &hba->res[RES_UFS]; |
| 1508 | sqdao_res = &hba->res[RES_MCQ_SQD]; |
| 1509 | |
| 1510 | if (!mem_res->base || !sqdao_res->base) |
| 1511 | return -EINVAL; |
| 1512 | |
| 1513 | for (i = 0; i < OPR_MAX; i++) { |
| 1514 | opr = &hba->mcq_opr[i]; |
| 1515 | opr->offset = sqdao_res->resource->start - |
| 1516 | mem_res->resource->start + 0x40 * i; |
| 1517 | opr->stride = 0x100; |
| 1518 | opr->base = sqdao_res->base + 0x40 * i; |
| 1519 | } |
| 1520 | |
| 1521 | return 0; |
| 1522 | } |
| 1523 | |
Asutosh Das | 7224c80 | 2023-01-13 12:48:43 -0800 | [diff] [blame] | 1524 | static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) |
| 1525 | { |
| 1526 | /* Qualcomm HC supports up to 64 */ |
| 1527 | return MAX_SUPP_MAC; |
| 1528 | } |
| 1529 | |
Asutosh Das | f87b2c4 | 2023-01-13 12:48:50 -0800 | [diff] [blame] | 1530 | static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, |
| 1531 | unsigned long *ocqs) |
| 1532 | { |
| 1533 | struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; |
| 1534 | |
| 1535 | if (!mcq_vs_res->base) |
| 1536 | return -EINVAL; |
| 1537 | |
| 1538 | *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); |
| 1539 | |
| 1540 | return 0; |
| 1541 | } |
| 1542 | |
Can Guo | 519b627 | 2022-12-14 19:06:22 -0800 | [diff] [blame] | 1543 | static void ufs_qcom_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) |
| 1544 | { |
| 1545 | struct device *dev = msi_desc_to_dev(desc); |
| 1546 | struct ufs_hba *hba = dev_get_drvdata(dev); |
| 1547 | |
| 1548 | ufshcd_mcq_config_esi(hba, msg); |
| 1549 | } |
| 1550 | |
| 1551 | static irqreturn_t ufs_qcom_mcq_esi_handler(int irq, void *__hba) |
| 1552 | { |
| 1553 | struct ufs_hba *hba = __hba; |
| 1554 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
| 1555 | u32 id = irq - host->esi_base; |
| 1556 | struct ufs_hw_queue *hwq = &hba->uhq[id]; |
| 1557 | |
| 1558 | ufshcd_mcq_write_cqis(hba, 0x1, id); |
| 1559 | ufshcd_mcq_poll_cqe_nolock(hba, hwq); |
| 1560 | |
| 1561 | return IRQ_HANDLED; |
| 1562 | } |
| 1563 | |
| 1564 | static int ufs_qcom_config_esi(struct ufs_hba *hba) |
| 1565 | { |
| 1566 | struct ufs_qcom_host *host = ufshcd_get_variant(hba); |
| 1567 | struct msi_desc *desc; |
| 1568 | struct msi_desc *failed_desc = NULL; |
| 1569 | int nr_irqs, ret; |
| 1570 | |
| 1571 | if (host->esi_enabled) |
| 1572 | return 0; |
| 1573 | else if (host->esi_base < 0) |
| 1574 | return -EINVAL; |
| 1575 | |
| 1576 | /* |
| 1577 | * 1. We only handle CQs as of now. |
| 1578 | * 2. Poll queues do not need ESI. |
| 1579 | */ |
| 1580 | nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; |
| 1581 | ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, |
| 1582 | ufs_qcom_write_msi_msg); |
| 1583 | if (ret) |
| 1584 | goto out; |
| 1585 | |
| 1586 | msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { |
| 1587 | if (!desc->msi_index) |
| 1588 | host->esi_base = desc->irq; |
| 1589 | |
| 1590 | ret = devm_request_irq(hba->dev, desc->irq, |
| 1591 | ufs_qcom_mcq_esi_handler, |
| 1592 | IRQF_SHARED, "qcom-mcq-esi", hba); |
| 1593 | if (ret) { |
| 1594 | dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", |
| 1595 | __func__, desc->irq, ret); |
| 1596 | failed_desc = desc; |
| 1597 | break; |
| 1598 | } |
| 1599 | } |
| 1600 | |
| 1601 | if (ret) { |
| 1602 | /* Rewind */ |
| 1603 | msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { |
| 1604 | if (desc == failed_desc) |
| 1605 | break; |
| 1606 | devm_free_irq(hba->dev, desc->irq, hba); |
| 1607 | } |
| 1608 | platform_msi_domain_free_irqs(hba->dev); |
| 1609 | } else { |
| 1610 | if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && |
| 1611 | host->hw_ver.step == 0) { |
| 1612 | ufshcd_writel(hba, |
| 1613 | ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000, |
| 1614 | REG_UFS_CFG3); |
| 1615 | } |
| 1616 | ufshcd_mcq_enable_esi(hba); |
| 1617 | } |
| 1618 | |
| 1619 | out: |
| 1620 | if (ret) { |
| 1621 | host->esi_base = -1; |
| 1622 | dev_warn(hba->dev, "Failed to request Platform MSI %d\n", ret); |
| 1623 | } else { |
| 1624 | host->esi_enabled = true; |
| 1625 | } |
| 1626 | |
| 1627 | return ret; |
| 1628 | } |
| 1629 | |
Lee Jones | bc5b681 | 2020-07-23 13:24:09 +0100 | [diff] [blame] | 1630 | /* |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1631 | * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations |
| 1632 | * |
| 1633 | * The variant operations configure the necessary controller and PHY |
| 1634 | * handshake during initialization. |
| 1635 | */ |
Nishka Dasgupta | d508e31 | 2019-08-19 13:25:57 +0530 | [diff] [blame] | 1636 | static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = { |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1637 | .name = "qcom", |
| 1638 | .init = ufs_qcom_init, |
| 1639 | .exit = ufs_qcom_exit, |
Yaniv Gardi | ae97758 | 2015-05-17 18:55:06 +0300 | [diff] [blame] | 1640 | .get_ufs_hci_version = ufs_qcom_get_ufs_hci_version, |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1641 | .clk_scale_notify = ufs_qcom_clk_scale_notify, |
| 1642 | .setup_clocks = ufs_qcom_setup_clocks, |
| 1643 | .hce_enable_notify = ufs_qcom_hce_enable_notify, |
| 1644 | .link_startup_notify = ufs_qcom_link_startup_notify, |
| 1645 | .pwr_change_notify = ufs_qcom_pwr_change_notify, |
Subhash Jadavani | 56d4a18 | 2016-12-05 19:25:32 -0800 | [diff] [blame] | 1646 | .apply_dev_quirks = ufs_qcom_apply_dev_quirks, |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1647 | .suspend = ufs_qcom_suspend, |
| 1648 | .resume = ufs_qcom_resume, |
Yaniv Gardi | 6e3fd44 | 2015-10-28 13:15:50 +0200 | [diff] [blame] | 1649 | .dbg_register_dump = ufs_qcom_dump_dbg_regs, |
Bjorn Andersson | b8416b2 | 2019-08-28 12:17:55 -0700 | [diff] [blame] | 1650 | .device_reset = ufs_qcom_device_reset, |
Asutosh Das | 80b2100 | 2020-03-25 11:29:02 -0700 | [diff] [blame] | 1651 | .config_scaling_param = ufs_qcom_config_scaling_param, |
Eric Biggers | df4ec2f | 2020-07-10 00:20:12 -0700 | [diff] [blame] | 1652 | .program_key = ufs_qcom_ice_program_key, |
Manivannan Sadhasivam | baf5dda | 2022-12-22 19:39:59 +0530 | [diff] [blame] | 1653 | .reinit_notify = ufs_qcom_reinit_notify, |
Asutosh Das | c263b4e | 2023-01-13 12:48:42 -0800 | [diff] [blame] | 1654 | .mcq_config_resource = ufs_qcom_mcq_config_resource, |
Asutosh Das | 7224c80 | 2023-01-13 12:48:43 -0800 | [diff] [blame] | 1655 | .get_hba_mac = ufs_qcom_get_hba_mac, |
Asutosh Das | 2468da6 | 2023-01-13 12:48:45 -0800 | [diff] [blame] | 1656 | .op_runtime_config = ufs_qcom_op_runtime_config, |
Asutosh Das | f87b2c4 | 2023-01-13 12:48:50 -0800 | [diff] [blame] | 1657 | .get_outstanding_cqs = ufs_qcom_get_outstanding_cqs, |
Can Guo | 519b627 | 2022-12-14 19:06:22 -0800 | [diff] [blame] | 1658 | .config_esi = ufs_qcom_config_esi, |
Yaniv Gardi | 81c0fc5 | 2015-01-15 16:32:37 +0200 | [diff] [blame] | 1659 | }; |
Yaniv Gardi | fb819ee | 2015-10-28 13:15:45 +0200 | [diff] [blame] | 1660 | |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1661 | /** |
| 1662 | * ufs_qcom_probe - probe routine of the driver |
| 1663 | * @pdev: pointer to Platform device handle |
| 1664 | * |
| 1665 | * Return zero for success and non-zero for failure |
| 1666 | */ |
| 1667 | static int ufs_qcom_probe(struct platform_device *pdev) |
| 1668 | { |
| 1669 | int err; |
| 1670 | struct device *dev = &pdev->dev; |
| 1671 | |
| 1672 | /* Perform generic probe */ |
| 1673 | err = ufshcd_pltfrm_init(pdev, &ufs_hba_qcom_vops); |
| 1674 | if (err) |
Manivannan Sadhasivam | 132b027 | 2022-12-22 19:39:54 +0530 | [diff] [blame] | 1675 | return dev_err_probe(dev, err, "ufshcd_pltfrm_init() failed\n"); |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1676 | |
Manivannan Sadhasivam | 132b027 | 2022-12-22 19:39:54 +0530 | [diff] [blame] | 1677 | return 0; |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1678 | } |
| 1679 | |
| 1680 | /** |
| 1681 | * ufs_qcom_remove - set driver_data of the device to NULL |
| 1682 | * @pdev: pointer to platform device handle |
| 1683 | * |
Yaniv Gardi | 4b9ad0b | 2016-03-10 17:37:19 +0200 | [diff] [blame] | 1684 | * Always returns 0 |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1685 | */ |
| 1686 | static int ufs_qcom_remove(struct platform_device *pdev) |
| 1687 | { |
| 1688 | struct ufs_hba *hba = platform_get_drvdata(pdev); |
| 1689 | |
| 1690 | pm_runtime_get_sync(&(pdev)->dev); |
| 1691 | ufshcd_remove(hba); |
Can Guo | 519b627 | 2022-12-14 19:06:22 -0800 | [diff] [blame] | 1692 | platform_msi_domain_free_irqs(hba->dev); |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1693 | return 0; |
| 1694 | } |
| 1695 | |
| 1696 | static const struct of_device_id ufs_qcom_of_match[] = { |
| 1697 | { .compatible = "qcom,ufshc"}, |
| 1698 | {}, |
| 1699 | }; |
Javier Martinez Canillas | ab3dabb | 2017-01-02 11:04:58 -0300 | [diff] [blame] | 1700 | MODULE_DEVICE_TABLE(of, ufs_qcom_of_match); |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1701 | |
Lee Jones | e1a7752 | 2019-06-17 12:54:54 +0100 | [diff] [blame] | 1702 | #ifdef CONFIG_ACPI |
| 1703 | static const struct acpi_device_id ufs_qcom_acpi_match[] = { |
| 1704 | { "QCOM24A5" }, |
| 1705 | { }, |
| 1706 | }; |
| 1707 | MODULE_DEVICE_TABLE(acpi, ufs_qcom_acpi_match); |
| 1708 | #endif |
| 1709 | |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1710 | static const struct dev_pm_ops ufs_qcom_pm_ops = { |
Bart Van Assche | f1ecbe1 | 2021-07-21 20:34:23 -0700 | [diff] [blame] | 1711 | SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) |
Asutosh Das | b294ff3 | 2021-04-23 17:20:16 -0700 | [diff] [blame] | 1712 | .prepare = ufshcd_suspend_prepare, |
| 1713 | .complete = ufshcd_resume_complete, |
Anjana Hari | 88441a8 | 2023-02-02 21:40:45 +0530 | [diff] [blame] | 1714 | #ifdef CONFIG_PM_SLEEP |
| 1715 | .suspend = ufshcd_system_suspend, |
| 1716 | .resume = ufshcd_system_resume, |
| 1717 | .freeze = ufshcd_system_freeze, |
| 1718 | .restore = ufshcd_system_restore, |
| 1719 | .thaw = ufshcd_system_thaw, |
| 1720 | #endif |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1721 | }; |
| 1722 | |
| 1723 | static struct platform_driver ufs_qcom_pltform = { |
| 1724 | .probe = ufs_qcom_probe, |
| 1725 | .remove = ufs_qcom_remove, |
| 1726 | .shutdown = ufshcd_pltfrm_shutdown, |
| 1727 | .driver = { |
| 1728 | .name = "ufshcd-qcom", |
| 1729 | .pm = &ufs_qcom_pm_ops, |
| 1730 | .of_match_table = of_match_ptr(ufs_qcom_of_match), |
Lee Jones | e1a7752 | 2019-06-17 12:54:54 +0100 | [diff] [blame] | 1731 | .acpi_match_table = ACPI_PTR(ufs_qcom_acpi_match), |
Yaniv Gardi | 47555a5 | 2015-10-28 13:15:49 +0200 | [diff] [blame] | 1732 | }, |
| 1733 | }; |
| 1734 | module_platform_driver(ufs_qcom_pltform); |
| 1735 | |
Yaniv Gardi | fb819ee | 2015-10-28 13:15:45 +0200 | [diff] [blame] | 1736 | MODULE_LICENSE("GPL v2"); |