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Kukjin Kimdbb8fd32013-01-21 15:24:34 -08001/*
Ben Dooks22d42392009-07-30 23:23:33 +01002 * Copyright 2008 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 CPU Frequency scalling
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/cpufreq.h>
Kay Sievers4a858cf2011-12-21 16:01:38 -080018#include <linux/device.h>
Ben Dooks22d42392009-07-30 23:23:33 +010019#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/io.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26
27#include <mach/regs-clock.h>
Viresh Kumarf023f8d2013-04-04 12:54:15 +000028#include <mach/s3c2412.h>
Ben Dooks22d42392009-07-30 23:23:33 +010029
30#include <plat/cpu.h>
Ben Dooks22d42392009-07-30 23:23:33 +010031#include <plat/cpu-freq-core.h>
32
33/* our clock resources. */
34static struct clk *xtal;
35static struct clk *fclk;
36static struct clk *hclk;
37static struct clk *armclk;
38
39/* HDIV: 1, 2, 3, 4, 6, 8 */
40
41static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
42{
43 unsigned int hdiv, pdiv, armdiv, dvs;
44 unsigned long hclk, fclk, armclk, armdiv_clk;
45 unsigned long hclk_max;
46
47 fclk = cfg->freq.fclk;
48 armclk = cfg->freq.armclk;
49 hclk_max = cfg->max.hclk;
50
51 /* We can't run hclk above armclk as at the best we have to
52 * have armclk and hclk in dvs mode. */
53
54 if (hclk_max > armclk)
55 hclk_max = armclk;
56
57 s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
58 __func__, fclk, armclk, hclk_max);
59 s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
60 __func__, cfg->freq.fclk, cfg->freq.armclk,
61 cfg->freq.hclk, cfg->freq.pclk);
62
63 armdiv = fclk / armclk;
64
65 if (armdiv < 1)
66 armdiv = 1;
67 if (armdiv > 2)
68 armdiv = 2;
69
70 cfg->divs.arm_divisor = armdiv;
71 armdiv_clk = fclk / armdiv;
72
73 hdiv = armdiv_clk / hclk_max;
74 if (hdiv < 1)
75 hdiv = 1;
76
77 cfg->freq.hclk = hclk = armdiv_clk / hdiv;
78
79 /* set dvs depending on whether we reached armclk or not. */
80 cfg->divs.dvs = dvs = armclk < armdiv_clk;
81
82 /* update the actual armclk we achieved. */
83 cfg->freq.armclk = dvs ? hclk : armdiv_clk;
84
85 s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
86 __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
87
88 if (hdiv > 4)
89 goto invalid;
90
91 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
92
93 if ((hclk / pdiv) > cfg->max.pclk)
94 pdiv++;
95
96 cfg->freq.pclk = hclk / pdiv;
97
98 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
99
100 if (pdiv > 2)
101 goto invalid;
102
103 pdiv *= hdiv;
104
105 /* store the result, and then return */
106
107 cfg->divs.h_divisor = hdiv * armdiv;
108 cfg->divs.p_divisor = pdiv * armdiv;
109
110 return 0;
111
Kukjin Kimdbb8fd32013-01-21 15:24:34 -0800112invalid:
Ben Dooks22d42392009-07-30 23:23:33 +0100113 return -EINVAL;
114}
115
116static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
117{
118 unsigned long clkdiv;
119 unsigned long olddiv;
120
121 olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
122
123 /* clear off current clock info */
124
125 clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
126 clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
127 clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
128
129 if (cfg->divs.arm_divisor == 2)
130 clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
131
132 clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
133
134 if (cfg->divs.p_divisor != cfg->divs.h_divisor)
135 clkdiv |= S3C2412_CLKDIVN_PDIVN;
136
137 s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
138 __raw_writel(clkdiv, S3C2410_CLKDIVN);
139
140 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
141}
142
143static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
144{
145 struct s3c_cpufreq_board *board = cfg->board;
146 unsigned long refresh;
147
148 s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
149 board->refresh, cfg->freq.hclk);
150
151 /* Reduce both the refresh time (in ns) and the frequency (in MHz)
152 * by 10 each to ensure that we do not overflow 32 bit numbers. This
153 * should work for HCLK up to 133MHz and refresh period up to 30usec.
154 */
155
156 refresh = (board->refresh / 10);
157 refresh *= (cfg->freq.hclk / 100);
158 refresh /= (1 * 1000 * 1000); /* 10^6 */
159
160 s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
161 __raw_writel(refresh, S3C2412_REFRESH);
162}
163
164/* set the default cpu frequency information, based on an 200MHz part
165 * as we have no other way of detecting the speed rating in software.
166 */
167
168static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
169 .max = {
170 .fclk = 200000000,
171 .hclk = 100000000,
172 .pclk = 50000000,
173 },
174
175 .latency = 5000000, /* 5ms */
176
177 .locktime_m = 150,
178 .locktime_u = 150,
179 .locktime_bits = 16,
180
181 .name = "s3c2412",
182 .set_refresh = s3c2412_cpufreq_setrefresh,
183 .set_divs = s3c2412_cpufreq_setdivs,
184 .calc_divs = s3c2412_cpufreq_calcdivs,
185
Ben Dooks140780ab2009-07-30 23:23:37 +0100186 .calc_iotiming = s3c2412_iotiming_calc,
187 .set_iotiming = s3c2412_iotiming_set,
188 .get_iotiming = s3c2412_iotiming_get,
189
Ben Dookse6d197a2009-07-30 23:23:42 +0100190 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
Ben Dooks22d42392009-07-30 23:23:33 +0100191};
192
Heiko Stuebner04511a62012-01-27 15:35:25 +0900193static int s3c2412_cpufreq_add(struct device *dev,
194 struct subsys_interface *sif)
Ben Dooks22d42392009-07-30 23:23:33 +0100195{
196 unsigned long fclk_rate;
197
198 hclk = clk_get(NULL, "hclk");
199 if (IS_ERR(hclk)) {
200 printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
201 return -ENOENT;
202 }
203
204 fclk = clk_get(NULL, "fclk");
205 if (IS_ERR(fclk)) {
206 printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
207 goto err_fclk;
208 }
209
210 fclk_rate = clk_get_rate(fclk);
211 if (fclk_rate > 200000000) {
212 printk(KERN_INFO
213 "%s: fclk %ld MHz, assuming 266MHz capable part\n",
214 __func__, fclk_rate / 1000000);
215 s3c2412_cpufreq_info.max.fclk = 266000000;
216 s3c2412_cpufreq_info.max.hclk = 133000000;
217 s3c2412_cpufreq_info.max.pclk = 66000000;
218 }
219
220 armclk = clk_get(NULL, "armclk");
221 if (IS_ERR(armclk)) {
222 printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
223 goto err_armclk;
224 }
225
226 xtal = clk_get(NULL, "xtal");
227 if (IS_ERR(xtal)) {
228 printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
229 goto err_xtal;
230 }
231
232 return s3c_cpufreq_register(&s3c2412_cpufreq_info);
233
234err_xtal:
235 clk_put(armclk);
236err_armclk:
237 clk_put(fclk);
238err_fclk:
239 clk_put(hclk);
240
241 return -ENOENT;
242}
243
Kay Sievers4a858cf2011-12-21 16:01:38 -0800244static struct subsys_interface s3c2412_cpufreq_interface = {
245 .name = "s3c2412_cpufreq",
246 .subsys = &s3c2412_subsys,
247 .add_dev = s3c2412_cpufreq_add,
Ben Dooks22d42392009-07-30 23:23:33 +0100248};
249
250static int s3c2412_cpufreq_init(void)
251{
Kay Sievers4a858cf2011-12-21 16:01:38 -0800252 return subsys_interface_register(&s3c2412_cpufreq_interface);
Ben Dooks22d42392009-07-30 23:23:33 +0100253}
Ben Dooks22d42392009-07-30 23:23:33 +0100254arch_initcall(s3c2412_cpufreq_init);