Fabio Estevam | 6576bf0 | 2018-07-24 10:04:02 -0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | // |
| 3 | // Copyright 2013 Freescale Semiconductor, Inc. |
| 4 | // |
| 5 | // Freescale DSPI driver |
| 6 | // This file contains a driver for the Freescale DSPI |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 7 | |
Xiubo Li | a310836 | 2014-09-29 10:57:06 +0800 | [diff] [blame] | 8 | #include <linux/clk.h> |
| 9 | #include <linux/delay.h> |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 10 | #include <linux/dmaengine.h> |
| 11 | #include <linux/dma-mapping.h> |
Xiubo Li | a310836 | 2014-09-29 10:57:06 +0800 | [diff] [blame] | 12 | #include <linux/err.h> |
| 13 | #include <linux/errno.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/io.h> |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 16 | #include <linux/kernel.h> |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 17 | #include <linux/math64.h> |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 18 | #include <linux/module.h> |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 19 | #include <linux/of.h> |
| 20 | #include <linux/of_device.h> |
Mirza Krak | 432a17d | 2015-06-12 18:55:22 +0200 | [diff] [blame] | 21 | #include <linux/pinctrl/consumer.h> |
Xiubo Li | a310836 | 2014-09-29 10:57:06 +0800 | [diff] [blame] | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/pm_runtime.h> |
| 24 | #include <linux/regmap.h> |
| 25 | #include <linux/sched.h> |
| 26 | #include <linux/spi/spi.h> |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 27 | #include <linux/spi/spi-fsl-dspi.h> |
Xiubo Li | a310836 | 2014-09-29 10:57:06 +0800 | [diff] [blame] | 28 | #include <linux/spi/spi_bitbang.h> |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 29 | #include <linux/time.h> |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 30 | |
| 31 | #define DRIVER_NAME "fsl-dspi" |
| 32 | |
Angelo Dureghello | 5223c9c1 | 2018-08-18 01:51:58 +0200 | [diff] [blame] | 33 | #ifdef CONFIG_M5441x |
| 34 | #define DSPI_FIFO_SIZE 16 |
| 35 | #else |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 36 | #define DSPI_FIFO_SIZE 4 |
Angelo Dureghello | 5223c9c1 | 2018-08-18 01:51:58 +0200 | [diff] [blame] | 37 | #endif |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 38 | #define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 39 | |
| 40 | #define SPI_MCR 0x00 |
| 41 | #define SPI_MCR_MASTER (1 << 31) |
| 42 | #define SPI_MCR_PCSIS (0x3F << 16) |
| 43 | #define SPI_MCR_CLR_TXF (1 << 11) |
| 44 | #define SPI_MCR_CLR_RXF (1 << 10) |
Esben Haabendal | 3e7cc62 | 2018-06-20 09:34:42 +0200 | [diff] [blame] | 45 | #define SPI_MCR_XSPI (1 << 3) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 46 | |
| 47 | #define SPI_TCR 0x08 |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 48 | #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 49 | |
Alexander Stein | 5cc7b04 | 2014-11-04 09:20:18 +0100 | [diff] [blame] | 50 | #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4)) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 51 | #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
| 52 | #define SPI_CTAR_CPOL(x) ((x) << 26) |
| 53 | #define SPI_CTAR_CPHA(x) ((x) << 25) |
| 54 | #define SPI_CTAR_LSBFE(x) ((x) << 24) |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 55 | #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 56 | #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) |
| 57 | #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) |
| 58 | #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) |
| 59 | #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) |
| 60 | #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) |
| 61 | #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) |
| 62 | #define SPI_CTAR_BR(x) ((x) & 0x0000000f) |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 63 | #define SPI_CTAR_SCALE_BITS 0xf |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 64 | |
| 65 | #define SPI_CTAR0_SLAVE 0x0c |
| 66 | |
| 67 | #define SPI_SR 0x2c |
| 68 | #define SPI_SR_EOQF 0x10000000 |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 69 | #define SPI_SR_TCFQF 0x80000000 |
Angelo Dureghello | aa54c1c | 2018-12-26 22:45:06 +0100 | [diff] [blame] | 70 | #define SPI_SR_CLEAR 0x9aaf0000 |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 71 | |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 72 | #define SPI_RSER_TFFFE BIT(25) |
| 73 | #define SPI_RSER_TFFFD BIT(24) |
| 74 | #define SPI_RSER_RFDFE BIT(17) |
| 75 | #define SPI_RSER_RFDFD BIT(16) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 76 | |
| 77 | #define SPI_RSER 0x30 |
| 78 | #define SPI_RSER_EOQFE 0x10000000 |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 79 | #define SPI_RSER_TCFQE 0x80000000 |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 80 | |
| 81 | #define SPI_PUSHR 0x34 |
Esben Haabendal | 9e1dc9b | 2018-06-20 09:34:33 +0200 | [diff] [blame] | 82 | #define SPI_PUSHR_CMD_CONT (1 << 15) |
| 83 | #define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16) |
| 84 | #define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12) |
| 85 | #define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16) |
| 86 | #define SPI_PUSHR_CMD_EOQ (1 << 11) |
| 87 | #define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16) |
| 88 | #define SPI_PUSHR_CMD_CTCNT (1 << 10) |
| 89 | #define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16) |
| 90 | #define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f) |
| 91 | #define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 92 | #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) |
| 93 | |
| 94 | #define SPI_PUSHR_SLAVE 0x34 |
| 95 | |
| 96 | #define SPI_POPR 0x38 |
| 97 | #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) |
| 98 | |
| 99 | #define SPI_TXFR0 0x3c |
| 100 | #define SPI_TXFR1 0x40 |
| 101 | #define SPI_TXFR2 0x44 |
| 102 | #define SPI_TXFR3 0x48 |
| 103 | #define SPI_RXFR0 0x7c |
| 104 | #define SPI_RXFR1 0x80 |
| 105 | #define SPI_RXFR2 0x84 |
| 106 | #define SPI_RXFR3 0x88 |
| 107 | |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 108 | #define SPI_CTARE(x) (0x11c + (((x) & 0x3) * 4)) |
| 109 | #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16) |
| 110 | #define SPI_CTARE_DTCP(x) ((x) & 0x7ff) |
| 111 | |
| 112 | #define SPI_SREX 0x13c |
| 113 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 114 | #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) |
| 115 | #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) |
| 116 | #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) |
| 117 | #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) |
| 118 | |
Esben Haabendal | 51d583a | 2018-06-20 09:34:39 +0200 | [diff] [blame] | 119 | #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) |
| 120 | #define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1) |
| 121 | |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 122 | /* Register offsets for regmap_pushr */ |
| 123 | #define PUSHR_CMD 0x0 |
| 124 | #define PUSHR_TX 0x2 |
| 125 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 126 | #define SPI_CS_INIT 0x01 |
| 127 | #define SPI_CS_ASSERT 0x02 |
| 128 | #define SPI_CS_DROP 0x04 |
| 129 | |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 130 | #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) |
| 131 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 132 | struct chip_data { |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 133 | u32 ctar_val; |
| 134 | u16 void_write_data; |
| 135 | }; |
| 136 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 137 | enum dspi_trans_mode { |
| 138 | DSPI_EOQ_MODE = 0, |
| 139 | DSPI_TCFQ_MODE, |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 140 | DSPI_DMA_MODE, |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 141 | }; |
| 142 | |
| 143 | struct fsl_dspi_devtype_data { |
| 144 | enum dspi_trans_mode trans_mode; |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 145 | u8 max_clock_factor; |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 146 | bool xspi_mode; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 147 | }; |
| 148 | |
| 149 | static const struct fsl_dspi_devtype_data vf610_data = { |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 150 | .trans_mode = DSPI_DMA_MODE, |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 151 | .max_clock_factor = 2, |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 152 | }; |
| 153 | |
| 154 | static const struct fsl_dspi_devtype_data ls1021a_v1_data = { |
| 155 | .trans_mode = DSPI_TCFQ_MODE, |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 156 | .max_clock_factor = 8, |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 157 | .xspi_mode = true, |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 158 | }; |
| 159 | |
| 160 | static const struct fsl_dspi_devtype_data ls2085a_data = { |
| 161 | .trans_mode = DSPI_TCFQ_MODE, |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 162 | .max_clock_factor = 8, |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 163 | }; |
| 164 | |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 165 | static const struct fsl_dspi_devtype_data coldfire_data = { |
| 166 | .trans_mode = DSPI_EOQ_MODE, |
| 167 | .max_clock_factor = 8, |
| 168 | }; |
| 169 | |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 170 | struct fsl_dspi_dma { |
Sanchayan Maity | 1eaccf2 | 2016-11-22 12:31:30 +0530 | [diff] [blame] | 171 | /* Length of transfer in words of DSPI_FIFO_SIZE */ |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 172 | u32 curr_xfer_len; |
| 173 | |
| 174 | u32 *tx_dma_buf; |
| 175 | struct dma_chan *chan_tx; |
| 176 | dma_addr_t tx_dma_phys; |
| 177 | struct completion cmd_tx_complete; |
| 178 | struct dma_async_tx_descriptor *tx_desc; |
| 179 | |
| 180 | u32 *rx_dma_buf; |
| 181 | struct dma_chan *chan_rx; |
| 182 | dma_addr_t rx_dma_phys; |
| 183 | struct completion cmd_rx_complete; |
| 184 | struct dma_async_tx_descriptor *rx_desc; |
| 185 | }; |
| 186 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 187 | struct fsl_dspi { |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 188 | struct spi_master *master; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 189 | struct platform_device *pdev; |
| 190 | |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 191 | struct regmap *regmap; |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 192 | struct regmap *regmap_pushr; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 193 | int irq; |
Chao Fu | 88386e8 | 2014-02-12 15:29:06 +0800 | [diff] [blame] | 194 | struct clk *clk; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 195 | |
Chao Fu | 88386e8 | 2014-02-12 15:29:06 +0800 | [diff] [blame] | 196 | struct spi_transfer *cur_transfer; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 197 | struct spi_message *cur_msg; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 198 | struct chip_data *cur_chip; |
| 199 | size_t len; |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 200 | const void *tx; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 201 | void *rx; |
| 202 | void *rx_end; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 203 | u16 void_write_data; |
Esben Haabendal | 9e1dc9b | 2018-06-20 09:34:33 +0200 | [diff] [blame] | 204 | u16 tx_cmd; |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 205 | u8 bits_per_word; |
| 206 | u8 bytes_per_word; |
LABBE Corentin | 94b968b | 2016-08-16 11:50:20 +0200 | [diff] [blame] | 207 | const struct fsl_dspi_devtype_data *devtype_data; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 208 | |
Chao Fu | 88386e8 | 2014-02-12 15:29:06 +0800 | [diff] [blame] | 209 | wait_queue_head_t waitq; |
| 210 | u32 waitflags; |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 211 | |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 212 | struct fsl_dspi_dma *dma; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 213 | }; |
| 214 | |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 215 | static u32 dspi_pop_tx(struct fsl_dspi *dspi) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 216 | { |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 217 | u32 txdata = 0; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 218 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 219 | if (dspi->tx) { |
| 220 | if (dspi->bytes_per_word == 1) |
| 221 | txdata = *(u8 *)dspi->tx; |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 222 | else if (dspi->bytes_per_word == 2) |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 223 | txdata = *(u16 *)dspi->tx; |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 224 | else /* dspi->bytes_per_word == 4 */ |
| 225 | txdata = *(u32 *)dspi->tx; |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 226 | dspi->tx += dspi->bytes_per_word; |
| 227 | } |
| 228 | dspi->len -= dspi->bytes_per_word; |
| 229 | return txdata; |
| 230 | } |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 231 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 232 | static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) |
| 233 | { |
| 234 | u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi); |
| 235 | |
Lukasz Majewski | 5ce3cc5 | 2019-02-05 23:13:49 +0100 | [diff] [blame] | 236 | if (spi_controller_is_slave(dspi->master)) |
| 237 | return data; |
| 238 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 239 | if (dspi->len > 0) |
| 240 | cmd |= SPI_PUSHR_CMD_CONT; |
| 241 | return cmd << 16 | data; |
| 242 | } |
| 243 | |
| 244 | static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) |
| 245 | { |
| 246 | if (!dspi->rx) |
| 247 | return; |
| 248 | |
| 249 | /* Mask of undefined bits */ |
| 250 | rxdata &= (1 << dspi->bits_per_word) - 1; |
| 251 | |
| 252 | if (dspi->bytes_per_word == 1) |
| 253 | *(u8 *)dspi->rx = rxdata; |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 254 | else if (dspi->bytes_per_word == 2) |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 255 | *(u16 *)dspi->rx = rxdata; |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 256 | else /* dspi->bytes_per_word == 4 */ |
| 257 | *(u32 *)dspi->rx = rxdata; |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 258 | dspi->rx += dspi->bytes_per_word; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 259 | } |
| 260 | |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 261 | static void dspi_tx_dma_callback(void *arg) |
| 262 | { |
| 263 | struct fsl_dspi *dspi = arg; |
| 264 | struct fsl_dspi_dma *dma = dspi->dma; |
| 265 | |
| 266 | complete(&dma->cmd_tx_complete); |
| 267 | } |
| 268 | |
| 269 | static void dspi_rx_dma_callback(void *arg) |
| 270 | { |
| 271 | struct fsl_dspi *dspi = arg; |
| 272 | struct fsl_dspi_dma *dma = dspi->dma; |
Sanchayan Maity | 1eaccf2 | 2016-11-22 12:31:30 +0530 | [diff] [blame] | 273 | int i; |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 274 | |
Esben Haabendal | 4779f23 | 2018-06-20 09:34:32 +0200 | [diff] [blame] | 275 | if (dspi->rx) { |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 276 | for (i = 0; i < dma->curr_xfer_len; i++) |
| 277 | dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]); |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | complete(&dma->cmd_rx_complete); |
| 281 | } |
| 282 | |
| 283 | static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) |
| 284 | { |
| 285 | struct fsl_dspi_dma *dma = dspi->dma; |
| 286 | struct device *dev = &dspi->pdev->dev; |
| 287 | int time_left; |
Sanchayan Maity | 1eaccf2 | 2016-11-22 12:31:30 +0530 | [diff] [blame] | 288 | int i; |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 289 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 290 | for (i = 0; i < dma->curr_xfer_len; i++) |
| 291 | dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi); |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 292 | |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 293 | dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, |
| 294 | dma->tx_dma_phys, |
Sanchayan Maity | 1eaccf2 | 2016-11-22 12:31:30 +0530 | [diff] [blame] | 295 | dma->curr_xfer_len * |
| 296 | DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 297 | DMA_MEM_TO_DEV, |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 298 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 299 | if (!dma->tx_desc) { |
| 300 | dev_err(dev, "Not able to get desc for DMA xfer\n"); |
| 301 | return -EIO; |
| 302 | } |
| 303 | |
| 304 | dma->tx_desc->callback = dspi_tx_dma_callback; |
| 305 | dma->tx_desc->callback_param = dspi; |
| 306 | if (dma_submit_error(dmaengine_submit(dma->tx_desc))) { |
| 307 | dev_err(dev, "DMA submit failed\n"); |
| 308 | return -EINVAL; |
| 309 | } |
| 310 | |
| 311 | dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, |
| 312 | dma->rx_dma_phys, |
Sanchayan Maity | 1eaccf2 | 2016-11-22 12:31:30 +0530 | [diff] [blame] | 313 | dma->curr_xfer_len * |
| 314 | DMA_SLAVE_BUSWIDTH_4_BYTES, |
| 315 | DMA_DEV_TO_MEM, |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 316 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 317 | if (!dma->rx_desc) { |
| 318 | dev_err(dev, "Not able to get desc for DMA xfer\n"); |
| 319 | return -EIO; |
| 320 | } |
| 321 | |
| 322 | dma->rx_desc->callback = dspi_rx_dma_callback; |
| 323 | dma->rx_desc->callback_param = dspi; |
| 324 | if (dma_submit_error(dmaengine_submit(dma->rx_desc))) { |
| 325 | dev_err(dev, "DMA submit failed\n"); |
| 326 | return -EINVAL; |
| 327 | } |
| 328 | |
| 329 | reinit_completion(&dspi->dma->cmd_rx_complete); |
| 330 | reinit_completion(&dspi->dma->cmd_tx_complete); |
| 331 | |
| 332 | dma_async_issue_pending(dma->chan_rx); |
| 333 | dma_async_issue_pending(dma->chan_tx); |
| 334 | |
Lukasz Majewski | 5ce3cc5 | 2019-02-05 23:13:49 +0100 | [diff] [blame] | 335 | if (spi_controller_is_slave(dspi->master)) { |
| 336 | wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete); |
| 337 | return 0; |
| 338 | } |
| 339 | |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 340 | time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete, |
| 341 | DMA_COMPLETION_TIMEOUT); |
| 342 | if (time_left == 0) { |
| 343 | dev_err(dev, "DMA tx timeout\n"); |
| 344 | dmaengine_terminate_all(dma->chan_tx); |
| 345 | dmaengine_terminate_all(dma->chan_rx); |
| 346 | return -ETIMEDOUT; |
| 347 | } |
| 348 | |
| 349 | time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete, |
| 350 | DMA_COMPLETION_TIMEOUT); |
| 351 | if (time_left == 0) { |
| 352 | dev_err(dev, "DMA rx timeout\n"); |
| 353 | dmaengine_terminate_all(dma->chan_tx); |
| 354 | dmaengine_terminate_all(dma->chan_rx); |
| 355 | return -ETIMEDOUT; |
| 356 | } |
| 357 | |
| 358 | return 0; |
| 359 | } |
| 360 | |
| 361 | static int dspi_dma_xfer(struct fsl_dspi *dspi) |
| 362 | { |
| 363 | struct fsl_dspi_dma *dma = dspi->dma; |
| 364 | struct device *dev = &dspi->pdev->dev; |
Andrey Smirnov | 5f8f803 | 2018-07-16 21:33:29 -0700 | [diff] [blame] | 365 | struct spi_message *message = dspi->cur_msg; |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 366 | int curr_remaining_bytes; |
| 367 | int bytes_per_buffer; |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 368 | int ret = 0; |
| 369 | |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 370 | curr_remaining_bytes = dspi->len; |
Sanchayan Maity | 1eaccf2 | 2016-11-22 12:31:30 +0530 | [diff] [blame] | 371 | bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE; |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 372 | while (curr_remaining_bytes) { |
| 373 | /* Check if current transfer fits the DMA buffer */ |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 374 | dma->curr_xfer_len = curr_remaining_bytes |
| 375 | / dspi->bytes_per_word; |
Sanchayan Maity | 1eaccf2 | 2016-11-22 12:31:30 +0530 | [diff] [blame] | 376 | if (dma->curr_xfer_len > bytes_per_buffer) |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 377 | dma->curr_xfer_len = bytes_per_buffer; |
| 378 | |
| 379 | ret = dspi_next_xfer_dma_submit(dspi); |
| 380 | if (ret) { |
| 381 | dev_err(dev, "DMA transfer failed\n"); |
| 382 | goto exit; |
| 383 | |
| 384 | } else { |
Andrey Smirnov | 5f8f803 | 2018-07-16 21:33:29 -0700 | [diff] [blame] | 385 | const int len = |
| 386 | dma->curr_xfer_len * dspi->bytes_per_word; |
| 387 | curr_remaining_bytes -= len; |
| 388 | message->actual_length += len; |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 389 | if (curr_remaining_bytes < 0) |
| 390 | curr_remaining_bytes = 0; |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 391 | } |
| 392 | } |
| 393 | |
| 394 | exit: |
| 395 | return ret; |
| 396 | } |
| 397 | |
| 398 | static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) |
| 399 | { |
| 400 | struct fsl_dspi_dma *dma; |
| 401 | struct dma_slave_config cfg; |
| 402 | struct device *dev = &dspi->pdev->dev; |
| 403 | int ret; |
| 404 | |
| 405 | dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); |
| 406 | if (!dma) |
| 407 | return -ENOMEM; |
| 408 | |
| 409 | dma->chan_rx = dma_request_slave_channel(dev, "rx"); |
| 410 | if (!dma->chan_rx) { |
| 411 | dev_err(dev, "rx dma channel not available\n"); |
| 412 | ret = -ENODEV; |
| 413 | return ret; |
| 414 | } |
| 415 | |
| 416 | dma->chan_tx = dma_request_slave_channel(dev, "tx"); |
| 417 | if (!dma->chan_tx) { |
| 418 | dev_err(dev, "tx dma channel not available\n"); |
| 419 | ret = -ENODEV; |
| 420 | goto err_tx_channel; |
| 421 | } |
| 422 | |
| 423 | dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, |
| 424 | &dma->tx_dma_phys, GFP_KERNEL); |
| 425 | if (!dma->tx_dma_buf) { |
| 426 | ret = -ENOMEM; |
| 427 | goto err_tx_dma_buf; |
| 428 | } |
| 429 | |
| 430 | dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, |
| 431 | &dma->rx_dma_phys, GFP_KERNEL); |
| 432 | if (!dma->rx_dma_buf) { |
| 433 | ret = -ENOMEM; |
| 434 | goto err_rx_dma_buf; |
| 435 | } |
| 436 | |
| 437 | cfg.src_addr = phy_addr + SPI_POPR; |
| 438 | cfg.dst_addr = phy_addr + SPI_PUSHR; |
| 439 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 440 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 441 | cfg.src_maxburst = 1; |
| 442 | cfg.dst_maxburst = 1; |
| 443 | |
| 444 | cfg.direction = DMA_DEV_TO_MEM; |
| 445 | ret = dmaengine_slave_config(dma->chan_rx, &cfg); |
| 446 | if (ret) { |
| 447 | dev_err(dev, "can't configure rx dma channel\n"); |
| 448 | ret = -EINVAL; |
| 449 | goto err_slave_config; |
| 450 | } |
| 451 | |
| 452 | cfg.direction = DMA_MEM_TO_DEV; |
| 453 | ret = dmaengine_slave_config(dma->chan_tx, &cfg); |
| 454 | if (ret) { |
| 455 | dev_err(dev, "can't configure tx dma channel\n"); |
| 456 | ret = -EINVAL; |
| 457 | goto err_slave_config; |
| 458 | } |
| 459 | |
| 460 | dspi->dma = dma; |
| 461 | init_completion(&dma->cmd_tx_complete); |
| 462 | init_completion(&dma->cmd_rx_complete); |
| 463 | |
| 464 | return 0; |
| 465 | |
| 466 | err_slave_config: |
Sanchayan Maity | 27d21e9 | 2016-11-22 12:31:32 +0530 | [diff] [blame] | 467 | dma_free_coherent(dev, DSPI_DMA_BUFSIZE, |
| 468 | dma->rx_dma_buf, dma->rx_dma_phys); |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 469 | err_rx_dma_buf: |
Sanchayan Maity | 27d21e9 | 2016-11-22 12:31:32 +0530 | [diff] [blame] | 470 | dma_free_coherent(dev, DSPI_DMA_BUFSIZE, |
| 471 | dma->tx_dma_buf, dma->tx_dma_phys); |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 472 | err_tx_dma_buf: |
| 473 | dma_release_channel(dma->chan_tx); |
| 474 | err_tx_channel: |
| 475 | dma_release_channel(dma->chan_rx); |
| 476 | |
| 477 | devm_kfree(dev, dma); |
| 478 | dspi->dma = NULL; |
| 479 | |
| 480 | return ret; |
| 481 | } |
| 482 | |
| 483 | static void dspi_release_dma(struct fsl_dspi *dspi) |
| 484 | { |
| 485 | struct fsl_dspi_dma *dma = dspi->dma; |
| 486 | struct device *dev = &dspi->pdev->dev; |
| 487 | |
| 488 | if (dma) { |
| 489 | if (dma->chan_tx) { |
| 490 | dma_unmap_single(dev, dma->tx_dma_phys, |
| 491 | DSPI_DMA_BUFSIZE, DMA_TO_DEVICE); |
| 492 | dma_release_channel(dma->chan_tx); |
| 493 | } |
| 494 | |
| 495 | if (dma->chan_rx) { |
| 496 | dma_unmap_single(dev, dma->rx_dma_phys, |
| 497 | DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE); |
| 498 | dma_release_channel(dma->chan_rx); |
| 499 | } |
| 500 | } |
| 501 | } |
| 502 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 503 | static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, |
| 504 | unsigned long clkrate) |
| 505 | { |
| 506 | /* Valid baud rate pre-scaler values */ |
| 507 | int pbr_tbl[4] = {2, 3, 5, 7}; |
| 508 | int brs[16] = { 2, 4, 6, 8, |
| 509 | 16, 32, 64, 128, |
| 510 | 256, 512, 1024, 2048, |
| 511 | 4096, 8192, 16384, 32768 }; |
Aaron Brice | 6fd6308 | 2015-03-30 10:49:15 -0700 | [diff] [blame] | 512 | int scale_needed, scale, minscale = INT_MAX; |
| 513 | int i, j; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 514 | |
Aaron Brice | 6fd6308 | 2015-03-30 10:49:15 -0700 | [diff] [blame] | 515 | scale_needed = clkrate / speed_hz; |
Aaron Brice | e689d6d | 2015-04-03 13:39:29 -0700 | [diff] [blame] | 516 | if (clkrate % speed_hz) |
| 517 | scale_needed++; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 518 | |
Aaron Brice | 6fd6308 | 2015-03-30 10:49:15 -0700 | [diff] [blame] | 519 | for (i = 0; i < ARRAY_SIZE(brs); i++) |
| 520 | for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) { |
| 521 | scale = brs[i] * pbr_tbl[j]; |
| 522 | if (scale >= scale_needed) { |
| 523 | if (scale < minscale) { |
| 524 | minscale = scale; |
| 525 | *br = i; |
| 526 | *pbr = j; |
| 527 | } |
| 528 | break; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 529 | } |
| 530 | } |
| 531 | |
Aaron Brice | 6fd6308 | 2015-03-30 10:49:15 -0700 | [diff] [blame] | 532 | if (minscale == INT_MAX) { |
| 533 | pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n", |
| 534 | speed_hz, clkrate); |
| 535 | *pbr = ARRAY_SIZE(pbr_tbl) - 1; |
| 536 | *br = ARRAY_SIZE(brs) - 1; |
| 537 | } |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 538 | } |
| 539 | |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 540 | static void ns_delay_scale(char *psc, char *sc, int delay_ns, |
| 541 | unsigned long clkrate) |
| 542 | { |
| 543 | int pscale_tbl[4] = {1, 3, 5, 7}; |
| 544 | int scale_needed, scale, minscale = INT_MAX; |
| 545 | int i, j; |
| 546 | u32 remainder; |
| 547 | |
| 548 | scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC, |
| 549 | &remainder); |
| 550 | if (remainder) |
| 551 | scale_needed++; |
| 552 | |
| 553 | for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++) |
| 554 | for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) { |
| 555 | scale = pscale_tbl[i] * (2 << j); |
| 556 | if (scale >= scale_needed) { |
| 557 | if (scale < minscale) { |
| 558 | minscale = scale; |
| 559 | *psc = i; |
| 560 | *sc = j; |
| 561 | } |
| 562 | break; |
| 563 | } |
| 564 | } |
| 565 | |
| 566 | if (minscale == INT_MAX) { |
| 567 | pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value", |
| 568 | delay_ns, clkrate); |
| 569 | *psc = ARRAY_SIZE(pscale_tbl) - 1; |
| 570 | *sc = SPI_CTAR_SCALE_BITS; |
| 571 | } |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 572 | } |
| 573 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 574 | static void fifo_write(struct fsl_dspi *dspi) |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 575 | { |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 576 | regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 577 | } |
| 578 | |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 579 | static void cmd_fifo_write(struct fsl_dspi *dspi) |
| 580 | { |
| 581 | u16 cmd = dspi->tx_cmd; |
| 582 | |
| 583 | if (dspi->len > 0) |
| 584 | cmd |= SPI_PUSHR_CMD_CONT; |
| 585 | regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); |
| 586 | } |
| 587 | |
| 588 | static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata) |
| 589 | { |
| 590 | regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); |
| 591 | } |
| 592 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 593 | static void dspi_tcfq_write(struct fsl_dspi *dspi) |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 594 | { |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 595 | /* Clear transfer count */ |
| 596 | dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 597 | |
| 598 | if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) { |
| 599 | /* Write two TX FIFO entries first, and then the corresponding |
| 600 | * CMD FIFO entry. |
| 601 | */ |
| 602 | u32 data = dspi_pop_tx(dspi); |
| 603 | |
| 604 | if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE(1)) { |
| 605 | /* LSB */ |
| 606 | tx_fifo_write(dspi, data & 0xFFFF); |
| 607 | tx_fifo_write(dspi, data >> 16); |
| 608 | } else { |
| 609 | /* MSB */ |
| 610 | tx_fifo_write(dspi, data >> 16); |
| 611 | tx_fifo_write(dspi, data & 0xFFFF); |
| 612 | } |
| 613 | cmd_fifo_write(dspi); |
| 614 | } else { |
| 615 | /* Write one entry to both TX FIFO and CMD FIFO |
| 616 | * simultaneously. |
| 617 | */ |
| 618 | fifo_write(dspi); |
| 619 | } |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 620 | } |
| 621 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 622 | static u32 fifo_read(struct fsl_dspi *dspi) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 623 | { |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 624 | u32 rxdata = 0; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 625 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 626 | regmap_read(dspi->regmap, SPI_POPR, &rxdata); |
| 627 | return rxdata; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 628 | } |
| 629 | |
| 630 | static void dspi_tcfq_read(struct fsl_dspi *dspi) |
| 631 | { |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 632 | dspi_push_rx(dspi, fifo_read(dspi)); |
| 633 | } |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 634 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 635 | static void dspi_eoq_write(struct fsl_dspi *dspi) |
| 636 | { |
| 637 | int fifo_size = DSPI_FIFO_SIZE; |
Angelo Dureghello | 5223c9c1 | 2018-08-18 01:51:58 +0200 | [diff] [blame] | 638 | u16 xfer_cmd = dspi->tx_cmd; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 639 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 640 | /* Fill TX FIFO with as many transfers as possible */ |
| 641 | while (dspi->len && fifo_size--) { |
Angelo Dureghello | 5223c9c1 | 2018-08-18 01:51:58 +0200 | [diff] [blame] | 642 | dspi->tx_cmd = xfer_cmd; |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 643 | /* Request EOQF for last transfer in FIFO */ |
| 644 | if (dspi->len == dspi->bytes_per_word || fifo_size == 0) |
| 645 | dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; |
| 646 | /* Clear transfer count for first transfer in FIFO */ |
| 647 | if (fifo_size == (DSPI_FIFO_SIZE - 1)) |
| 648 | dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; |
| 649 | /* Write combined TX FIFO and CMD FIFO entry */ |
| 650 | fifo_write(dspi); |
| 651 | } |
| 652 | } |
| 653 | |
| 654 | static void dspi_eoq_read(struct fsl_dspi *dspi) |
| 655 | { |
| 656 | int fifo_size = DSPI_FIFO_SIZE; |
| 657 | |
| 658 | /* Read one FIFO entry at and push to rx buffer */ |
| 659 | while ((dspi->rx < dspi->rx_end) && fifo_size--) |
| 660 | dspi_push_rx(dspi, fifo_read(dspi)); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 661 | } |
| 662 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 663 | static int dspi_transfer_one_message(struct spi_master *master, |
| 664 | struct spi_message *message) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 665 | { |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 666 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
| 667 | struct spi_device *spi = message->spi; |
| 668 | struct spi_transfer *transfer; |
| 669 | int status = 0; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 670 | enum dspi_trans_mode trans_mode; |
| 671 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 672 | message->actual_length = 0; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 673 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 674 | list_for_each_entry(transfer, &message->transfers, transfer_list) { |
| 675 | dspi->cur_transfer = transfer; |
| 676 | dspi->cur_msg = message; |
| 677 | dspi->cur_chip = spi_get_ctldata(spi); |
Esben Haabendal | 9e1dc9b | 2018-06-20 09:34:33 +0200 | [diff] [blame] | 678 | /* Prepare command word for CMD FIFO */ |
| 679 | dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) | |
| 680 | SPI_PUSHR_CMD_PCS(spi->chip_select); |
Andrey Vostrikov | 92dc20d | 2016-04-05 15:33:14 +0300 | [diff] [blame] | 681 | if (list_is_last(&dspi->cur_transfer->transfer_list, |
Esben Haabendal | 9e1dc9b | 2018-06-20 09:34:33 +0200 | [diff] [blame] | 682 | &dspi->cur_msg->transfers)) { |
| 683 | /* Leave PCS activated after last transfer when |
| 684 | * cs_change is set. |
| 685 | */ |
| 686 | if (transfer->cs_change) |
| 687 | dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; |
| 688 | } else { |
| 689 | /* Keep PCS active between transfers in same message |
| 690 | * when cs_change is not set, and de-activate PCS |
| 691 | * between transfers in the same message when |
| 692 | * cs_change is set. |
| 693 | */ |
| 694 | if (!transfer->cs_change) |
| 695 | dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; |
| 696 | } |
| 697 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 698 | dspi->void_write_data = dspi->cur_chip->void_write_data; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 699 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 700 | dspi->tx = transfer->tx_buf; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 701 | dspi->rx = transfer->rx_buf; |
| 702 | dspi->rx_end = dspi->rx + transfer->len; |
| 703 | dspi->len = transfer->len; |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 704 | /* Validated transfer specific frame size (defaults applied) */ |
| 705 | dspi->bits_per_word = transfer->bits_per_word; |
| 706 | if (transfer->bits_per_word <= 8) |
| 707 | dspi->bytes_per_word = 1; |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 708 | else if (transfer->bits_per_word <= 16) |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 709 | dspi->bytes_per_word = 2; |
Esben Haabendal | 8fcd151 | 2018-06-20 09:34:40 +0200 | [diff] [blame] | 710 | else |
| 711 | dspi->bytes_per_word = 4; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 712 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 713 | regmap_update_bits(dspi->regmap, SPI_MCR, |
Esben Haabendal | d87e08f | 2018-06-20 09:34:37 +0200 | [diff] [blame] | 714 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, |
| 715 | SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); |
Bhuvanchandra DV | ef22d16 | 2015-12-10 11:25:30 +0530 | [diff] [blame] | 716 | regmap_write(dspi->regmap, SPI_CTAR(0), |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 717 | dspi->cur_chip->ctar_val | |
| 718 | SPI_FRAME_BITS(transfer->bits_per_word)); |
Esben Haabendal | 51d583a | 2018-06-20 09:34:39 +0200 | [diff] [blame] | 719 | if (dspi->devtype_data->xspi_mode) |
| 720 | regmap_write(dspi->regmap, SPI_CTARE(0), |
| 721 | SPI_FRAME_EBITS(transfer->bits_per_word) |
| 722 | | SPI_CTARE_DTCP(1)); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 723 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 724 | trans_mode = dspi->devtype_data->trans_mode; |
| 725 | switch (trans_mode) { |
| 726 | case DSPI_EOQ_MODE: |
| 727 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 728 | dspi_eoq_write(dspi); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 729 | break; |
| 730 | case DSPI_TCFQ_MODE: |
| 731 | regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 732 | dspi_tcfq_write(dspi); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 733 | break; |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 734 | case DSPI_DMA_MODE: |
| 735 | regmap_write(dspi->regmap, SPI_RSER, |
| 736 | SPI_RSER_TFFFE | SPI_RSER_TFFFD | |
| 737 | SPI_RSER_RFDFE | SPI_RSER_RFDFD); |
| 738 | status = dspi_dma_xfer(dspi); |
Sanchayan Maity | 9811430 | 2016-11-17 17:46:48 +0530 | [diff] [blame] | 739 | break; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 740 | default: |
| 741 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", |
| 742 | trans_mode); |
| 743 | status = -EINVAL; |
| 744 | goto out; |
| 745 | } |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 746 | |
Sanchayan Maity | 9811430 | 2016-11-17 17:46:48 +0530 | [diff] [blame] | 747 | if (trans_mode != DSPI_DMA_MODE) { |
| 748 | if (wait_event_interruptible(dspi->waitq, |
| 749 | dspi->waitflags)) |
| 750 | dev_err(&dspi->pdev->dev, |
| 751 | "wait transfer complete fail!\n"); |
| 752 | dspi->waitflags = 0; |
| 753 | } |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 754 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 755 | if (transfer->delay_usecs) |
| 756 | udelay(transfer->delay_usecs); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 757 | } |
| 758 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 759 | out: |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 760 | message->status = status; |
| 761 | spi_finalize_current_message(master); |
| 762 | |
| 763 | return status; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 764 | } |
| 765 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 766 | static int dspi_setup(struct spi_device *spi) |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 767 | { |
| 768 | struct chip_data *chip; |
| 769 | struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 770 | struct fsl_dspi_platform_data *pdata; |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 771 | u32 cs_sck_delay = 0, sck_cs_delay = 0; |
| 772 | unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0; |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 773 | unsigned char pasc = 0, asc = 0; |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 774 | unsigned long clkrate; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 775 | |
| 776 | /* Only alloc on first setup */ |
| 777 | chip = spi_get_ctldata(spi); |
| 778 | if (chip == NULL) { |
Bhuvanchandra DV | 973fbce | 2015-01-27 16:27:20 +0530 | [diff] [blame] | 779 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 780 | if (!chip) |
| 781 | return -ENOMEM; |
| 782 | } |
| 783 | |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 784 | pdata = dev_get_platdata(&dspi->pdev->dev); |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 785 | |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 786 | if (!pdata) { |
| 787 | of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay", |
| 788 | &cs_sck_delay); |
| 789 | |
| 790 | of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay", |
| 791 | &sck_cs_delay); |
| 792 | } else { |
| 793 | cs_sck_delay = pdata->cs_sck_delay; |
| 794 | sck_cs_delay = pdata->sck_cs_delay; |
| 795 | } |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 796 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 797 | chip->void_write_data = 0; |
| 798 | |
Aaron Brice | 95bf15f | 2015-04-03 13:39:31 -0700 | [diff] [blame] | 799 | clkrate = clk_get_rate(dspi->clk); |
| 800 | hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); |
| 801 | |
| 802 | /* Set PCS to SCK delay scale values */ |
| 803 | ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate); |
| 804 | |
| 805 | /* Set After SCK delay scale values */ |
| 806 | ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 807 | |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 808 | chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) |
Lukasz Majewski | 5ce3cc5 | 2019-02-05 23:13:49 +0100 | [diff] [blame] | 809 | | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0); |
| 810 | |
| 811 | if (!spi_controller_is_slave(dspi->master)) { |
| 812 | chip->ctar_val |= SPI_CTAR_LSBFE(spi->mode & |
| 813 | SPI_LSB_FIRST ? 1 : 0) |
| 814 | | SPI_CTAR_PCSSCK(pcssck) |
| 815 | | SPI_CTAR_CSSCK(cssck) |
| 816 | | SPI_CTAR_PASC(pasc) |
| 817 | | SPI_CTAR_ASC(asc) |
| 818 | | SPI_CTAR_PBR(pbr) |
| 819 | | SPI_CTAR_BR(br); |
| 820 | } |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 821 | |
| 822 | spi_set_ctldata(spi, chip); |
| 823 | |
| 824 | return 0; |
| 825 | } |
| 826 | |
Bhuvanchandra DV | 973fbce | 2015-01-27 16:27:20 +0530 | [diff] [blame] | 827 | static void dspi_cleanup(struct spi_device *spi) |
| 828 | { |
| 829 | struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi); |
| 830 | |
| 831 | dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n", |
| 832 | spi->master->bus_num, spi->chip_select); |
| 833 | |
| 834 | kfree(chip); |
| 835 | } |
| 836 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 837 | static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
| 838 | { |
| 839 | struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 840 | struct spi_message *msg = dspi->cur_msg; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 841 | enum dspi_trans_mode trans_mode; |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 842 | u32 spi_sr, spi_tcr; |
Esben Haabendal | 0a4ec2c | 2018-06-20 09:34:34 +0200 | [diff] [blame] | 843 | u16 spi_tcnt; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 844 | |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 845 | regmap_read(dspi->regmap, SPI_SR, &spi_sr); |
| 846 | regmap_write(dspi->regmap, SPI_SR, spi_sr); |
| 847 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 848 | |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 849 | if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) { |
Esben Haabendal | 0a4ec2c | 2018-06-20 09:34:34 +0200 | [diff] [blame] | 850 | /* Get transfer counter (in number of SPI transfers). It was |
| 851 | * reset to 0 when transfer(s) were started. |
| 852 | */ |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 853 | regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); |
| 854 | spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); |
Esben Haabendal | 0a4ec2c | 2018-06-20 09:34:34 +0200 | [diff] [blame] | 855 | /* Update total number of bytes that were transferred */ |
Esben Haabendal | dadcf4a | 2018-06-20 09:34:35 +0200 | [diff] [blame] | 856 | msg->actual_length += spi_tcnt * dspi->bytes_per_word; |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 857 | |
| 858 | trans_mode = dspi->devtype_data->trans_mode; |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 859 | switch (trans_mode) { |
| 860 | case DSPI_EOQ_MODE: |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 861 | dspi_eoq_read(dspi); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 862 | break; |
| 863 | case DSPI_TCFQ_MODE: |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 864 | dspi_tcfq_read(dspi); |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 865 | break; |
| 866 | default: |
| 867 | dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", |
| 868 | trans_mode); |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 869 | return IRQ_HANDLED; |
| 870 | } |
| 871 | |
| 872 | if (!dspi->len) { |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 873 | dspi->waitflags = 1; |
| 874 | wake_up_interruptible(&dspi->waitq); |
| 875 | } else { |
| 876 | switch (trans_mode) { |
| 877 | case DSPI_EOQ_MODE: |
| 878 | dspi_eoq_write(dspi); |
| 879 | break; |
| 880 | case DSPI_TCFQ_MODE: |
| 881 | dspi_tcfq_write(dspi); |
| 882 | break; |
| 883 | default: |
| 884 | dev_err(&dspi->pdev->dev, |
| 885 | "unsupported trans_mode %u\n", |
| 886 | trans_mode); |
| 887 | } |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 888 | } |
| 889 | } |
Haikun Wang | c042af9 | 2015-06-09 19:45:37 +0800 | [diff] [blame] | 890 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 891 | return IRQ_HANDLED; |
| 892 | } |
| 893 | |
Jingoo Han | 790d190 | 2014-05-07 16:45:41 +0900 | [diff] [blame] | 894 | static const struct of_device_id fsl_dspi_dt_ids[] = { |
Julia Lawall | 230c08b | 2018-01-02 14:28:06 +0100 | [diff] [blame] | 895 | { .compatible = "fsl,vf610-dspi", .data = &vf610_data, }, |
| 896 | { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, }, |
| 897 | { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, }, |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 898 | { /* sentinel */ } |
| 899 | }; |
| 900 | MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); |
| 901 | |
| 902 | #ifdef CONFIG_PM_SLEEP |
| 903 | static int dspi_suspend(struct device *dev) |
| 904 | { |
| 905 | struct spi_master *master = dev_get_drvdata(dev); |
| 906 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
| 907 | |
| 908 | spi_master_suspend(master); |
| 909 | clk_disable_unprepare(dspi->clk); |
| 910 | |
Mirza Krak | 432a17d | 2015-06-12 18:55:22 +0200 | [diff] [blame] | 911 | pinctrl_pm_select_sleep_state(dev); |
| 912 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 913 | return 0; |
| 914 | } |
| 915 | |
| 916 | static int dspi_resume(struct device *dev) |
| 917 | { |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 918 | struct spi_master *master = dev_get_drvdata(dev); |
| 919 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
Fabio Estevam | 1c5ea2b | 2016-08-21 23:05:30 -0300 | [diff] [blame] | 920 | int ret; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 921 | |
Mirza Krak | 432a17d | 2015-06-12 18:55:22 +0200 | [diff] [blame] | 922 | pinctrl_pm_select_default_state(dev); |
| 923 | |
Fabio Estevam | 1c5ea2b | 2016-08-21 23:05:30 -0300 | [diff] [blame] | 924 | ret = clk_prepare_enable(dspi->clk); |
| 925 | if (ret) |
| 926 | return ret; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 927 | spi_master_resume(master); |
| 928 | |
| 929 | return 0; |
| 930 | } |
| 931 | #endif /* CONFIG_PM_SLEEP */ |
| 932 | |
Jingoo Han | ba811ad | 2014-02-26 10:30:14 +0900 | [diff] [blame] | 933 | static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 934 | |
Esben Haabendal | 8570043 | 2018-06-20 09:34:36 +0200 | [diff] [blame] | 935 | static const struct regmap_range dspi_volatile_ranges[] = { |
| 936 | regmap_reg_range(SPI_MCR, SPI_TCR), |
| 937 | regmap_reg_range(SPI_SR, SPI_SR), |
| 938 | regmap_reg_range(SPI_PUSHR, SPI_RXFR3), |
| 939 | }; |
| 940 | |
| 941 | static const struct regmap_access_table dspi_volatile_table = { |
| 942 | .yes_ranges = dspi_volatile_ranges, |
| 943 | .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges), |
| 944 | }; |
| 945 | |
Xiubo Li | 409851c | 2014-10-09 11:27:45 +0800 | [diff] [blame] | 946 | static const struct regmap_config dspi_regmap_config = { |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 947 | .reg_bits = 32, |
| 948 | .val_bits = 32, |
| 949 | .reg_stride = 4, |
| 950 | .max_register = 0x88, |
Esben Haabendal | 8570043 | 2018-06-20 09:34:36 +0200 | [diff] [blame] | 951 | .volatile_table = &dspi_volatile_table, |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 952 | }; |
| 953 | |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 954 | static const struct regmap_range dspi_xspi_volatile_ranges[] = { |
| 955 | regmap_reg_range(SPI_MCR, SPI_TCR), |
| 956 | regmap_reg_range(SPI_SR, SPI_SR), |
| 957 | regmap_reg_range(SPI_PUSHR, SPI_RXFR3), |
| 958 | regmap_reg_range(SPI_SREX, SPI_SREX), |
| 959 | }; |
| 960 | |
| 961 | static const struct regmap_access_table dspi_xspi_volatile_table = { |
| 962 | .yes_ranges = dspi_xspi_volatile_ranges, |
| 963 | .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges), |
| 964 | }; |
| 965 | |
| 966 | static const struct regmap_config dspi_xspi_regmap_config[] = { |
| 967 | { |
| 968 | .reg_bits = 32, |
| 969 | .val_bits = 32, |
| 970 | .reg_stride = 4, |
| 971 | .max_register = 0x13c, |
| 972 | .volatile_table = &dspi_xspi_volatile_table, |
| 973 | }, |
| 974 | { |
| 975 | .name = "pushr", |
| 976 | .reg_bits = 16, |
| 977 | .val_bits = 16, |
| 978 | .reg_stride = 2, |
| 979 | .max_register = 0x2, |
| 980 | }, |
| 981 | }; |
| 982 | |
Yuan Yao | 5ee67b5 | 2016-10-17 18:02:34 +0800 | [diff] [blame] | 983 | static void dspi_init(struct fsl_dspi *dspi) |
| 984 | { |
Lukasz Majewski | 5ce3cc5 | 2019-02-05 23:13:49 +0100 | [diff] [blame] | 985 | unsigned int mcr = SPI_MCR_PCSIS | |
| 986 | (dspi->devtype_data->xspi_mode ? SPI_MCR_XSPI : 0); |
| 987 | |
| 988 | if (!spi_controller_is_slave(dspi->master)) |
| 989 | mcr |= SPI_MCR_MASTER; |
| 990 | |
| 991 | regmap_write(dspi->regmap, SPI_MCR, mcr); |
Yuan Yao | 5ee67b5 | 2016-10-17 18:02:34 +0800 | [diff] [blame] | 992 | regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); |
Esben Haabendal | 51d583a | 2018-06-20 09:34:39 +0200 | [diff] [blame] | 993 | if (dspi->devtype_data->xspi_mode) |
| 994 | regmap_write(dspi->regmap, SPI_CTARE(0), |
| 995 | SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1)); |
Yuan Yao | 5ee67b5 | 2016-10-17 18:02:34 +0800 | [diff] [blame] | 996 | } |
| 997 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 998 | static int dspi_probe(struct platform_device *pdev) |
| 999 | { |
| 1000 | struct device_node *np = pdev->dev.of_node; |
| 1001 | struct spi_master *master; |
| 1002 | struct fsl_dspi *dspi; |
| 1003 | struct resource *res; |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 1004 | const struct regmap_config *regmap_config; |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 1005 | void __iomem *base; |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 1006 | struct fsl_dspi_platform_data *pdata; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1007 | int ret = 0, cs_num, bus_num; |
| 1008 | |
| 1009 | master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); |
| 1010 | if (!master) |
| 1011 | return -ENOMEM; |
| 1012 | |
| 1013 | dspi = spi_master_get_devdata(master); |
| 1014 | dspi->pdev = pdev; |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 1015 | dspi->master = master; |
| 1016 | |
| 1017 | master->transfer = NULL; |
| 1018 | master->setup = dspi_setup; |
| 1019 | master->transfer_one_message = dspi_transfer_one_message; |
| 1020 | master->dev.of_node = pdev->dev.of_node; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1021 | |
Bhuvanchandra DV | 973fbce | 2015-01-27 16:27:20 +0530 | [diff] [blame] | 1022 | master->cleanup = dspi_cleanup; |
Kurt Kanzenbach | 00ac956 | 2017-11-13 08:47:21 +0100 | [diff] [blame] | 1023 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1024 | |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 1025 | pdata = dev_get_platdata(&pdev->dev); |
| 1026 | if (pdata) { |
| 1027 | master->num_chipselect = pdata->cs_num; |
| 1028 | master->bus_num = pdata->bus_num; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1029 | |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 1030 | dspi->devtype_data = &coldfire_data; |
| 1031 | } else { |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1032 | |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 1033 | ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); |
| 1034 | if (ret < 0) { |
| 1035 | dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); |
| 1036 | goto out_master_put; |
| 1037 | } |
| 1038 | master->num_chipselect = cs_num; |
| 1039 | |
| 1040 | ret = of_property_read_u32(np, "bus-num", &bus_num); |
| 1041 | if (ret < 0) { |
| 1042 | dev_err(&pdev->dev, "can't get bus-num\n"); |
| 1043 | goto out_master_put; |
| 1044 | } |
| 1045 | master->bus_num = bus_num; |
| 1046 | |
Lukasz Majewski | 5ce3cc5 | 2019-02-05 23:13:49 +0100 | [diff] [blame] | 1047 | if (of_property_read_bool(np, "spi-slave")) |
| 1048 | master->slave = true; |
| 1049 | |
Angelo Dureghello | ec7ed77 | 2017-10-28 00:23:01 +0200 | [diff] [blame] | 1050 | dspi->devtype_data = of_device_get_match_data(&pdev->dev); |
| 1051 | if (!dspi->devtype_data) { |
| 1052 | dev_err(&pdev->dev, "can't get devtype_data\n"); |
| 1053 | ret = -EFAULT; |
| 1054 | goto out_master_put; |
| 1055 | } |
Haikun Wang | d1f4a38 | 2015-06-09 19:45:27 +0800 | [diff] [blame] | 1056 | } |
| 1057 | |
Esben Haabendal | 35c9d46 | 2018-06-20 09:34:41 +0200 | [diff] [blame] | 1058 | if (dspi->devtype_data->xspi_mode) |
| 1059 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); |
| 1060 | else |
| 1061 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); |
| 1062 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1063 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 1064 | base = devm_ioremap_resource(&pdev->dev, res); |
| 1065 | if (IS_ERR(base)) { |
| 1066 | ret = PTR_ERR(base); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1067 | goto out_master_put; |
| 1068 | } |
| 1069 | |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 1070 | if (dspi->devtype_data->xspi_mode) |
| 1071 | regmap_config = &dspi_xspi_regmap_config[0]; |
| 1072 | else |
| 1073 | regmap_config = &dspi_regmap_config; |
| 1074 | dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config); |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 1075 | if (IS_ERR(dspi->regmap)) { |
| 1076 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", |
| 1077 | PTR_ERR(dspi->regmap)); |
Christophe JAILLET | fbad6c2 | 2017-02-19 14:19:02 +0100 | [diff] [blame] | 1078 | ret = PTR_ERR(dspi->regmap); |
| 1079 | goto out_master_put; |
Chao Fu | 1acbdeb | 2014-02-12 15:29:05 +0800 | [diff] [blame] | 1080 | } |
| 1081 | |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 1082 | if (dspi->devtype_data->xspi_mode) { |
| 1083 | dspi->regmap_pushr = devm_regmap_init_mmio( |
| 1084 | &pdev->dev, base + SPI_PUSHR, |
| 1085 | &dspi_xspi_regmap_config[1]); |
| 1086 | if (IS_ERR(dspi->regmap_pushr)) { |
| 1087 | dev_err(&pdev->dev, |
| 1088 | "failed to init pushr regmap: %ld\n", |
| 1089 | PTR_ERR(dspi->regmap_pushr)); |
Gustavo A. R. Silva | 80dc12c | 2018-06-21 08:22:09 -0500 | [diff] [blame] | 1090 | ret = PTR_ERR(dspi->regmap_pushr); |
Esben Haabendal | 58ba07ec | 2018-06-20 09:34:38 +0200 | [diff] [blame] | 1091 | goto out_master_put; |
| 1092 | } |
| 1093 | } |
| 1094 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1095 | dspi->clk = devm_clk_get(&pdev->dev, "dspi"); |
| 1096 | if (IS_ERR(dspi->clk)) { |
| 1097 | ret = PTR_ERR(dspi->clk); |
| 1098 | dev_err(&pdev->dev, "unable to get clock\n"); |
| 1099 | goto out_master_put; |
| 1100 | } |
Fabio Estevam | 1c5ea2b | 2016-08-21 23:05:30 -0300 | [diff] [blame] | 1101 | ret = clk_prepare_enable(dspi->clk); |
| 1102 | if (ret) |
| 1103 | goto out_master_put; |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1104 | |
Krzysztof Kozlowski | d8ffee2 | 2018-06-29 13:33:09 +0200 | [diff] [blame] | 1105 | dspi_init(dspi); |
| 1106 | dspi->irq = platform_get_irq(pdev, 0); |
| 1107 | if (dspi->irq < 0) { |
| 1108 | dev_err(&pdev->dev, "can't get platform irq\n"); |
| 1109 | ret = dspi->irq; |
| 1110 | goto out_clk_put; |
| 1111 | } |
| 1112 | |
Chuanhua Han | 13aed23 | 2018-10-29 11:11:16 +0800 | [diff] [blame] | 1113 | ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, |
| 1114 | IRQF_SHARED, pdev->name, dspi); |
Krzysztof Kozlowski | d8ffee2 | 2018-06-29 13:33:09 +0200 | [diff] [blame] | 1115 | if (ret < 0) { |
| 1116 | dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); |
| 1117 | goto out_clk_put; |
| 1118 | } |
| 1119 | |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 1120 | if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { |
Nikita Yushchenko | cddebdd | 2017-05-22 16:19:20 +0300 | [diff] [blame] | 1121 | ret = dspi_request_dma(dspi, res->start); |
| 1122 | if (ret < 0) { |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 1123 | dev_err(&pdev->dev, "can't get dma channels\n"); |
| 1124 | goto out_clk_put; |
| 1125 | } |
| 1126 | } |
| 1127 | |
Bhuvanchandra DV | 9419b20 | 2016-03-22 01:41:52 +0530 | [diff] [blame] | 1128 | master->max_speed_hz = |
| 1129 | clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; |
| 1130 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1131 | init_waitqueue_head(&dspi->waitq); |
Axel Lin | 017145f | 2014-02-14 12:49:12 +0800 | [diff] [blame] | 1132 | platform_set_drvdata(pdev, master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1133 | |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 1134 | ret = spi_register_master(master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1135 | if (ret != 0) { |
| 1136 | dev_err(&pdev->dev, "Problem registering DSPI master\n"); |
| 1137 | goto out_clk_put; |
| 1138 | } |
| 1139 | |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1140 | return ret; |
| 1141 | |
| 1142 | out_clk_put: |
| 1143 | clk_disable_unprepare(dspi->clk); |
| 1144 | out_master_put: |
| 1145 | spi_master_put(master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1146 | |
| 1147 | return ret; |
| 1148 | } |
| 1149 | |
| 1150 | static int dspi_remove(struct platform_device *pdev) |
| 1151 | { |
Axel Lin | 017145f | 2014-02-14 12:49:12 +0800 | [diff] [blame] | 1152 | struct spi_master *master = platform_get_drvdata(pdev); |
| 1153 | struct fsl_dspi *dspi = spi_master_get_devdata(master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1154 | |
| 1155 | /* Disconnect from the SPI framework */ |
Sanchayan Maity | 90ba370 | 2016-11-10 17:49:15 +0530 | [diff] [blame] | 1156 | dspi_release_dma(dspi); |
Wei Yongjun | 05209f4 | 2013-10-12 15:15:31 +0800 | [diff] [blame] | 1157 | clk_disable_unprepare(dspi->clk); |
Chao Fu | 9298bc7 | 2015-01-27 16:27:22 +0530 | [diff] [blame] | 1158 | spi_unregister_master(dspi->master); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1159 | |
| 1160 | return 0; |
| 1161 | } |
| 1162 | |
| 1163 | static struct platform_driver fsl_dspi_driver = { |
| 1164 | .driver.name = DRIVER_NAME, |
| 1165 | .driver.of_match_table = fsl_dspi_dt_ids, |
| 1166 | .driver.owner = THIS_MODULE, |
| 1167 | .driver.pm = &dspi_pm, |
| 1168 | .probe = dspi_probe, |
| 1169 | .remove = dspi_remove, |
| 1170 | }; |
| 1171 | module_platform_driver(fsl_dspi_driver); |
| 1172 | |
| 1173 | MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); |
Uwe Kleine-König | b444d1d | 2013-09-10 10:46:33 +0200 | [diff] [blame] | 1174 | MODULE_LICENSE("GPL"); |
Chao Fu | 349ad66 | 2013-08-16 11:08:55 +0800 | [diff] [blame] | 1175 | MODULE_ALIAS("platform:" DRIVER_NAME); |