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Thomas Gleixner09c434b2019-05-19 13:08:20 +01001// SPDX-License-Identifier: GPL-2.0-only
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002/*
3 * Driver for DBRI sound chip found on Sparcs.
Martin Habets43388292005-09-10 15:39:00 +02004 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02005 *
Krzysztof Helt1be54c82006-08-21 19:30:57 +02006 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
7 *
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02008 * Based entirely upon drivers/sbus/audio/dbri.c which is:
9 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
10 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
11 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020012 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
13 * on Sun SPARCStation 10, 20, LX and Voyager models.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020014 *
15 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
16 * data time multiplexer with ISDN support (aka T7259)
17 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
18 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
19 * Documentation:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020020 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020021 * Sparc Technology Business (courtesy of Sun Support)
22 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020023 * available from the Lucent (formerly AT&T microelectronics) home
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020024 * page.
25 * - http://www.freesoft.org/Linux/DBRI/
26 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
27 * Interfaces: CHI, Audio In & Out, 2 bits parallel
28 * Documentation: from the Crystal Semiconductor home page.
29 *
30 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020031 * memory and a serial device (long pipes, no. 0-15) or between two serial
32 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020033 * device (short pipes).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020034 * A timeslot defines the bit-offset and no. of bits read from a serial device.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020035 * The timeslots are linked to 6 circular lists, one for each direction for
36 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
37 * (the second one is a monitor/tee pipe, valid only for serial input).
38 *
39 * The mmcodec is connected via the CHI bus and needs the data & some
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020040 * parameters (volume, output selection) time multiplexed in 8 byte
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020041 * chunks. It also has a control mode, which serves for audio format setting.
42 *
43 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020044 * the same CHI bus, so I thought perhaps it is possible to use the on-board
45 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020046 * audio devices. But the SUN HW group decided against it, at least on my
47 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
48 * connected.
Martin Habets43388292005-09-10 15:39:00 +020049 *
50 * I've tried to stick to the following function naming conventions:
51 * snd_* ALSA stuff
Adrian Bunkd254c8f2006-06-30 18:29:51 +020052 * cs4215_* CS4215 codec specific stuff
Martin Habets43388292005-09-10 15:39:00 +020053 * dbri_* DBRI high-level stuff
54 * other DBRI low-level stuff
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020055 */
56
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020057#include <linux/interrupt.h>
58#include <linux/delay.h>
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020059#include <linux/irq.h>
60#include <linux/io.h>
David S. Miller738f2b72008-08-27 18:09:11 -070061#include <linux/dma-mapping.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090062#include <linux/gfp.h>
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020063
64#include <sound/core.h>
65#include <sound/pcm.h>
66#include <sound/pcm_params.h>
67#include <sound/info.h>
68#include <sound/control.h>
69#include <sound/initval.h>
70
Krzysztof Heltef285fe2007-09-06 15:02:33 +020071#include <linux/of.h>
David S. Miller2bd320f2008-08-27 00:30:59 -070072#include <linux/of_device.h>
Arun Sharma600634972011-07-26 16:09:06 -070073#include <linux/atomic.h>
Paul Gortmakerda155d52011-07-15 12:38:28 -040074#include <linux/module.h>
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020075
76MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
77MODULE_DESCRIPTION("Sun DBRI");
78MODULE_LICENSE("GPL");
79MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
80
81static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
82static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020083/* Enable this card */
Rusty Russella67ff6a2011-12-15 13:49:36 +103084static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020085
86module_param_array(index, int, NULL, 0444);
87MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
88module_param_array(id, charp, NULL, 0444);
89MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
90module_param_array(enable, bool, NULL, 0444);
91MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
92
Krzysztof Heltab93c7a2006-08-23 11:37:36 +020093#undef DBRI_DEBUG
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020094
95#define D_INT (1<<0)
96#define D_GEN (1<<1)
97#define D_CMD (1<<2)
98#define D_MM (1<<3)
99#define D_USR (1<<4)
100#define D_DESC (1<<5)
101
Takashi Iwai6581f4e2006-05-17 17:14:51 +0200102static int dbri_debug;
Martin Habets43388292005-09-10 15:39:00 +0200103module_param(dbri_debug, int, 0644);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200104MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
105
106#ifdef DBRI_DEBUG
107static char *cmds[] = {
108 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
109 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
110};
111
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200112#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200113
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200114#else
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200115#define dprintk(a, x...) do { } while (0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200116
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200117#endif /* DBRI_DEBUG */
118
Krzysztof Helt42fe7642006-08-16 12:53:34 +0200119#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
120 (intr << 27) | \
121 value)
122
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200123/***************************************************************************
124 CS4215 specific definitions and structures
125****************************************************************************/
126
127struct cs4215 {
128 __u8 data[4]; /* Data mode: Time slots 5-8 */
129 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
130 __u8 onboard;
131 __u8 offset; /* Bit offset from frame sync to time slot 1 */
132 volatile __u32 status;
133 volatile __u32 version;
134 __u8 precision; /* In bits, either 8 or 16 */
135 __u8 channels; /* 1 or 2 */
136};
137
138/*
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200139 * Control mode first
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200140 */
141
142/* Time Slot 1, Status register */
143#define CS4215_CLB (1<<2) /* Control Latch Bit */
144#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
145 /* 0: line: 2.8V, speaker 8V */
146#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
147#define CS4215_RSRVD_1 (1<<5)
148
149/* Time Slot 2, Data Format Register */
150#define CS4215_DFR_LINEAR16 0
151#define CS4215_DFR_ULAW 1
152#define CS4215_DFR_ALAW 2
153#define CS4215_DFR_LINEAR8 3
154#define CS4215_DFR_STEREO (1<<2)
155static struct {
156 unsigned short freq;
157 unsigned char xtal;
158 unsigned char csval;
159} CS4215_FREQ[] = {
160 { 8000, (1 << 4), (0 << 3) },
161 { 16000, (1 << 4), (1 << 3) },
162 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
163 { 32000, (1 << 4), (3 << 3) },
164 /* { NA, (1 << 4), (4 << 3) }, */
165 /* { NA, (1 << 4), (5 << 3) }, */
166 { 48000, (1 << 4), (6 << 3) },
167 { 9600, (1 << 4), (7 << 3) },
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200168 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200169 { 11025, (2 << 4), (1 << 3) },
170 { 18900, (2 << 4), (2 << 3) },
171 { 22050, (2 << 4), (3 << 3) },
172 { 37800, (2 << 4), (4 << 3) },
173 { 44100, (2 << 4), (5 << 3) },
174 { 33075, (2 << 4), (6 << 3) },
175 { 6615, (2 << 4), (7 << 3) },
176 { 0, 0, 0}
177};
178
179#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
180
181#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
182
183/* Time Slot 3, Serial Port Control register */
184#define CS4215_XEN (1<<0) /* 0: Enable serial output */
185#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
186#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
187#define CS4215_BSEL_128 (1<<2)
188#define CS4215_BSEL_256 (2<<2)
189#define CS4215_MCK_MAST (0<<4) /* Master clock */
190#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
191#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
192#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
193#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
194
195/* Time Slot 4, Test Register */
196#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
197#define CS4215_ENL (1<<1) /* Enable Loopback Testing */
198
199/* Time Slot 5, Parallel Port Register */
200/* Read only here and the same as the in data mode */
201
202/* Time Slot 6, Reserved */
203
204/* Time Slot 7, Version Register */
205#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
206
207/* Time Slot 8, Reserved */
208
209/*
210 * Data mode
211 */
212/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
213
214/* Time Slot 5, Output Setting */
215#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
216#define CS4215_LE (1<<6) /* Line Out Enable */
217#define CS4215_HE (1<<7) /* Headphone Enable */
218
219/* Time Slot 6, Output Setting */
220#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
221#define CS4215_SE (1<<6) /* Speaker Enable */
222#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
223
224/* Time Slot 7, Input Setting */
225#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
226#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200227#define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200228#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
229#define CS4215_PIO1 (1<<7)
230
231/* Time Slot 8, Input Setting */
232#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
233#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
234
235/***************************************************************************
236 DBRI specific definitions and structures
237****************************************************************************/
238
239/* DBRI main registers */
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200240#define REG0 0x00 /* Status and Control */
241#define REG1 0x04 /* Mode and Interrupt */
242#define REG2 0x08 /* Parallel IO */
243#define REG3 0x0c /* Test */
244#define REG8 0x20 /* Command Queue Pointer */
245#define REG9 0x24 /* Interrupt Queue Pointer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200246
247#define DBRI_NO_CMDS 64
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200248#define DBRI_INT_BLK 64
249#define DBRI_NO_DESCS 64
250#define DBRI_NO_PIPES 32
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200251#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200252
253#define DBRI_REC 0
254#define DBRI_PLAY 1
255#define DBRI_NO_STREAMS 2
256
257/* One transmit/receive descriptor */
Krzysztof Heltc2735442006-08-21 19:27:35 +0200258/* When ba != 0 descriptor is used */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200259struct dbri_mem {
260 volatile __u32 word1;
Krzysztof Helt16727d92006-08-17 16:59:28 +0200261 __u32 ba; /* Transmit/Receive Buffer Address */
262 __u32 nda; /* Next Descriptor Address */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200263 volatile __u32 word4;
264};
265
266/* This structure is in a DMA region where it can accessed by both
267 * the CPU and the DBRI
268 */
269struct dbri_dma {
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200270 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
Krzysztof Helt6fb98282006-08-16 12:54:29 +0200271 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200272 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
273};
274
275#define dbri_dma_off(member, elem) \
276 ((u32)(unsigned long) \
277 (&(((struct dbri_dma *)0)->member[elem])))
278
279enum in_or_out { PIPEinput, PIPEoutput };
280
281struct dbri_pipe {
282 u32 sdp; /* SDP command word */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200283 int nextpipe; /* Next pipe in linked list */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200284 int length; /* Length of timeslot (bits) */
285 int first_desc; /* Index of first descriptor */
286 int desc; /* Index of active descriptor */
287 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
288};
289
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200290/* Per stream (playback or record) information */
Takashi Iwai475675d2005-11-17 15:11:51 +0100291struct dbri_streaminfo {
292 struct snd_pcm_substream *substream;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200293 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200294 int size; /* Size of DMA buffer */
295 size_t offset; /* offset in user buffer */
296 int pipe; /* Data pipe used */
297 int left_gain; /* mixer elements */
298 int right_gain;
Takashi Iwai475675d2005-11-17 15:11:51 +0100299};
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200300
301/* This structure holds the information for both chips (DBRI & CS4215) */
Takashi Iwai475675d2005-11-17 15:11:51 +0100302struct snd_dbri {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200303 int regs_size, irq; /* Needed for unload */
Grant Likely2dc11582010-08-06 09:25:50 -0600304 struct platform_device *op; /* OF device info */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200305 spinlock_t lock;
306
Krzysztof Helt16727d92006-08-17 16:59:28 +0200307 struct dbri_dma *dma; /* Pointer to our DMA block */
Tushar Dave16f46052016-11-24 12:35:16 -0800308 dma_addr_t dma_dvma; /* DBRI visible DMA address */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200309
310 void __iomem *regs; /* dbri HW regs */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200311 int dbri_irqp; /* intr queue pointer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200312
313 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
Krzysztof Heltc2735442006-08-21 19:27:35 +0200314 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200315 spinlock_t cmdlock; /* Protects cmd queue accesses */
316 s32 *cmdptr; /* Pointer to the last queued cmd */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200317
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200318 int chi_bpf;
319
320 struct cs4215 mm; /* mmcodec special info */
321 /* per stream (playback/record) info */
322 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
Takashi Iwai475675d2005-11-17 15:11:51 +0100323};
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200324
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200325#define DBRI_MAX_VOLUME 63 /* Output volume */
326#define DBRI_MAX_GAIN 15 /* Input gain */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200327
328/* DBRI Reg0 - Status Control Register - defines. (Page 17) */
329#define D_P (1<<15) /* Program command & queue pointer valid */
330#define D_G (1<<14) /* Allow 4-Word SBus Burst */
331#define D_S (1<<13) /* Allow 16-Word SBus Burst */
332#define D_E (1<<12) /* Allow 8-Word SBus Burst */
333#define D_X (1<<7) /* Sanity Timer Disable */
334#define D_T (1<<6) /* Permit activation of the TE interface */
335#define D_N (1<<5) /* Permit activation of the NT interface */
336#define D_C (1<<4) /* Permit activation of the CHI interface */
337#define D_F (1<<3) /* Force Sanity Timer Time-Out */
338#define D_D (1<<2) /* Disable Master Mode */
339#define D_H (1<<1) /* Halt for Analysis */
340#define D_R (1<<0) /* Soft Reset */
341
342/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
343#define D_LITTLE_END (1<<8) /* Byte Order */
344#define D_BIG_END (0<<8) /* Byte Order */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200345#define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
346#define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
347#define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
348#define D_MBE (1<<1) /* Burst Error on SBus (read only) */
349#define D_IR (1<<0) /* Interrupt Indicator (read only) */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200350
351/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
352#define D_ENPIO3 (1<<7) /* Enable Pin 3 */
353#define D_ENPIO2 (1<<6) /* Enable Pin 2 */
354#define D_ENPIO1 (1<<5) /* Enable Pin 1 */
355#define D_ENPIO0 (1<<4) /* Enable Pin 0 */
356#define D_ENPIO (0xf0) /* Enable all the pins */
357#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
358#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
359#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
360#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
361
362/* DBRI Commands (Page 20) */
363#define D_WAIT 0x0 /* Stop execution */
364#define D_PAUSE 0x1 /* Flush long pipes */
365#define D_JUMP 0x2 /* New command queue */
366#define D_IIQ 0x3 /* Initialize Interrupt Queue */
367#define D_REX 0x4 /* Report command execution via interrupt */
368#define D_SDP 0x5 /* Setup Data Pipe */
369#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
370#define D_DTS 0x7 /* Define Time Slot */
371#define D_SSP 0x8 /* Set short Data Pipe */
372#define D_CHI 0x9 /* Set CHI Global Mode */
373#define D_NT 0xa /* NT Command */
374#define D_TE 0xb /* TE Command */
375#define D_CDEC 0xc /* Codec setup */
376#define D_TEST 0xd /* No comment */
377#define D_CDM 0xe /* CHI Data mode command */
378
379/* Special bits for some commands */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200380#define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200381
382/* Setup Data Pipe */
383/* IRM */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200384#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200385#define D_SDP_CHANGE (2<<18) /* Report any changes */
386#define D_SDP_EVERY (3<<18) /* Report any changes */
387#define D_SDP_EOL (1<<17) /* EOL interrupt enable */
388#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
389
390/* Pipe data MODE */
391#define D_SDP_MEM (0<<13) /* To/from memory */
392#define D_SDP_HDLC (2<<13)
393#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
394#define D_SDP_SER (4<<13) /* Serial to serial */
395#define D_SDP_FIXED (6<<13) /* Short only */
396#define D_SDP_MODE(v) ((v)&(7<<13))
397
398#define D_SDP_TO_SER (1<<12) /* Direction */
399#define D_SDP_FROM_SER (0<<12) /* Direction */
400#define D_SDP_MSB (1<<11) /* Bit order within Byte */
401#define D_SDP_LSB (0<<11) /* Bit order within Byte */
402#define D_SDP_P (1<<10) /* Pointer Valid */
403#define D_SDP_A (1<<8) /* Abort */
404#define D_SDP_C (1<<7) /* Clear */
405
406/* Define Time Slot */
407#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
408#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
409#define D_DTS_INS (1<<15) /* Insert Time Slot */
410#define D_DTS_DEL (0<<15) /* Delete Time Slot */
411#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
412#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
413
414/* Time Slot defines */
415#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
416#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
417#define D_TS_DI (1<<13) /* Data Invert */
418#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
419#define D_TS_MONITOR (2<<10) /* Monitor pipe */
420#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
421#define D_TS_ANCHOR (7<<10) /* Starting short pipes */
422#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200423#define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200424
425/* Concentration Highway Interface Modes */
426#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
427#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
428#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
429#define D_CHI_OD (1<<13) /* Open Drain Enable */
430#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
431#define D_CHI_FD (1<<11) /* Frame Drive */
432#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
433
434/* NT: These are here for completeness */
435#define D_NT_FBIT (1<<17) /* Frame Bit */
436#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
437#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
438#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200439#define D_NT_ISNT (1<<13) /* Configure interface as NT */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200440#define D_NT_FT (1<<12) /* Fixed Timing */
441#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
442#define D_NT_IFA (1<<10) /* Inhibit Final Activation */
443#define D_NT_ACT (1<<9) /* Activate Interface */
444#define D_NT_MFE (1<<8) /* Multiframe Enable */
445#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
446#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
447#define D_NT_FACT (1<<1) /* Force Activation */
448#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
449
450/* Codec Setup */
451#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
452#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
453#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
454
455/* Test */
456#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
457#define D_TEST_SIZE(v) ((v)<<11) /* */
458#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200459#define D_TEST_PROC 0x6 /* Microprocessor test */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200460#define D_TEST_SER 0x7 /* Serial-Controller test */
461#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
462#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
463#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
464#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
465#define D_TEST_DUMP 0xe /* ROM Dump */
466
467/* CHI Data Mode */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200468#define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
469#define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
470#define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
471#define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
472#define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
473#define D_CDM_REN (1 << 0) /* Receive Highway Enable */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200474
475/* The Interrupts */
476#define D_INTR_BRDY 1 /* Buffer Ready for processing */
477#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
478#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
479#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
480#define D_INTR_EOL 5 /* End of List */
481#define D_INTR_CMDI 6 /* Command has bean read */
482#define D_INTR_XCMP 8 /* Transmission of frame complete */
483#define D_INTR_SBRI 9 /* BRI status change info */
484#define D_INTR_FXDT 10 /* Fixed data change */
485#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
486#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
487#define D_INTR_DBYT 12 /* Dropped by frame slip */
488#define D_INTR_RBYT 13 /* Repeated by frame slip */
489#define D_INTR_LINT 14 /* Lost Interrupt */
490#define D_INTR_UNDR 15 /* DMA underrun */
491
492#define D_INTR_TE 32
493#define D_INTR_NT 34
494#define D_INTR_CHI 36
495#define D_INTR_CMD 38
496
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200497#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
498#define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
499#define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200500#define D_INTR_GETVAL(v) ((v) & 0xffff)
501#define D_INTR_GETRVAL(v) ((v) & 0xfffff)
502
503#define D_P_0 0 /* TE receive anchor */
504#define D_P_1 1 /* TE transmit anchor */
505#define D_P_2 2 /* NT transmit anchor */
506#define D_P_3 3 /* NT receive anchor */
507#define D_P_4 4 /* CHI send data */
508#define D_P_5 5 /* CHI receive data */
509#define D_P_6 6 /* */
510#define D_P_7 7 /* */
511#define D_P_8 8 /* */
512#define D_P_9 9 /* */
513#define D_P_10 10 /* */
514#define D_P_11 11 /* */
515#define D_P_12 12 /* */
516#define D_P_13 13 /* */
517#define D_P_14 14 /* */
518#define D_P_15 15 /* */
519#define D_P_16 16 /* CHI anchor pipe */
520#define D_P_17 17 /* CHI send */
521#define D_P_18 18 /* CHI receive */
522#define D_P_19 19 /* CHI receive */
523#define D_P_20 20 /* CHI receive */
524#define D_P_21 21 /* */
525#define D_P_22 22 /* */
526#define D_P_23 23 /* */
527#define D_P_24 24 /* */
528#define D_P_25 25 /* */
529#define D_P_26 26 /* */
530#define D_P_27 27 /* */
531#define D_P_28 28 /* */
532#define D_P_29 29 /* */
533#define D_P_30 30 /* */
534#define D_P_31 31 /* */
535
536/* Transmit descriptor defines */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200537#define DBRI_TD_F (1 << 31) /* End of Frame */
538#define DBRI_TD_D (1 << 30) /* Do not append CRC */
539#define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
540#define DBRI_TD_B (1 << 15) /* Final interrupt */
541#define DBRI_TD_M (1 << 14) /* Marker interrupt */
542#define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
543#define DBRI_TD_FCNT(v) (v) /* Flag Count */
544#define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
545#define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
546#define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
547#define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
548 /* Maximum buffer size per TD: almost 8KB */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200549#define DBRI_TD_MAXCNT ((1 << 13) - 4)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200550
551/* Receive descriptor defines */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200552#define DBRI_RD_F (1 << 31) /* End of Frame */
553#define DBRI_RD_C (1 << 30) /* Completed buffer */
554#define DBRI_RD_B (1 << 15) /* Final interrupt */
555#define DBRI_RD_M (1 << 14) /* Marker interrupt */
556#define DBRI_RD_BCNT(v) (v) /* Buffer size */
557#define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
558#define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
559#define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
560#define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
561#define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
562#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200563
564/* stream_info[] access */
565/* Translate the ALSA direction into the array index */
566#define DBRI_STREAMNO(substream) \
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200567 (substream->stream == \
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200568 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200569
570/* Return a pointer to dbri_streaminfo */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200571#define DBRI_STREAM(dbri, substream) \
572 &dbri->stream_info[DBRI_STREAMNO(substream)]
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200573
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200574/*
575 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
576 * So we have to reverse the bits. Note: not all bit lengths are supported
577 */
578static __u32 reverse_bytes(__u32 b, int len)
579{
580 switch (len) {
581 case 32:
582 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
Gustavo A. R. Silva83554cb2019-07-29 20:49:44 -0500583 /* fall through */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200584 case 16:
585 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
Gustavo A. R. Silva83554cb2019-07-29 20:49:44 -0500586 /* fall through */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200587 case 8:
588 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
Gustavo A. R. Silva83554cb2019-07-29 20:49:44 -0500589 /* fall through */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200590 case 4:
591 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
Gustavo A. R. Silva83554cb2019-07-29 20:49:44 -0500592 /* fall through */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200593 case 2:
594 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
595 case 1:
596 case 0:
597 break;
598 default:
599 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
Peter Senna Tschudin395d9dd2012-09-28 11:24:57 +0200600 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200601
602 return b;
603}
604
605/*
606****************************************************************************
607************** DBRI initialization and command synchronization *************
608****************************************************************************
609
610Commands are sent to the DBRI by building a list of them in memory,
611then writing the address of the first list item to DBRI register 8.
Martin Habets43388292005-09-10 15:39:00 +0200612The list is terminated with a WAIT command, which generates a
613CPU interrupt to signal completion.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200614
615Since the DBRI can run in parallel with the CPU, several means of
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200616synchronization present themselves. The method implemented here uses
617the dbri_cmdwait() to wait for execution of batch of sent commands.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200618
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200619A circular command buffer is used here. A new command is being added
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200620while another can be executed. The scheme works by adding two WAIT commands
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200621after each sent batch of commands. When the next batch is prepared it is
622added after the WAIT commands then the WAITs are replaced with single JUMP
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200623command to the new batch. The the DBRI is forced to reread the last WAIT
624command (replaced by the JUMP by then). If the DBRI is still executing
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200625previous commands the request to reread the WAIT command is ignored.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200626
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200627Every time a routine wants to write commands to the DBRI, it must
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200628first call dbri_cmdlock() and get pointer to a free space in
629dbri->dma->cmd buffer. After this, the commands can be written to
630the buffer, and dbri_cmdsend() is called with the final pointer value
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200631to send them to the DBRI.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200632
633*/
634
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200635#define MAXLOOPS 20
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200636/*
637 * Wait for the current command string to execute
638 */
639static void dbri_cmdwait(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200640{
Martin Habets43388292005-09-10 15:39:00 +0200641 int maxloops = MAXLOOPS;
Krzysztof Heltea543f12006-09-05 20:25:05 +0200642 unsigned long flags;
Martin Habets43388292005-09-10 15:39:00 +0200643
Martin Habets43388292005-09-10 15:39:00 +0200644 /* Delay if previous commands are still being processed */
Krzysztof Heltea543f12006-09-05 20:25:05 +0200645 spin_lock_irqsave(&dbri->lock, flags);
646 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
647 spin_unlock_irqrestore(&dbri->lock, flags);
Martin Habets43388292005-09-10 15:39:00 +0200648 msleep_interruptible(1);
Krzysztof Heltea543f12006-09-05 20:25:05 +0200649 spin_lock_irqsave(&dbri->lock, flags);
650 }
651 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200652
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200653 if (maxloops == 0)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200654 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200655 else
Martin Habets43388292005-09-10 15:39:00 +0200656 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
657 MAXLOOPS - maxloops - 1);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200658}
659/*
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200660 * Lock the command queue and return pointer to space for len cmd words
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200661 * It locks the cmdlock spinlock.
662 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200663static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200664{
Tushar Dave16f46052016-11-24 12:35:16 -0800665 u32 dvma_addr = (u32)dbri->dma_dvma;
666
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200667 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
668 len += 2;
669 spin_lock(&dbri->cmdlock);
670 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
671 return dbri->cmdptr + 2;
Tushar Dave16f46052016-11-24 12:35:16 -0800672 else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200673 return dbri->dma->cmd;
674 else
675 printk(KERN_ERR "DBRI: no space for commands.");
Martin Habets43388292005-09-10 15:39:00 +0200676
Al Viroae97dd92006-09-24 23:42:57 +0100677 return NULL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200678}
679
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200680/*
Robert P. J. Daybeb7dd82007-05-09 07:14:03 +0200681 * Send prepared cmd string. It works by writing a JUMP cmd into
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200682 * the last WAIT cmd and force DBRI to reread the cmd.
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200683 * The JUMP cmd points to the new cmd string.
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200684 * It also releases the cmdlock spinlock.
Krzysztof Heltea543f12006-09-05 20:25:05 +0200685 *
Krzysztof Heltca405872006-12-18 14:41:03 +0100686 * Lock must be held before calling this.
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200687 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200688static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200689{
Tushar Dave16f46052016-11-24 12:35:16 -0800690 u32 dvma_addr = (u32)dbri->dma_dvma;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200691 s32 tmp, addr;
692 static int wait_id = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200693
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200694 wait_id++;
695 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
696 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
697 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
698
699 /* Replace the last command with JUMP */
Tushar Dave16f46052016-11-24 12:35:16 -0800700 addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200701 *(dbri->cmdptr+1) = addr;
702 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
703
704#ifdef DBRI_DEBUG
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200705 if (cmd > dbri->cmdptr) {
706 s32 *ptr;
707
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200708 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200709 dprintk(D_CMD, "cmd: %lx:%08x\n",
710 (unsigned long)ptr, *ptr);
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200711 } else {
712 s32 *ptr = dbri->cmdptr;
713
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200714 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200715 ptr++;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200716 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200717 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
718 dprintk(D_CMD, "cmd: %lx:%08x\n",
719 (unsigned long)ptr, *ptr);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200720 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200721#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200722
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200723 /* Reread the last command */
724 tmp = sbus_readl(dbri->regs + REG0);
725 tmp |= D_P;
726 sbus_writel(tmp, dbri->regs + REG0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200727
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200728 dbri->cmdptr = cmd;
729 spin_unlock(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200730}
731
732/* Lock must be held when calling this */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200733static void dbri_reset(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200734{
735 int i;
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200736 u32 tmp;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200737
738 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
739 sbus_readl(dbri->regs + REG0),
740 sbus_readl(dbri->regs + REG2),
741 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
742
743 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
744 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
745 udelay(10);
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200746
747 /* A brute approach - DBRI falls back to working burst size by itself
748 * On SS20 D_S does not work, so do not try so high. */
749 tmp = sbus_readl(dbri->regs + REG0);
750 tmp |= D_G | D_E;
751 tmp &= ~D_S;
752 sbus_writel(tmp, dbri->regs + REG0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200753}
754
755/* Lock must not be held before calling this */
Bill Pemberton32e02a72012-12-06 12:35:25 -0500756static void dbri_initialize(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200757{
Tushar Dave16f46052016-11-24 12:35:16 -0800758 u32 dvma_addr = (u32)dbri->dma_dvma;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200759 s32 *cmd;
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200760 u32 dma_addr;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200761 unsigned long flags;
762 int n;
763
764 spin_lock_irqsave(&dbri->lock, flags);
765
766 dbri_reset(dbri);
767
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200768 /* Initialize pipes */
769 for (n = 0; n < DBRI_NO_PIPES; n++)
770 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
771
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200772 spin_lock_init(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200773 /*
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200774 * Initialize the interrupt ring buffer.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200775 */
Tushar Dave16f46052016-11-24 12:35:16 -0800776 dma_addr = dvma_addr + dbri_dma_off(intr, 0);
Krzysztof Helt6fb98282006-08-16 12:54:29 +0200777 dbri->dma->intr[0] = dma_addr;
778 dbri->dbri_irqp = 1;
779 /*
780 * Set up the interrupt queue
781 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200782 spin_lock(&dbri->cmdlock);
783 cmd = dbri->cmdptr = dbri->dma->cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200784 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
785 *(cmd++) = dma_addr;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200786 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
787 dbri->cmdptr = cmd;
788 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
789 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
Tushar Dave16f46052016-11-24 12:35:16 -0800790 dma_addr = dvma_addr + dbri_dma_off(cmd, 0);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200791 sbus_writel(dma_addr, dbri->regs + REG8);
792 spin_unlock(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200793
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200794 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Heltea543f12006-09-05 20:25:05 +0200795 dbri_cmdwait(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200796}
797
798/*
799****************************************************************************
800************************** DBRI data pipe management ***********************
801****************************************************************************
802
803While DBRI control functions use the command and interrupt buffers, the
804main data path takes the form of data pipes, which can be short (command
805and interrupt driven), or long (attached to DMA buffers). These functions
806provide a rudimentary means of setting up and managing the DBRI's pipes,
807but the calling functions have to make sure they respect the pipes' linked
808list ordering, among other things. The transmit and receive functions
809here interface closely with the transmit and receive interrupt code.
810
811*/
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200812static inline int pipe_active(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200813{
814 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
815}
816
817/* reset_pipe(dbri, pipe)
818 *
819 * Called on an in-use pipe to clear anything being transmitted or received
820 * Lock must be held before calling this.
821 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200822static void reset_pipe(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200823{
824 int sdp;
825 int desc;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200826 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200827
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200828 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200829 printk(KERN_ERR "DBRI: reset_pipe called with "
830 "illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200831 return;
832 }
833
834 sdp = dbri->pipes[pipe].sdp;
835 if (sdp == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200836 printk(KERN_ERR "DBRI: reset_pipe called "
837 "on uninitialized pipe\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200838 return;
839 }
840
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200841 cmd = dbri_cmdlock(dbri, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200842 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
843 *(cmd++) = 0;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200844 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
845 dbri_cmdsend(dbri, cmd, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200846
847 desc = dbri->pipes[pipe].first_desc;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200848 if (desc >= 0)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200849 do {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200850 dbri->dma->desc[desc].ba = 0;
851 dbri->dma->desc[desc].nda = 0;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200852 desc = dbri->next_desc[desc];
853 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200854
855 dbri->pipes[pipe].desc = -1;
856 dbri->pipes[pipe].first_desc = -1;
857}
858
Krzysztof Heltea543f12006-09-05 20:25:05 +0200859/*
860 * Lock must be held before calling this.
861 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200862static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200863{
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200864 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200865 printk(KERN_ERR "DBRI: setup_pipe called "
866 "with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200867 return;
868 }
869
870 if ((sdp & 0xf800) != sdp) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200871 printk(KERN_ERR "DBRI: setup_pipe called "
872 "with strange SDP value\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200873 /* sdp &= 0xf800; */
874 }
875
876 /* If this is a fixed receive pipe, arrange for an interrupt
877 * every time its data changes
878 */
879 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
880 sdp |= D_SDP_CHANGE;
881
882 sdp |= D_PIPE(pipe);
883 dbri->pipes[pipe].sdp = sdp;
884 dbri->pipes[pipe].desc = -1;
885 dbri->pipes[pipe].first_desc = -1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200886
887 reset_pipe(dbri, pipe);
888}
889
Krzysztof Heltea543f12006-09-05 20:25:05 +0200890/*
891 * Lock must be held before calling this.
892 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200893static void link_time_slot(struct snd_dbri *dbri, int pipe,
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200894 int prevpipe, int nextpipe,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200895 int length, int cycle)
896{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200897 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200898 int val;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200899
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200900 if (pipe < 0 || pipe > DBRI_MAX_PIPE
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200901 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
902 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200903 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +0200904 "DBRI: link_time_slot called with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200905 return;
906 }
907
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200908 if (dbri->pipes[pipe].sdp == 0
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200909 || dbri->pipes[prevpipe].sdp == 0
910 || dbri->pipes[nextpipe].sdp == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200911 printk(KERN_ERR "DBRI: link_time_slot called "
912 "on uninitialized pipe\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200913 return;
914 }
915
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200916 dbri->pipes[prevpipe].nextpipe = pipe;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200917 dbri->pipes[pipe].nextpipe = nextpipe;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200918 dbri->pipes[pipe].length = length;
919
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200920 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200921
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200922 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
923 /* Deal with CHI special case:
924 * "If transmission on edges 0 or 1 is desired, then cycle n
925 * (where n = # of bit times per frame...) must be used."
926 * - DBRI data sheet, page 11
927 */
928 if (prevpipe == 16 && cycle == 0)
929 cycle = dbri->chi_bpf;
930
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200931 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
932 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
933 *(cmd++) = 0;
934 *(cmd++) =
935 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200936 } else {
937 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
938 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
939 *(cmd++) =
940 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
941 *(cmd++) = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200942 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200943 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200944
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200945 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200946}
947
Krzysztof Heltea543f12006-09-05 20:25:05 +0200948#if 0
949/*
950 * Lock must be held before calling this.
951 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200952static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200953 enum in_or_out direction, int prevpipe,
954 int nextpipe)
955{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200956 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200957 int val;
958
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200959 if (pipe < 0 || pipe > DBRI_MAX_PIPE
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200960 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
961 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200962 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +0200963 "DBRI: unlink_time_slot called with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200964 return;
965 }
966
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200967 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200968
969 if (direction == PIPEinput) {
970 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
971 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
972 *(cmd++) = D_TS_NEXT(nextpipe);
973 *(cmd++) = 0;
974 } else {
975 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
976 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
977 *(cmd++) = 0;
978 *(cmd++) = D_TS_NEXT(nextpipe);
979 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200980 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200981
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200982 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200983}
Krzysztof Heltea543f12006-09-05 20:25:05 +0200984#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200985
986/* xmit_fixed() / recv_fixed()
987 *
988 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
989 * expected to change much, and which we don't need to buffer.
990 * The DBRI only interrupts us when the data changes (receive pipes),
991 * or only changes the data when this function is called (transmit pipes).
992 * Only short pipes (numbers 16-31) can be used in fixed data mode.
993 *
994 * These function operate on a 32-bit field, no matter how large
995 * the actual time slot is. The interrupt handler takes care of bit
996 * ordering and alignment. An 8-bit time slot will always end up
997 * in the low-order 8 bits, filled either MSB-first or LSB-first,
Krzysztof Heltea543f12006-09-05 20:25:05 +0200998 * depending on the settings passed to setup_pipe().
999 *
1000 * Lock must not be held before calling it.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001001 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001002static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001003{
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001004 s32 *cmd;
Krzysztof Heltea543f12006-09-05 20:25:05 +02001005 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001006
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001007 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
Martin Habets43388292005-09-10 15:39:00 +02001008 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001009 return;
1010 }
1011
1012 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001013 printk(KERN_ERR "DBRI: xmit_fixed: "
1014 "Uninitialized pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001015 return;
1016 }
1017
1018 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
Martin Habets43388292005-09-10 15:39:00 +02001019 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001020 return;
1021 }
1022
1023 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001024 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1025 pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001026 return;
1027 }
1028
1029 /* DBRI short pipes always transmit LSB first */
1030
1031 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1032 data = reverse_bytes(data, dbri->pipes[pipe].length);
1033
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001034 cmd = dbri_cmdlock(dbri, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001035
1036 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1037 *(cmd++) = data;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001038 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001039
Krzysztof Heltea543f12006-09-05 20:25:05 +02001040 spin_lock_irqsave(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001041 dbri_cmdsend(dbri, cmd, 3);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001042 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001043 dbri_cmdwait(dbri);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001044
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001045}
1046
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001047static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001048{
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001049 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001050 printk(KERN_ERR "DBRI: recv_fixed called with "
1051 "illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001052 return;
1053 }
1054
1055 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001056 printk(KERN_ERR "DBRI: recv_fixed called on "
1057 "non-fixed pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001058 return;
1059 }
1060
1061 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001062 printk(KERN_ERR "DBRI: recv_fixed called on "
1063 "transmit pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001064 return;
1065 }
1066
1067 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1068}
1069
1070/* setup_descs()
1071 *
1072 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1073 * with a DMA buffer.
1074 *
1075 * Only pipe numbers 0-15 can be used in this mode.
1076 *
1077 * This function takes a stream number pointing to a data buffer,
1078 * and work by building chains of descriptors which identify the
1079 * data buffers. Buffers too large for a single descriptor will
1080 * be spread across multiple descriptors.
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001081 *
1082 * All descriptors create a ring buffer.
Krzysztof Heltea543f12006-09-05 20:25:05 +02001083 *
1084 * Lock must be held before calling this.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001085 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001086static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001087{
Takashi Iwai475675d2005-11-17 15:11:51 +01001088 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
Tushar Dave16f46052016-11-24 12:35:16 -08001089 u32 dvma_addr = (u32)dbri->dma_dvma;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001090 __u32 dvma_buffer;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001091 int desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001092 int len;
1093 int first_desc = -1;
1094 int last_desc = -1;
1095
1096 if (info->pipe < 0 || info->pipe > 15) {
Martin Habets43388292005-09-10 15:39:00 +02001097 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001098 return -2;
1099 }
1100
1101 if (dbri->pipes[info->pipe].sdp == 0) {
Martin Habets43388292005-09-10 15:39:00 +02001102 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001103 info->pipe);
1104 return -2;
1105 }
1106
1107 dvma_buffer = info->dvma_buffer;
1108 len = info->size;
1109
1110 if (streamno == DBRI_PLAY) {
1111 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001112 printk(KERN_ERR "DBRI: setup_descs: "
1113 "Called on receive pipe %d\n", info->pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001114 return -2;
1115 }
1116 } else {
1117 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001118 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +02001119 "DBRI: setup_descs: Called on transmit pipe %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001120 info->pipe);
1121 return -2;
1122 }
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001123 /* Should be able to queue multiple buffers
1124 * to receive on a pipe
1125 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001126 if (pipe_active(dbri, info->pipe)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001127 printk(KERN_ERR "DBRI: recv_on_pipe: "
1128 "Called on active pipe %d\n", info->pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001129 return -2;
1130 }
1131
1132 /* Make sure buffer size is multiple of four */
1133 len &= ~3;
1134 }
1135
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001136 /* Free descriptors if pipe has any */
1137 desc = dbri->pipes[info->pipe].first_desc;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001138 if (desc >= 0)
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001139 do {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001140 dbri->dma->desc[desc].ba = 0;
1141 dbri->dma->desc[desc].nda = 0;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001142 desc = dbri->next_desc[desc];
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001143 } while (desc != -1 &&
1144 desc != dbri->pipes[info->pipe].first_desc);
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001145
1146 dbri->pipes[info->pipe].desc = -1;
1147 dbri->pipes[info->pipe].first_desc = -1;
1148
1149 desc = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001150 while (len > 0) {
1151 int mylen;
1152
1153 for (; desc < DBRI_NO_DESCS; desc++) {
Krzysztof Heltc2735442006-08-21 19:27:35 +02001154 if (!dbri->dma->desc[desc].ba)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001155 break;
1156 }
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001157
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001158 if (desc == DBRI_NO_DESCS) {
Martin Habets43388292005-09-10 15:39:00 +02001159 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001160 return -1;
1161 }
1162
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001163 if (len > DBRI_TD_MAXCNT)
1164 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1165 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001166 mylen = len;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001167
1168 if (mylen > period)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001169 mylen = period;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001170
Krzysztof Heltc2735442006-08-21 19:27:35 +02001171 dbri->next_desc[desc] = -1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001172 dbri->dma->desc[desc].ba = dvma_buffer;
1173 dbri->dma->desc[desc].nda = 0;
1174
1175 if (streamno == DBRI_PLAY) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001176 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1177 dbri->dma->desc[desc].word4 = 0;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001178 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001179 } else {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001180 dbri->dma->desc[desc].word1 = 0;
1181 dbri->dma->desc[desc].word4 =
1182 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1183 }
1184
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001185 if (first_desc == -1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001186 first_desc = desc;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001187 else {
Krzysztof Heltc2735442006-08-21 19:27:35 +02001188 dbri->next_desc[last_desc] = desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001189 dbri->dma->desc[last_desc].nda =
Tushar Dave16f46052016-11-24 12:35:16 -08001190 dvma_addr + dbri_dma_off(desc, desc);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001191 }
1192
1193 last_desc = desc;
1194 dvma_buffer += mylen;
1195 len -= mylen;
1196 }
1197
1198 if (first_desc == -1 || last_desc == -1) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001199 printk(KERN_ERR "DBRI: setup_descs: "
1200 " Not enough descriptors available\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001201 return -1;
1202 }
1203
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001204 dbri->dma->desc[last_desc].nda =
Tushar Dave16f46052016-11-24 12:35:16 -08001205 dvma_addr + dbri_dma_off(desc, first_desc);
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001206 dbri->next_desc[last_desc] = first_desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001207 dbri->pipes[info->pipe].first_desc = first_desc;
1208 dbri->pipes[info->pipe].desc = first_desc;
1209
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001210#ifdef DBRI_DEBUG
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001211 for (desc = first_desc; desc != -1;) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001212 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1213 desc,
1214 dbri->dma->desc[desc].word1,
1215 dbri->dma->desc[desc].ba,
1216 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001217 desc = dbri->next_desc[desc];
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001218 if (desc == first_desc)
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001219 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001220 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001221#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001222 return 0;
1223}
1224
1225/*
1226****************************************************************************
1227************************** DBRI - CHI interface ****************************
1228****************************************************************************
1229
1230The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1231multiplexed serial interface which the DBRI can operate in either master
1232(give clock/frame sync) or slave (take clock/frame sync) mode.
1233
1234*/
1235
1236enum master_or_slave { CHImaster, CHIslave };
1237
Krzysztof Heltea543f12006-09-05 20:25:05 +02001238/*
1239 * Lock must not be held before calling it.
1240 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001241static void reset_chi(struct snd_dbri *dbri,
1242 enum master_or_slave master_or_slave,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001243 int bits_per_frame)
1244{
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001245 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001246 int val;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001247
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001248 /* Set CHI Anchor: Pipe 16 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001249
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001250 cmd = dbri_cmdlock(dbri, 4);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001251 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001252 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1253 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1254 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1255 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1256 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1257 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001258
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001259 dbri->pipes[16].sdp = 1;
1260 dbri->pipes[16].nextpipe = 16;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001261
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001262 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001263
1264 if (master_or_slave == CHIslave) {
1265 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1266 *
1267 * CHICM = 0 (slave mode, 8 kHz frame rate)
1268 * IR = give immediate CHI status interrupt
1269 * EN = give CHI status interrupt upon change
1270 */
1271 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1272 } else {
1273 /* Setup DBRI for CHI Master - generate clock, FS
1274 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001275 * BPF = bits per 8 kHz frame
1276 * 12.288 MHz / CHICM_divisor = clock rate
1277 * FD = 1 - drive CHIFS on rising edge of CHICK
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001278 */
1279 int clockrate = bits_per_frame * 8;
1280 int divisor = 12288 / clockrate;
1281
1282 if (divisor > 255 || divisor * clockrate != 12288)
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001283 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1284 "in setup_chi\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001285
1286 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1287 | D_CHI_BPF(bits_per_frame));
1288 }
1289
1290 dbri->chi_bpf = bits_per_frame;
1291
1292 /* CHI Data Mode
1293 *
1294 * RCE = 0 - receive on falling edge of CHICK
1295 * XCE = 1 - transmit on rising edge of CHICK
1296 * XEN = 1 - enable transmitter
1297 * REN = 1 - enable receiver
1298 */
1299
1300 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1301 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001302 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001303
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001304 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001305}
1306
1307/*
1308****************************************************************************
1309*********************** CS4215 audio codec management **********************
1310****************************************************************************
1311
1312In the standard SPARC audio configuration, the CS4215 codec is attached
1313to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1314
Krzysztof Heltea543f12006-09-05 20:25:05 +02001315 * Lock must not be held before calling it.
1316
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001317*/
Bill Pemberton32e02a72012-12-06 12:35:25 -05001318static void cs4215_setup_pipes(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001319{
Krzysztof Heltea543f12006-09-05 20:25:05 +02001320 unsigned long flags;
1321
1322 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001323 /*
1324 * Data mode:
1325 * Pipe 4: Send timeslots 1-4 (audio data)
1326 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1327 * Pipe 6: Receive timeslots 1-4 (audio data)
1328 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1329 * interrupt, and the rest of the data (slot 5 and 8) is
1330 * not relevant for us (only for doublechecking).
1331 *
1332 * Control mode:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001333 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001334 * Pipe 18: Receive timeslot 1 (clb).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001335 * Pipe 19: Receive timeslot 7 (version).
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001336 */
1337
1338 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1339 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1340 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1341 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1342
1343 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1344 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1345 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001346 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001347
1348 dbri_cmdwait(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001349}
1350
Bill Pemberton32e02a72012-12-06 12:35:25 -05001351static int cs4215_init_data(struct cs4215 *mm)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001352{
1353 /*
1354 * No action, memory resetting only.
1355 *
1356 * Data Time Slot 5-8
1357 * Speaker,Line and Headphone enable. Gain set to the half.
1358 * Input is mike.
1359 */
1360 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1361 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1362 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1363 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1364
1365 /*
1366 * Control Time Slot 1-4
1367 * 0: Default I/O voltage scale
1368 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1369 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1370 * 3: Tests disabled
1371 */
1372 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1373 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1374 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1375 mm->ctrl[3] = 0;
1376
1377 mm->status = 0;
1378 mm->version = 0xff;
1379 mm->precision = 8; /* For ULAW */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001380 mm->channels = 1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001381
1382 return 0;
1383}
1384
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001385static void cs4215_setdata(struct snd_dbri *dbri, int muted)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001386{
1387 if (muted) {
1388 dbri->mm.data[0] |= 63;
1389 dbri->mm.data[1] |= 63;
1390 dbri->mm.data[2] &= ~15;
1391 dbri->mm.data[3] &= ~15;
1392 } else {
1393 /* Start by setting the playback attenuation. */
Takashi Iwai475675d2005-11-17 15:11:51 +01001394 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001395 int left_gain = info->left_gain & 0x3f;
1396 int right_gain = info->right_gain & 0x3f;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001397
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001398 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1399 dbri->mm.data[1] &= ~0x3f;
1400 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1401 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1402
1403 /* Now set the recording gain. */
1404 info = &dbri->stream_info[DBRI_REC];
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001405 left_gain = info->left_gain & 0xf;
1406 right_gain = info->right_gain & 0xf;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001407 dbri->mm.data[2] |= CS4215_LG(left_gain);
1408 dbri->mm.data[3] |= CS4215_RG(right_gain);
1409 }
1410
1411 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1412}
1413
1414/*
1415 * Set the CS4215 to data mode.
1416 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001417static void cs4215_open(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001418{
1419 int data_width;
1420 u32 tmp;
Krzysztof Heltea543f12006-09-05 20:25:05 +02001421 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001422
1423 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1424 dbri->mm.channels, dbri->mm.precision);
1425
1426 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1427 * to make sure this takes. This avoids clicking noises.
1428 */
1429
1430 cs4215_setdata(dbri, 1);
1431 udelay(125);
1432
1433 /*
1434 * Data mode:
1435 * Pipe 4: Send timeslots 1-4 (audio data)
1436 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1437 * Pipe 6: Receive timeslots 1-4 (audio data)
1438 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1439 * interrupt, and the rest of the data (slot 5 and 8) is
1440 * not relevant for us (only for doublechecking).
1441 *
1442 * Just like in control mode, the time slots are all offset by eight
1443 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1444 * even if it's the CHI master. Don't ask me...
1445 */
Krzysztof Heltea543f12006-09-05 20:25:05 +02001446 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001447 tmp = sbus_readl(dbri->regs + REG0);
1448 tmp &= ~(D_C); /* Disable CHI */
1449 sbus_writel(tmp, dbri->regs + REG0);
1450
1451 /* Switch CS4215 to data mode - set PIO3 to 1 */
1452 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1453 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1454
1455 reset_chi(dbri, CHIslave, 128);
1456
1457 /* Note: this next doesn't work for 8-bit stereo, because the two
1458 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1459 * (See CS4215 datasheet Fig 15)
1460 *
1461 * DBRI non-contiguous mode would be required to make this work.
1462 */
1463 data_width = dbri->mm.channels * dbri->mm.precision;
1464
Krzysztof Helt294a30d2006-08-21 19:29:59 +02001465 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1466 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1467 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1468 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001469
1470 /* FIXME: enable CHI after _setdata? */
1471 tmp = sbus_readl(dbri->regs + REG0);
1472 tmp |= D_C; /* Enable CHI */
1473 sbus_writel(tmp, dbri->regs + REG0);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001474 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001475
1476 cs4215_setdata(dbri, 0);
1477}
1478
1479/*
1480 * Send the control information (i.e. audio format)
1481 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001482static int cs4215_setctrl(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001483{
1484 int i, val;
1485 u32 tmp;
Krzysztof Heltea543f12006-09-05 20:25:05 +02001486 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001487
1488 /* FIXME - let the CPU do something useful during these delays */
1489
1490 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1491 * to make sure this takes. This avoids clicking noises.
1492 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001493 cs4215_setdata(dbri, 1);
1494 udelay(125);
1495
1496 /*
1497 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1498 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1499 */
1500 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1501 sbus_writel(val, dbri->regs + REG2);
1502 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1503 udelay(34);
1504
1505 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1506 * operate as CHI master, supplying clocking and frame synchronization.
1507 *
1508 * In Data mode, however, the CS4215 must be CHI master to insure
1509 * that its data stream is synchronous with its codec.
1510 *
1511 * The upshot of all this? We start by putting the DBRI into master
1512 * mode, program the CS4215 in Control mode, then switch the CS4215
1513 * into Data mode and put the DBRI into slave mode. Various timing
1514 * requirements must be observed along the way.
1515 *
1516 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1517 * others?), the addressing of the CS4215's time slots is
1518 * offset by eight bits, so we add eight to all the "cycle"
1519 * values in the Define Time Slot (DTS) commands. This is
1520 * done in hardware by a TI 248 that delays the DBRI->4215
1521 * frame sync signal by eight clock cycles. Anybody know why?
1522 */
Krzysztof Heltea543f12006-09-05 20:25:05 +02001523 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001524 tmp = sbus_readl(dbri->regs + REG0);
1525 tmp &= ~D_C; /* Disable CHI */
1526 sbus_writel(tmp, dbri->regs + REG0);
1527
1528 reset_chi(dbri, CHImaster, 128);
1529
1530 /*
1531 * Control mode:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001532 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001533 * Pipe 18: Receive timeslot 1 (clb).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001534 * Pipe 19: Receive timeslot 7 (version).
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001535 */
1536
Krzysztof Helt294a30d2006-08-21 19:29:59 +02001537 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1538 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1539 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001540 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001541
1542 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1543 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1544 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1545
Krzysztof Heltea543f12006-09-05 20:25:05 +02001546 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001547 tmp = sbus_readl(dbri->regs + REG0);
1548 tmp |= D_C; /* Enable CHI */
1549 sbus_writel(tmp, dbri->regs + REG0);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001550 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001551
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001552 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
Martin Habets43388292005-09-10 15:39:00 +02001553 msleep_interruptible(1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001554
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001555 if (i == 0) {
1556 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1557 dbri->mm.status);
1558 return -1;
1559 }
1560
1561 /* Disable changes to our copy of the version number, as we are about
1562 * to leave control mode.
1563 */
1564 recv_fixed(dbri, 19, NULL);
1565
1566 /* Terminate CS4215 control mode - data sheet says
1567 * "Set CLB=1 and send two more frames of valid control info"
1568 */
1569 dbri->mm.ctrl[0] |= CS4215_CLB;
1570 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1571
1572 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1573 udelay(250);
1574
1575 cs4215_setdata(dbri, 0);
1576
1577 return 0;
1578}
1579
1580/*
1581 * Setup the codec with the sampling rate, audio format and number of
1582 * channels.
1583 * As part of the process we resend the settings for the data
1584 * timeslots as well.
1585 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001586static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001587 snd_pcm_format_t format, unsigned int channels)
1588{
1589 int freq_idx;
1590 int ret = 0;
1591
1592 /* Lookup index for this rate */
1593 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1594 if (CS4215_FREQ[freq_idx].freq == rate)
1595 break;
1596 }
1597 if (CS4215_FREQ[freq_idx].freq != rate) {
1598 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1599 return -1;
1600 }
1601
1602 switch (format) {
1603 case SNDRV_PCM_FORMAT_MU_LAW:
1604 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1605 dbri->mm.precision = 8;
1606 break;
1607 case SNDRV_PCM_FORMAT_A_LAW:
1608 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1609 dbri->mm.precision = 8;
1610 break;
1611 case SNDRV_PCM_FORMAT_U8:
1612 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1613 dbri->mm.precision = 8;
1614 break;
1615 case SNDRV_PCM_FORMAT_S16_BE:
1616 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1617 dbri->mm.precision = 16;
1618 break;
1619 default:
1620 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1621 return -1;
1622 }
1623
1624 /* Add rate parameters */
1625 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1626 dbri->mm.ctrl[2] = CS4215_XCLK |
1627 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1628
1629 dbri->mm.channels = channels;
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001630 if (channels == 2)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001631 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1632
1633 ret = cs4215_setctrl(dbri);
1634 if (ret == 0)
1635 cs4215_open(dbri); /* set codec to data mode */
1636
1637 return ret;
1638}
1639
1640/*
1641 *
1642 */
Bill Pemberton32e02a72012-12-06 12:35:25 -05001643static int cs4215_init(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001644{
1645 u32 reg2 = sbus_readl(dbri->regs + REG2);
1646 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1647
1648 /* Look for the cs4215 chips */
1649 if (reg2 & D_PIO2) {
1650 dprintk(D_MM, "Onboard CS4215 detected\n");
1651 dbri->mm.onboard = 1;
1652 }
1653 if (reg2 & D_PIO0) {
1654 dprintk(D_MM, "Speakerbox detected\n");
1655 dbri->mm.onboard = 0;
1656
1657 if (reg2 & D_PIO2) {
1658 printk(KERN_INFO "DBRI: Using speakerbox / "
1659 "ignoring onboard mmcodec.\n");
1660 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1661 }
1662 }
1663
1664 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1665 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1666 return -EIO;
1667 }
1668
1669 cs4215_setup_pipes(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001670 cs4215_init_data(&dbri->mm);
1671
1672 /* Enable capture of the status & version timeslots. */
1673 recv_fixed(dbri, 18, &dbri->mm.status);
1674 recv_fixed(dbri, 19, &dbri->mm.version);
1675
1676 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1677 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1678 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1679 dbri->mm.offset);
1680 return -EIO;
1681 }
1682 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1683
1684 return 0;
1685}
1686
1687/*
1688****************************************************************************
1689*************************** DBRI interrupt handler *************************
1690****************************************************************************
1691
1692The DBRI communicates with the CPU mainly via a circular interrupt
1693buffer. When an interrupt is signaled, the CPU walks through the
1694buffer and calls dbri_process_one_interrupt() for each interrupt word.
1695Complicated interrupts are handled by dedicated functions (which
1696appear first in this file). Any pending interrupts can be serviced by
1697calling dbri_process_interrupt_buffer(), which works even if the CPU's
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001698interrupts are disabled.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001699
1700*/
1701
1702/* xmit_descs()
1703 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001704 * Starts transmitting the current TD's for recording/playing.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001705 * For playback, ALSA has filled the DMA memory with new data (we hope).
1706 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001707static void xmit_descs(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001708{
Takashi Iwai475675d2005-11-17 15:11:51 +01001709 struct dbri_streaminfo *info;
Dan Carpenter163117e2016-12-01 08:48:30 +03001710 u32 dvma_addr;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001711 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001712 unsigned long flags;
1713 int first_td;
1714
1715 if (dbri == NULL)
1716 return; /* Disabled */
1717
Dan Carpenter163117e2016-12-01 08:48:30 +03001718 dvma_addr = (u32)dbri->dma_dvma;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001719 info = &dbri->stream_info[DBRI_REC];
1720 spin_lock_irqsave(&dbri->lock, flags);
1721
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001722 if (info->pipe >= 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001723 first_td = dbri->pipes[info->pipe].first_desc;
1724
1725 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1726
1727 /* Stream could be closed by the time we run. */
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001728 if (first_td >= 0) {
1729 cmd = dbri_cmdlock(dbri, 2);
1730 *(cmd++) = DBRI_CMD(D_SDP, 0,
1731 dbri->pipes[info->pipe].sdp
1732 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
Tushar Dave16f46052016-11-24 12:35:16 -08001733 *(cmd++) = dvma_addr +
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001734 dbri_dma_off(desc, first_td);
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001735 dbri_cmdsend(dbri, cmd, 2);
1736
1737 /* Reset our admin of the pipe. */
1738 dbri->pipes[info->pipe].desc = first_td;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001739 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001740 }
1741
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001742 info = &dbri->stream_info[DBRI_PLAY];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001743
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001744 if (info->pipe >= 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001745 first_td = dbri->pipes[info->pipe].first_desc;
1746
1747 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1748
1749 /* Stream could be closed by the time we run. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001750 if (first_td >= 0) {
1751 cmd = dbri_cmdlock(dbri, 2);
1752 *(cmd++) = DBRI_CMD(D_SDP, 0,
1753 dbri->pipes[info->pipe].sdp
1754 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
Tushar Dave16f46052016-11-24 12:35:16 -08001755 *(cmd++) = dvma_addr +
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001756 dbri_dma_off(desc, first_td);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001757 dbri_cmdsend(dbri, cmd, 2);
1758
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001759 /* Reset our admin of the pipe. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001760 dbri->pipes[info->pipe].desc = first_td;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001761 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001762 }
Krzysztof Heltea543f12006-09-05 20:25:05 +02001763
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001764 spin_unlock_irqrestore(&dbri->lock, flags);
1765}
1766
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001767/* transmission_complete_intr()
1768 *
1769 * Called by main interrupt handler when DBRI signals transmission complete
1770 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1771 *
Martin Habets43388292005-09-10 15:39:00 +02001772 * Walks through the pipe's list of transmit buffer descriptors and marks
1773 * them as available. Stops when the first descriptor is found without
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001774 * TBC (Transmit Buffer Complete) set, or we've run through them all.
Martin Habets43388292005-09-10 15:39:00 +02001775 *
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001776 * The DMA buffers are not released. They form a ring buffer and
1777 * they are filled by ALSA while others are transmitted by DMA.
1778 *
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001779 */
1780
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001781static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001782{
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001783 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1784 int td = dbri->pipes[pipe].desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001785 int status;
1786
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001787 while (td >= 0) {
1788 if (td >= DBRI_NO_DESCS) {
1789 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1790 return;
1791 }
1792
1793 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001794 if (!(status & DBRI_TD_TBC))
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001795 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001796
1797 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1798
1799 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001800 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001801
Krzysztof Heltc2735442006-08-21 19:27:35 +02001802 td = dbri->next_desc[td];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001803 dbri->pipes[pipe].desc = td;
1804 }
1805
1806 /* Notify ALSA */
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001807 spin_unlock(&dbri->lock);
1808 snd_pcm_period_elapsed(info->substream);
1809 spin_lock(&dbri->lock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001810}
1811
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001812static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001813{
Takashi Iwai475675d2005-11-17 15:11:51 +01001814 struct dbri_streaminfo *info;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001815 int rd = dbri->pipes[pipe].desc;
1816 s32 status;
1817
1818 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1819 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1820 return;
1821 }
1822
Krzysztof Heltc2735442006-08-21 19:27:35 +02001823 dbri->pipes[pipe].desc = dbri->next_desc[rd];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001824 status = dbri->dma->desc[rd].word1;
1825 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1826
1827 info = &dbri->stream_info[DBRI_REC];
1828 info->offset += DBRI_RD_CNT(status);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001829
1830 /* FIXME: Check status */
1831
1832 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1833 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1834
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001835 /* Notify ALSA */
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001836 spin_unlock(&dbri->lock);
1837 snd_pcm_period_elapsed(info->substream);
1838 spin_lock(&dbri->lock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001839}
1840
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001841static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001842{
1843 int val = D_INTR_GETVAL(x);
1844 int channel = D_INTR_GETCHAN(x);
1845 int command = D_INTR_GETCMD(x);
1846 int code = D_INTR_GETCODE(x);
1847#ifdef DBRI_DEBUG
1848 int rval = D_INTR_GETRVAL(x);
1849#endif
1850
1851 if (channel == D_INTR_CMD) {
1852 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1853 cmds[command], val);
1854 } else {
1855 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1856 channel, code, rval);
1857 }
1858
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001859 switch (code) {
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001860 case D_INTR_CMDI:
1861 if (command != D_WAIT)
1862 printk(KERN_ERR "DBRI: Command read interrupt\n");
1863 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001864 case D_INTR_BRDY:
1865 reception_complete_intr(dbri, channel);
1866 break;
1867 case D_INTR_XCMP:
1868 case D_INTR_MINT:
1869 transmission_complete_intr(dbri, channel);
1870 break;
1871 case D_INTR_UNDR:
1872 /* UNDR - Transmission underrun
1873 * resend SDP command with clear pipe bit (C) set
1874 */
1875 {
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001876 /* FIXME: do something useful in case of underrun */
1877 printk(KERN_ERR "DBRI: Underrun error\n");
1878#if 0
1879 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001880 int pipe = channel;
1881 int td = dbri->pipes[pipe].desc;
1882
1883 dbri->dma->desc[td].word4 = 0;
1884 cmd = dbri_cmdlock(dbri, NoGetLock);
1885 *(cmd++) = DBRI_CMD(D_SDP, 0,
1886 dbri->pipes[pipe].sdp
1887 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1888 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1889 dbri_cmdsend(dbri, cmd);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001890#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001891 }
1892 break;
1893 case D_INTR_FXDT:
1894 /* FXDT - Fixed data change */
1895 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1896 val = reverse_bytes(val, dbri->pipes[channel].length);
1897
1898 if (dbri->pipes[channel].recv_fixed_ptr)
1899 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1900 break;
1901 default:
1902 if (channel != D_INTR_CMD)
1903 printk(KERN_WARNING
1904 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1905 }
1906}
1907
1908/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1909 * buffer until it finds a zero word (indicating nothing more to do
1910 * right now). Non-zero words require processing and are handed off
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001911 * to dbri_process_one_interrupt AFTER advancing the pointer.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001912 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001913static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001914{
1915 s32 x;
1916
1917 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1918 dbri->dma->intr[dbri->dbri_irqp] = 0;
1919 dbri->dbri_irqp++;
Krzysztof Helt6fb98282006-08-16 12:54:29 +02001920 if (dbri->dbri_irqp == DBRI_INT_BLK)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001921 dbri->dbri_irqp = 1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001922
1923 dbri_process_one_interrupt(dbri, x);
1924 }
1925}
1926
David Howells7d12e782006-10-05 14:55:46 +01001927static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001928{
Takashi Iwai475675d2005-11-17 15:11:51 +01001929 struct snd_dbri *dbri = dev_id;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001930 static int errcnt = 0;
1931 int x;
1932
1933 if (dbri == NULL)
1934 return IRQ_NONE;
1935 spin_lock(&dbri->lock);
1936
1937 /*
1938 * Read it, so the interrupt goes away.
1939 */
1940 x = sbus_readl(dbri->regs + REG1);
1941
1942 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1943 u32 tmp;
1944
1945 if (x & D_MRR)
1946 printk(KERN_ERR
1947 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1948 x);
1949 if (x & D_MLE)
1950 printk(KERN_ERR
1951 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1952 x);
1953 if (x & D_LBG)
1954 printk(KERN_ERR
1955 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1956 if (x & D_MBE)
1957 printk(KERN_ERR
1958 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1959
1960 /* Some of these SBus errors cause the chip's SBus circuitry
1961 * to be disabled, so just re-enable and try to keep going.
1962 *
1963 * The only one I've seen is MRR, which will be triggered
1964 * if you let a transmit pipe underrun, then try to CDP it.
1965 *
Martin Habets43388292005-09-10 15:39:00 +02001966 * If these things persist, we reset the chip.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001967 */
1968 if ((++errcnt) % 10 == 0) {
1969 dprintk(D_INT, "Interrupt errors exceeded.\n");
1970 dbri_reset(dbri);
1971 } else {
1972 tmp = sbus_readl(dbri->regs + REG0);
1973 tmp &= ~(D_D);
1974 sbus_writel(tmp, dbri->regs + REG0);
1975 }
1976 }
1977
1978 dbri_process_interrupt_buffer(dbri);
1979
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001980 spin_unlock(&dbri->lock);
1981
1982 return IRQ_HANDLED;
1983}
1984
1985/****************************************************************************
1986 PCM Interface
1987****************************************************************************/
Bhumika Goyal688ed202017-08-17 14:45:58 +05301988static const struct snd_pcm_hardware snd_dbri_pcm_hw = {
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001989 .info = SNDRV_PCM_INFO_MMAP |
1990 SNDRV_PCM_INFO_INTERLEAVED |
1991 SNDRV_PCM_INFO_BLOCK_TRANSFER |
Takashi Iwai2008f132009-04-28 12:25:59 +02001992 SNDRV_PCM_INFO_MMAP_VALID |
1993 SNDRV_PCM_INFO_BATCH,
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001994 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1995 SNDRV_PCM_FMTBIT_A_LAW |
1996 SNDRV_PCM_FMTBIT_U8 |
1997 SNDRV_PCM_FMTBIT_S16_BE,
1998 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001999 .rate_min = 5512,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002000 .rate_max = 48000,
2001 .channels_min = 1,
2002 .channels_max = 2,
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002003 .buffer_bytes_max = 64 * 1024,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002004 .period_bytes_min = 1,
2005 .period_bytes_max = DBRI_TD_MAXCNT,
2006 .periods_min = 1,
2007 .periods_max = 1024,
2008};
2009
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002010static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
2011 struct snd_pcm_hw_rule *rule)
2012{
2013 struct snd_interval *c = hw_param_interval(params,
2014 SNDRV_PCM_HW_PARAM_CHANNELS);
2015 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2016 struct snd_mask fmt;
2017
2018 snd_mask_any(&fmt);
2019 if (c->min > 1) {
2020 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2021 return snd_mask_refine(f, &fmt);
2022 }
2023 return 0;
2024}
2025
2026static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2027 struct snd_pcm_hw_rule *rule)
2028{
2029 struct snd_interval *c = hw_param_interval(params,
2030 SNDRV_PCM_HW_PARAM_CHANNELS);
2031 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2032 struct snd_interval ch;
2033
2034 snd_interval_any(&ch);
2035 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002036 ch.min = 1;
2037 ch.max = 1;
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002038 ch.integer = 1;
2039 return snd_interval_refine(c, &ch);
2040 }
2041 return 0;
2042}
2043
Takashi Iwai475675d2005-11-17 15:11:51 +01002044static int snd_dbri_open(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002045{
Takashi Iwai475675d2005-11-17 15:11:51 +01002046 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2047 struct snd_pcm_runtime *runtime = substream->runtime;
2048 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002049 unsigned long flags;
2050
2051 dprintk(D_USR, "open audio output.\n");
2052 runtime->hw = snd_dbri_pcm_hw;
2053
2054 spin_lock_irqsave(&dbri->lock, flags);
2055 info->substream = substream;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002056 info->offset = 0;
2057 info->dvma_buffer = 0;
2058 info->pipe = -1;
2059 spin_unlock_irqrestore(&dbri->lock, flags);
2060
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002061 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
Al Viroae97dd92006-09-24 23:42:57 +01002062 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002063 -1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002064 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2065 snd_hw_rule_channels, NULL,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002066 SNDRV_PCM_HW_PARAM_CHANNELS,
2067 -1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002068
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002069 cs4215_open(dbri);
2070
2071 return 0;
2072}
2073
Takashi Iwai475675d2005-11-17 15:11:51 +01002074static int snd_dbri_close(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002075{
Takashi Iwai475675d2005-11-17 15:11:51 +01002076 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2077 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002078
2079 dprintk(D_USR, "close audio output.\n");
2080 info->substream = NULL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002081 info->offset = 0;
2082
2083 return 0;
2084}
2085
Takashi Iwai475675d2005-11-17 15:11:51 +01002086static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2087 struct snd_pcm_hw_params *hw_params)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002088{
Takashi Iwai475675d2005-11-17 15:11:51 +01002089 struct snd_pcm_runtime *runtime = substream->runtime;
2090 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2091 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002092 int direction;
2093 int ret;
2094
2095 /* set sampling rate, audio format and number of channels */
2096 ret = cs4215_prepare(dbri, params_rate(hw_params),
2097 params_format(hw_params),
2098 params_channels(hw_params));
2099 if (ret != 0)
2100 return ret;
2101
2102 if ((ret = snd_pcm_lib_malloc_pages(substream,
2103 params_buffer_bytes(hw_params))) < 0) {
Martin Habets43388292005-09-10 15:39:00 +02002104 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002105 return ret;
2106 }
2107
2108 /* hw_params can get called multiple times. Only map the DMA once.
2109 */
2110 if (info->dvma_buffer == 0) {
2111 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
David S. Miller738f2b72008-08-27 18:09:11 -07002112 direction = DMA_TO_DEVICE;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002113 else
David S. Miller738f2b72008-08-27 18:09:11 -07002114 direction = DMA_FROM_DEVICE;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002115
David S. Miller7a715f42008-08-27 18:37:58 -07002116 info->dvma_buffer =
David S. Miller2bd320f2008-08-27 00:30:59 -07002117 dma_map_single(&dbri->op->dev,
David S. Miller738f2b72008-08-27 18:09:11 -07002118 runtime->dma_area,
2119 params_buffer_bytes(hw_params),
2120 direction);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002121 }
2122
2123 direction = params_buffer_bytes(hw_params);
2124 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2125 direction, info->dvma_buffer);
2126 return 0;
2127}
2128
Takashi Iwai475675d2005-11-17 15:11:51 +01002129static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002130{
Takashi Iwai475675d2005-11-17 15:11:51 +01002131 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2132 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002133 int direction;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02002134
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002135 dprintk(D_USR, "hw_free.\n");
2136
2137 /* hw_free can get called multiple times. Only unmap the DMA once.
2138 */
2139 if (info->dvma_buffer) {
2140 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
David S. Miller738f2b72008-08-27 18:09:11 -07002141 direction = DMA_TO_DEVICE;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002142 else
David S. Miller738f2b72008-08-27 18:09:11 -07002143 direction = DMA_FROM_DEVICE;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002144
David S. Miller2bd320f2008-08-27 00:30:59 -07002145 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
David S. Miller738f2b72008-08-27 18:09:11 -07002146 substream->runtime->buffer_size, direction);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002147 info->dvma_buffer = 0;
2148 }
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02002149 if (info->pipe != -1) {
2150 reset_pipe(dbri, info->pipe);
2151 info->pipe = -1;
2152 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002153
2154 return snd_pcm_lib_free_pages(substream);
2155}
2156
Takashi Iwai475675d2005-11-17 15:11:51 +01002157static int snd_dbri_prepare(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002158{
Takashi Iwai475675d2005-11-17 15:11:51 +01002159 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2160 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002161 int ret;
2162
2163 info->size = snd_pcm_lib_buffer_bytes(substream);
2164 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2165 info->pipe = 4; /* Send pipe */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002166 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002167 info->pipe = 6; /* Receive pipe */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002168
2169 spin_lock_irq(&dbri->lock);
Krzysztof Heltaaad3652006-08-28 12:59:23 +02002170 info->offset = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002171
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002172 /* Setup the all the transmit/receive descriptors to cover the
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002173 * whole DMA buffer.
2174 */
2175 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2176 snd_pcm_lib_period_bytes(substream));
2177
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002178 spin_unlock_irq(&dbri->lock);
2179
2180 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2181 return ret;
2182}
2183
Takashi Iwai475675d2005-11-17 15:11:51 +01002184static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002185{
Takashi Iwai475675d2005-11-17 15:11:51 +01002186 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2187 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002188 int ret = 0;
2189
2190 switch (cmd) {
2191 case SNDRV_PCM_TRIGGER_START:
2192 dprintk(D_USR, "start audio, period is %d bytes\n",
2193 (int)snd_pcm_lib_period_bytes(substream));
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002194 /* Re-submit the TDs. */
2195 xmit_descs(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002196 break;
2197 case SNDRV_PCM_TRIGGER_STOP:
2198 dprintk(D_USR, "stop audio.\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002199 reset_pipe(dbri, info->pipe);
2200 break;
2201 default:
2202 ret = -EINVAL;
2203 }
2204
2205 return ret;
2206}
2207
Takashi Iwai475675d2005-11-17 15:11:51 +01002208static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002209{
Takashi Iwai475675d2005-11-17 15:11:51 +01002210 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2211 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002212 snd_pcm_uframes_t ret;
2213
2214 ret = bytes_to_frames(substream->runtime, info->offset)
2215 % substream->runtime->buffer_size;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002216 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2217 ret, substream->runtime->buffer_size);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002218 return ret;
2219}
2220
Arvind Yadav544d6272017-08-18 13:15:19 +05302221static const struct snd_pcm_ops snd_dbri_ops = {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002222 .open = snd_dbri_open,
2223 .close = snd_dbri_close,
2224 .ioctl = snd_pcm_lib_ioctl,
2225 .hw_params = snd_dbri_hw_params,
2226 .hw_free = snd_dbri_hw_free,
2227 .prepare = snd_dbri_prepare,
2228 .trigger = snd_dbri_trigger,
2229 .pointer = snd_dbri_pointer,
2230};
2231
Bill Pemberton32e02a72012-12-06 12:35:25 -05002232static int snd_dbri_pcm(struct snd_card *card)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002233{
Takashi Iwai475675d2005-11-17 15:11:51 +01002234 struct snd_pcm *pcm;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002235 int err;
2236
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002237 if ((err = snd_pcm_new(card,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002238 /* ID */ "sun_dbri",
2239 /* device */ 0,
2240 /* playback count */ 1,
2241 /* capture count */ 1, &pcm)) < 0)
2242 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002243
2244 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2245 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2246
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002247 pcm->private_data = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002248 pcm->info_flags = 0;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002249 strcpy(pcm->name, card->shortname);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002250
Takashi Iwai1267e242019-02-04 16:35:48 +01002251 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
Takashi Iwai0382e4e2019-11-05 16:18:37 +01002252 NULL,
Takashi Iwai1267e242019-02-04 16:35:48 +01002253 64 * 1024, 64 * 1024);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002254 return 0;
2255}
2256
2257/*****************************************************************************
2258 Mixer interface
2259*****************************************************************************/
2260
Takashi Iwai475675d2005-11-17 15:11:51 +01002261static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2262 struct snd_ctl_elem_info *uinfo)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002263{
2264 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2265 uinfo->count = 2;
2266 uinfo->value.integer.min = 0;
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002267 if (kcontrol->private_value == DBRI_PLAY)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002268 uinfo->value.integer.max = DBRI_MAX_VOLUME;
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002269 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002270 uinfo->value.integer.max = DBRI_MAX_GAIN;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002271 return 0;
2272}
2273
Takashi Iwai475675d2005-11-17 15:11:51 +01002274static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2275 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002276{
Takashi Iwai475675d2005-11-17 15:11:51 +01002277 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2278 struct dbri_streaminfo *info;
Takashi Iwai5e246b82008-08-08 17:12:47 +02002279
2280 if (snd_BUG_ON(!dbri))
2281 return -EINVAL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002282 info = &dbri->stream_info[kcontrol->private_value];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002283
2284 ucontrol->value.integer.value[0] = info->left_gain;
2285 ucontrol->value.integer.value[1] = info->right_gain;
2286 return 0;
2287}
2288
Takashi Iwai475675d2005-11-17 15:11:51 +01002289static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2290 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002291{
Takashi Iwai475675d2005-11-17 15:11:51 +01002292 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002293 struct dbri_streaminfo *info =
2294 &dbri->stream_info[kcontrol->private_value];
Takashi Iwai3b89246772007-11-15 16:17:24 +01002295 unsigned int vol[2];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002296 int changed = 0;
2297
Takashi Iwai3b89246772007-11-15 16:17:24 +01002298 vol[0] = ucontrol->value.integer.value[0];
2299 vol[1] = ucontrol->value.integer.value[1];
2300 if (kcontrol->private_value == DBRI_PLAY) {
2301 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2302 return -EINVAL;
2303 } else {
2304 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2305 return -EINVAL;
2306 }
2307
Takashi Iwai4581aa32007-11-20 18:31:22 +01002308 if (info->left_gain != vol[0]) {
2309 info->left_gain = vol[0];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002310 changed = 1;
2311 }
Takashi Iwai4581aa32007-11-20 18:31:22 +01002312 if (info->right_gain != vol[1]) {
2313 info->right_gain = vol[1];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002314 changed = 1;
2315 }
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002316 if (changed) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002317 /* First mute outputs, and wait 1/8000 sec (125 us)
2318 * to make sure this takes. This avoids clicking noises.
2319 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002320 cs4215_setdata(dbri, 1);
2321 udelay(125);
2322 cs4215_setdata(dbri, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002323 }
2324 return changed;
2325}
2326
Takashi Iwai475675d2005-11-17 15:11:51 +01002327static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2328 struct snd_ctl_elem_info *uinfo)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002329{
2330 int mask = (kcontrol->private_value >> 16) & 0xff;
2331
2332 uinfo->type = (mask == 1) ?
2333 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2334 uinfo->count = 1;
2335 uinfo->value.integer.min = 0;
2336 uinfo->value.integer.max = mask;
2337 return 0;
2338}
2339
Takashi Iwai475675d2005-11-17 15:11:51 +01002340static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2341 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002342{
Takashi Iwai475675d2005-11-17 15:11:51 +01002343 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002344 int elem = kcontrol->private_value & 0xff;
2345 int shift = (kcontrol->private_value >> 8) & 0xff;
2346 int mask = (kcontrol->private_value >> 16) & 0xff;
2347 int invert = (kcontrol->private_value >> 24) & 1;
Takashi Iwai5e246b82008-08-08 17:12:47 +02002348
2349 if (snd_BUG_ON(!dbri))
2350 return -EINVAL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002351
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002352 if (elem < 4)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002353 ucontrol->value.integer.value[0] =
2354 (dbri->mm.data[elem] >> shift) & mask;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002355 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002356 ucontrol->value.integer.value[0] =
2357 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002358
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002359 if (invert == 1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002360 ucontrol->value.integer.value[0] =
2361 mask - ucontrol->value.integer.value[0];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002362 return 0;
2363}
2364
Takashi Iwai475675d2005-11-17 15:11:51 +01002365static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2366 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002367{
Takashi Iwai475675d2005-11-17 15:11:51 +01002368 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002369 int elem = kcontrol->private_value & 0xff;
2370 int shift = (kcontrol->private_value >> 8) & 0xff;
2371 int mask = (kcontrol->private_value >> 16) & 0xff;
2372 int invert = (kcontrol->private_value >> 24) & 1;
2373 int changed = 0;
2374 unsigned short val;
Takashi Iwai5e246b82008-08-08 17:12:47 +02002375
2376 if (snd_BUG_ON(!dbri))
2377 return -EINVAL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002378
2379 val = (ucontrol->value.integer.value[0] & mask);
2380 if (invert == 1)
2381 val = mask - val;
2382 val <<= shift;
2383
2384 if (elem < 4) {
2385 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2386 ~(mask << shift)) | val;
2387 changed = (val != dbri->mm.data[elem]);
2388 } else {
2389 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2390 ~(mask << shift)) | val;
2391 changed = (val != dbri->mm.ctrl[elem - 4]);
2392 }
2393
2394 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2395 "mixer-value=%ld, mm-value=0x%x\n",
2396 mask, changed, ucontrol->value.integer.value[0],
2397 dbri->mm.data[elem & 3]);
2398
2399 if (changed) {
2400 /* First mute outputs, and wait 1/8000 sec (125 us)
2401 * to make sure this takes. This avoids clicking noises.
2402 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002403 cs4215_setdata(dbri, 1);
2404 udelay(125);
2405 cs4215_setdata(dbri, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002406 }
2407 return changed;
2408}
2409
2410/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2411 timeslots. Shift is the bit offset in the timeslot, mask defines the
2412 number of bits. invert is a boolean for use with attenuation.
2413 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002414#define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2415{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2416 .info = snd_cs4215_info_single, \
2417 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2418 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2419 ((invert) << 24) },
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002420
Bill Pemberton32e02a72012-12-06 12:35:25 -05002421static struct snd_kcontrol_new dbri_controls[] = {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002422 {
2423 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2424 .name = "Playback Volume",
2425 .info = snd_cs4215_info_volume,
2426 .get = snd_cs4215_get_volume,
2427 .put = snd_cs4215_put_volume,
2428 .private_value = DBRI_PLAY,
2429 },
2430 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2431 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2432 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2433 {
2434 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2435 .name = "Capture Volume",
2436 .info = snd_cs4215_info_volume,
2437 .get = snd_cs4215_get_volume,
2438 .put = snd_cs4215_put_volume,
2439 .private_value = DBRI_REC,
2440 },
2441 /* FIXME: mic/line switch */
2442 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2443 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2444 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2445 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2446};
2447
Bill Pemberton32e02a72012-12-06 12:35:25 -05002448static int snd_dbri_mixer(struct snd_card *card)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002449{
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002450 int idx, err;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002451 struct snd_dbri *dbri;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002452
Takashi Iwai5e246b82008-08-08 17:12:47 +02002453 if (snd_BUG_ON(!card || !card->private_data))
2454 return -EINVAL;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002455 dbri = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002456
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002457 strcpy(card->mixername, card->shortname);
2458
Tobias Klauser6c2d8b52006-09-29 02:00:21 -07002459 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002460 err = snd_ctl_add(card,
2461 snd_ctl_new1(&dbri_controls[idx], dbri));
2462 if (err < 0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002463 return err;
2464 }
2465
2466 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2467 dbri->stream_info[idx].left_gain = 0;
2468 dbri->stream_info[idx].right_gain = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002469 }
2470
2471 return 0;
2472}
2473
2474/****************************************************************************
2475 /proc interface
2476****************************************************************************/
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002477static void dbri_regs_read(struct snd_info_entry *entry,
2478 struct snd_info_buffer *buffer)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002479{
Takashi Iwai475675d2005-11-17 15:11:51 +01002480 struct snd_dbri *dbri = entry->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002481
2482 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2483 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2484 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2485 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2486}
2487
2488#ifdef DBRI_DEBUG
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002489static void dbri_debug_read(struct snd_info_entry *entry,
Takashi Iwai475675d2005-11-17 15:11:51 +01002490 struct snd_info_buffer *buffer)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002491{
Takashi Iwai475675d2005-11-17 15:11:51 +01002492 struct snd_dbri *dbri = entry->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002493 int pipe;
2494 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2495
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002496 for (pipe = 0; pipe < 32; pipe++) {
2497 if (pipe_active(dbri, pipe)) {
2498 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2499 snd_iprintf(buffer,
2500 "Pipe %d: %s SDP=0x%x desc=%d, "
Krzysztof Helt294a30d2006-08-21 19:29:59 +02002501 "len=%d next %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002502 pipe,
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002503 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2504 "input",
Krzysztof Helt5fc3a2b2006-08-17 16:58:45 +02002505 pptr->sdp, pptr->desc,
Krzysztof Helt294a30d2006-08-21 19:29:59 +02002506 pptr->length, pptr->nextpipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002507 }
2508 }
2509}
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002510#endif
2511
Bill Pemberton32e02a72012-12-06 12:35:25 -05002512static void snd_dbri_proc(struct snd_card *card)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002513{
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002514 struct snd_dbri *dbri = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002515
Takashi Iwai3c6ee772019-02-04 16:06:43 +01002516 snd_card_ro_proc_new(card, "regs", dbri, dbri_regs_read);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002517#ifdef DBRI_DEBUG
Takashi Iwai3c6ee772019-02-04 16:06:43 +01002518 snd_card_ro_proc_new(card, "debug", dbri, dbri_debug_read);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002519#endif
2520}
2521
2522/*
2523****************************************************************************
2524**************************** Initialization ********************************
2525****************************************************************************
2526*/
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002527static void snd_dbri_free(struct snd_dbri *dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002528
Bill Pemberton32e02a72012-12-06 12:35:25 -05002529static int snd_dbri_create(struct snd_card *card,
2530 struct platform_device *op,
2531 int irq, int dev)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002532{
Takashi Iwai475675d2005-11-17 15:11:51 +01002533 struct snd_dbri *dbri = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002534 int err;
2535
2536 spin_lock_init(&dbri->lock);
David S. Miller2bd320f2008-08-27 00:30:59 -07002537 dbri->op = op;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002538 dbri->irq = irq;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002539
Luis Chamberlain750afb02019-01-04 09:23:09 +01002540 dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma),
2541 &dbri->dma_dvma, GFP_KERNEL);
FUJITA Tomonoribe376642008-10-29 15:34:39 -07002542 if (!dbri->dma)
2543 return -ENOMEM;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002544
Tushar Dave16f46052016-11-24 12:35:16 -08002545 dprintk(D_GEN, "DMA Cmd Block 0x%p (%pad)\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002546 dbri->dma, dbri->dma_dvma);
2547
2548 /* Map the registers into memory. */
David S. Miller2bd320f2008-08-27 00:30:59 -07002549 dbri->regs_size = resource_size(&op->resource[0]);
2550 dbri->regs = of_ioremap(&op->resource[0], 0,
2551 dbri->regs_size, "DBRI Registers");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002552 if (!dbri->regs) {
2553 printk(KERN_ERR "DBRI: could not allocate registers\n");
David S. Miller2bd320f2008-08-27 00:30:59 -07002554 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
David S. Miller738f2b72008-08-27 18:09:11 -07002555 (void *)dbri->dma, dbri->dma_dvma);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002556 return -EIO;
2557 }
2558
Thomas Gleixner65ca68b2006-07-01 19:29:46 -07002559 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002560 "DBRI audio", dbri);
2561 if (err) {
2562 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
David S. Miller2bd320f2008-08-27 00:30:59 -07002563 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2564 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
David S. Miller738f2b72008-08-27 18:09:11 -07002565 (void *)dbri->dma, dbri->dma_dvma);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002566 return err;
2567 }
2568
2569 /* Do low level initialization of the DBRI and CS4215 chips */
2570 dbri_initialize(dbri);
2571 err = cs4215_init(dbri);
2572 if (err) {
2573 snd_dbri_free(dbri);
2574 return err;
2575 }
2576
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002577 return 0;
2578}
2579
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002580static void snd_dbri_free(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002581{
2582 dprintk(D_GEN, "snd_dbri_free\n");
2583 dbri_reset(dbri);
2584
2585 if (dbri->irq)
2586 free_irq(dbri->irq, dbri);
2587
2588 if (dbri->regs)
David S. Miller2bd320f2008-08-27 00:30:59 -07002589 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002590
2591 if (dbri->dma)
David S. Miller2bd320f2008-08-27 00:30:59 -07002592 dma_free_coherent(&dbri->op->dev,
David S. Miller738f2b72008-08-27 18:09:11 -07002593 sizeof(struct dbri_dma),
2594 (void *)dbri->dma, dbri->dma_dvma);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002595}
2596
Bill Pemberton32e02a72012-12-06 12:35:25 -05002597static int dbri_probe(struct platform_device *op)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002598{
Takashi Iwai475675d2005-11-17 15:11:51 +01002599 struct snd_dbri *dbri;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002600 struct resource *rp;
Takashi Iwai475675d2005-11-17 15:11:51 +01002601 struct snd_card *card;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002602 static int dev = 0;
David S. Miller2bd320f2008-08-27 00:30:59 -07002603 int irq;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002604 int err;
2605
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002606 if (dev >= SNDRV_CARDS)
2607 return -ENODEV;
2608 if (!enable[dev]) {
2609 dev++;
2610 return -ENOENT;
2611 }
2612
Grant Likely1636f8a2010-06-18 11:09:58 -06002613 irq = op->archdata.irqs[0];
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002614 if (irq <= 0) {
2615 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
Martin Habets43388292005-09-10 15:39:00 +02002616 return -ENODEV;
2617 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002618
Takashi Iwaia2fefc32014-01-29 14:41:09 +01002619 err = snd_card_new(&op->dev, index[dev], id[dev], THIS_MODULE,
2620 sizeof(struct snd_dbri), &card);
Takashi Iwaibd7dd772008-12-28 16:45:02 +01002621 if (err < 0)
2622 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002623
2624 strcpy(card->driver, "DBRI");
2625 strcpy(card->shortname, "Sun DBRI");
David S. Miller2bd320f2008-08-27 00:30:59 -07002626 rp = &op->resource[0];
Andrew Morton5863aa62006-07-03 00:24:22 -07002627 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002628 card->shortname,
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002629 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002630
David S. Miller2bd320f2008-08-27 00:30:59 -07002631 err = snd_dbri_create(card, op, irq, dev);
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002632 if (err < 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002633 snd_card_free(card);
2634 return err;
2635 }
2636
Takashi Iwai475675d2005-11-17 15:11:51 +01002637 dbri = card->private_data;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002638 err = snd_dbri_pcm(card);
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002639 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002640 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002641
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002642 err = snd_dbri_mixer(card);
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002643 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002644 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002645
2646 /* /proc file handling */
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002647 snd_dbri_proc(card);
David S. Miller2bd320f2008-08-27 00:30:59 -07002648 dev_set_drvdata(&op->dev, card);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002649
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002650 err = snd_card_register(card);
2651 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002652 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002653
2654 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2655 dev, dbri->regs,
Grant Likely61c7a082010-04-13 16:12:29 -07002656 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002657 dev++;
2658
2659 return 0;
Takashi Iwai16dab542005-09-05 17:17:58 +02002660
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002661_err:
Takashi Iwai16dab542005-09-05 17:17:58 +02002662 snd_dbri_free(dbri);
2663 snd_card_free(card);
2664 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002665}
2666
Bill Pemberton32e02a72012-12-06 12:35:25 -05002667static int dbri_remove(struct platform_device *op)
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002668{
David S. Miller2bd320f2008-08-27 00:30:59 -07002669 struct snd_card *card = dev_get_drvdata(&op->dev);
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002670
2671 snd_dbri_free(card->private_data);
2672 snd_card_free(card);
2673
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002674 return 0;
2675}
2676
David S. Millerfd098312008-08-31 01:23:17 -07002677static const struct of_device_id dbri_match[] = {
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002678 {
2679 .name = "SUNW,DBRIe",
2680 },
2681 {
2682 .name = "SUNW,DBRIf",
2683 },
2684 {},
2685};
2686
2687MODULE_DEVICE_TABLE(of, dbri_match);
2688
Grant Likelyf07eb222011-02-22 21:05:04 -07002689static struct platform_driver dbri_sbus_driver = {
Grant Likely40182942010-04-13 16:13:02 -07002690 .driver = {
2691 .name = "dbri",
Grant Likely40182942010-04-13 16:13:02 -07002692 .of_match_table = dbri_match,
2693 },
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002694 .probe = dbri_probe,
Bill Pemberton32e02a72012-12-06 12:35:25 -05002695 .remove = dbri_remove,
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002696};
2697
Axel Lina09452e2011-11-27 16:36:04 +08002698module_platform_driver(dbri_sbus_driver);