Chen Liqin | 6bc9a39 | 2009-06-12 22:01:00 +0800 | [diff] [blame] | 1 | #ifndef _ASM_SCORE_ASMMACRO_H |
| 2 | #define _ASM_SCORE_ASMMACRO_H |
| 3 | |
| 4 | #include <asm/asm-offsets.h> |
| 5 | |
| 6 | #ifdef __ASSEMBLY__ |
| 7 | |
| 8 | .macro SAVE_ALL |
| 9 | mfcr r30, cr0 |
| 10 | mv r31, r0 |
| 11 | nop |
| 12 | /* if UMs == 1, change stack. */ |
| 13 | slli.c r30, r30, 28 |
| 14 | bpl 1f |
| 15 | la r31, kernelsp |
| 16 | lw r31, [r31] |
| 17 | 1: |
| 18 | mv r30, r0 |
| 19 | addri r0, r31, -PT_SIZE |
| 20 | |
| 21 | sw r30, [r0, PT_R0] |
| 22 | .set r1 |
| 23 | sw r1, [r0, PT_R1] |
| 24 | .set nor1 |
| 25 | sw r2, [r0, PT_R2] |
| 26 | sw r3, [r0, PT_R3] |
| 27 | sw r4, [r0, PT_R4] |
| 28 | sw r5, [r0, PT_R5] |
| 29 | sw r6, [r0, PT_R6] |
| 30 | sw r7, [r0, PT_R7] |
| 31 | |
| 32 | sw r8, [r0, PT_R8] |
| 33 | sw r9, [r0, PT_R9] |
| 34 | sw r10, [r0, PT_R10] |
| 35 | sw r11, [r0, PT_R11] |
| 36 | sw r12, [r0, PT_R12] |
| 37 | sw r13, [r0, PT_R13] |
| 38 | sw r14, [r0, PT_R14] |
| 39 | sw r15, [r0, PT_R15] |
| 40 | |
| 41 | sw r16, [r0, PT_R16] |
| 42 | sw r17, [r0, PT_R17] |
| 43 | sw r18, [r0, PT_R18] |
| 44 | sw r19, [r0, PT_R19] |
| 45 | sw r20, [r0, PT_R20] |
| 46 | sw r21, [r0, PT_R21] |
| 47 | sw r22, [r0, PT_R22] |
| 48 | sw r23, [r0, PT_R23] |
| 49 | |
| 50 | sw r24, [r0, PT_R24] |
| 51 | sw r25, [r0, PT_R25] |
| 52 | sw r25, [r0, PT_R25] |
| 53 | sw r26, [r0, PT_R26] |
| 54 | sw r27, [r0, PT_R27] |
| 55 | |
| 56 | sw r28, [r0, PT_R28] |
| 57 | sw r29, [r0, PT_R29] |
| 58 | orri r28, r0, 0x1fff |
| 59 | li r31, 0x00001fff |
| 60 | xor r28, r28, r31 |
| 61 | |
| 62 | mfcehl r30, r31 |
| 63 | sw r30, [r0, PT_CEH] |
| 64 | sw r31, [r0, PT_CEL] |
| 65 | |
| 66 | mfcr r31, cr0 |
| 67 | sw r31, [r0, PT_PSR] |
| 68 | |
| 69 | mfcr r31, cr1 |
| 70 | sw r31, [r0, PT_CONDITION] |
| 71 | |
| 72 | mfcr r31, cr2 |
| 73 | sw r31, [r0, PT_ECR] |
| 74 | |
| 75 | mfcr r31, cr5 |
| 76 | srli r31, r31, 1 |
| 77 | slli r31, r31, 1 |
| 78 | sw r31, [r0, PT_EPC] |
| 79 | .endm |
| 80 | |
| 81 | .macro RESTORE_ALL_AND_RET |
| 82 | mfcr r30, cr0 |
| 83 | srli r30, r30, 1 |
| 84 | slli r30, r30, 1 |
| 85 | mtcr r30, cr0 |
| 86 | nop |
| 87 | nop |
| 88 | nop |
| 89 | nop |
| 90 | nop |
| 91 | |
| 92 | .set r1 |
| 93 | ldis r1, 0x00ff |
| 94 | and r30, r30, r1 |
| 95 | not r1, r1 |
| 96 | lw r31, [r0, PT_PSR] |
| 97 | and r31, r31, r1 |
| 98 | .set nor1 |
| 99 | or r31, r31, r30 |
| 100 | mtcr r31, cr0 |
| 101 | nop |
| 102 | nop |
| 103 | nop |
| 104 | nop |
| 105 | nop |
| 106 | |
| 107 | lw r30, [r0, PT_CONDITION] |
| 108 | mtcr r30, cr1 |
| 109 | nop |
| 110 | nop |
| 111 | nop |
| 112 | nop |
| 113 | nop |
| 114 | |
| 115 | lw r30, [r0, PT_CEH] |
| 116 | lw r31, [r0, PT_CEL] |
| 117 | mtcehl r30, r31 |
| 118 | |
| 119 | .set r1 |
| 120 | lw r1, [r0, PT_R1] |
| 121 | .set nor1 |
| 122 | lw r2, [r0, PT_R2] |
| 123 | lw r3, [r0, PT_R3] |
| 124 | lw r4, [r0, PT_R4] |
| 125 | lw r5, [r0, PT_R5] |
| 126 | lw r6, [r0, PT_R6] |
| 127 | lw r7, [r0, PT_R7] |
| 128 | |
| 129 | lw r8, [r0, PT_R8] |
| 130 | lw r9, [r0, PT_R9] |
| 131 | lw r10, [r0, PT_R10] |
| 132 | lw r11, [r0, PT_R11] |
| 133 | lw r12, [r0, PT_R12] |
| 134 | lw r13, [r0, PT_R13] |
| 135 | lw r14, [r0, PT_R14] |
| 136 | lw r15, [r0, PT_R15] |
| 137 | |
| 138 | lw r16, [r0, PT_R16] |
| 139 | lw r17, [r0, PT_R17] |
| 140 | lw r18, [r0, PT_R18] |
| 141 | lw r19, [r0, PT_R19] |
| 142 | lw r20, [r0, PT_R20] |
| 143 | lw r21, [r0, PT_R21] |
| 144 | lw r22, [r0, PT_R22] |
| 145 | lw r23, [r0, PT_R23] |
| 146 | |
| 147 | lw r24, [r0, PT_R24] |
| 148 | lw r25, [r0, PT_R25] |
| 149 | lw r26, [r0, PT_R26] |
| 150 | lw r27, [r0, PT_R27] |
| 151 | lw r28, [r0, PT_R28] |
| 152 | lw r29, [r0, PT_R29] |
| 153 | |
| 154 | lw r30, [r0, PT_EPC] |
| 155 | lw r0, [r0, PT_R0] |
| 156 | mtcr r30, cr5 |
| 157 | rte |
| 158 | .endm |
| 159 | |
| 160 | #endif /* __ASSEMBLY__ */ |
| 161 | #endif /* _ASM_SCORE_ASMMACRO_H */ |