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Thierry Redinga1702852009-03-27 00:12:24 -07001/*
Paul Gortmaker3396c782012-01-27 13:36:01 +00002 * linux/drivers/net/ethernet/ethoc.c
Thierry Redinga1702852009-03-27 00:12:24 -07003 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000014#include <linux/dma-mapping.h>
Thierry Redinga1702852009-03-27 00:12:24 -070015#include <linux/etherdevice.h>
Max Filippova13aff02014-02-04 03:33:10 +040016#include <linux/clk.h>
Thierry Redinga1702852009-03-27 00:12:24 -070017#include <linux/crc32.h>
Alexey Dobriyana6b7a402011-06-06 10:43:46 +000018#include <linux/interrupt.h>
Thierry Redinga1702852009-03-27 00:12:24 -070019#include <linux/io.h>
20#include <linux/mii.h>
21#include <linux/phy.h>
22#include <linux/platform_device.h>
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040023#include <linux/sched.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Jonas Bonne0f42582010-11-25 02:30:25 +000025#include <linux/of.h>
Paul Gortmaker9d9779e2011-07-03 15:21:01 -040026#include <linux/module.h>
Thierry Redinga1702852009-03-27 00:12:24 -070027#include <net/ethoc.h>
28
Thomas Chou0baa0802009-10-04 23:33:20 +000029static int buffer_size = 0x8000; /* 32 KBytes */
30module_param(buffer_size, int, 0);
31MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
32
Thierry Redinga1702852009-03-27 00:12:24 -070033/* register offsets */
34#define MODER 0x00
35#define INT_SOURCE 0x04
36#define INT_MASK 0x08
37#define IPGT 0x0c
38#define IPGR1 0x10
39#define IPGR2 0x14
40#define PACKETLEN 0x18
41#define COLLCONF 0x1c
42#define TX_BD_NUM 0x20
43#define CTRLMODER 0x24
44#define MIIMODER 0x28
45#define MIICOMMAND 0x2c
46#define MIIADDRESS 0x30
47#define MIITX_DATA 0x34
48#define MIIRX_DATA 0x38
49#define MIISTATUS 0x3c
50#define MAC_ADDR0 0x40
51#define MAC_ADDR1 0x44
52#define ETH_HASH0 0x48
53#define ETH_HASH1 0x4c
54#define ETH_TXCTRL 0x50
Max Filippov11129092014-01-31 09:41:06 +040055#define ETH_END 0x54
Thierry Redinga1702852009-03-27 00:12:24 -070056
57/* mode register */
58#define MODER_RXEN (1 << 0) /* receive enable */
59#define MODER_TXEN (1 << 1) /* transmit enable */
60#define MODER_NOPRE (1 << 2) /* no preamble */
61#define MODER_BRO (1 << 3) /* broadcast address */
62#define MODER_IAM (1 << 4) /* individual address mode */
63#define MODER_PRO (1 << 5) /* promiscuous mode */
64#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
65#define MODER_LOOP (1 << 7) /* loopback */
66#define MODER_NBO (1 << 8) /* no back-off */
67#define MODER_EDE (1 << 9) /* excess defer enable */
68#define MODER_FULLD (1 << 10) /* full duplex */
69#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
70#define MODER_DCRC (1 << 12) /* delayed CRC enable */
71#define MODER_CRC (1 << 13) /* CRC enable */
72#define MODER_HUGE (1 << 14) /* huge packets enable */
73#define MODER_PAD (1 << 15) /* padding enabled */
74#define MODER_RSM (1 << 16) /* receive small packets */
75
76/* interrupt source and mask registers */
77#define INT_MASK_TXF (1 << 0) /* transmit frame */
78#define INT_MASK_TXE (1 << 1) /* transmit error */
79#define INT_MASK_RXF (1 << 2) /* receive frame */
80#define INT_MASK_RXE (1 << 3) /* receive error */
81#define INT_MASK_BUSY (1 << 4)
82#define INT_MASK_TXC (1 << 5) /* transmit control frame */
83#define INT_MASK_RXC (1 << 6) /* receive control frame */
84
85#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
86#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
87
88#define INT_MASK_ALL ( \
89 INT_MASK_TXF | INT_MASK_TXE | \
90 INT_MASK_RXF | INT_MASK_RXE | \
91 INT_MASK_TXC | INT_MASK_RXC | \
92 INT_MASK_BUSY \
93 )
94
95/* packet length register */
96#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
97#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
98#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
99 PACKETLEN_MAX(max))
100
101/* transmit buffer number register */
102#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
103
104/* control module mode register */
105#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
106#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
107#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
108
109/* MII mode register */
110#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
111#define MIIMODER_NOPRE (1 << 8) /* no preamble */
112
113/* MII command register */
114#define MIICOMMAND_SCAN (1 << 0) /* scan status */
115#define MIICOMMAND_READ (1 << 1) /* read status */
116#define MIICOMMAND_WRITE (1 << 2) /* write control data */
117
118/* MII address register */
119#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
120#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
121#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
122 MIIADDRESS_RGAD(reg))
123
124/* MII transmit data register */
125#define MIITX_DATA_VAL(x) ((x) & 0xffff)
126
127/* MII receive data register */
128#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
129
130/* MII status register */
131#define MIISTATUS_LINKFAIL (1 << 0)
132#define MIISTATUS_BUSY (1 << 1)
133#define MIISTATUS_INVALID (1 << 2)
134
135/* TX buffer descriptor */
136#define TX_BD_CS (1 << 0) /* carrier sense lost */
137#define TX_BD_DF (1 << 1) /* defer indication */
138#define TX_BD_LC (1 << 2) /* late collision */
139#define TX_BD_RL (1 << 3) /* retransmission limit */
140#define TX_BD_RETRY_MASK (0x00f0)
141#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
142#define TX_BD_UR (1 << 8) /* transmitter underrun */
143#define TX_BD_CRC (1 << 11) /* TX CRC enable */
144#define TX_BD_PAD (1 << 12) /* pad enable for short packets */
145#define TX_BD_WRAP (1 << 13)
146#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
147#define TX_BD_READY (1 << 15) /* TX buffer ready */
148#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
149#define TX_BD_LEN_MASK (0xffff << 16)
150
151#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
152 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
153
154/* RX buffer descriptor */
155#define RX_BD_LC (1 << 0) /* late collision */
156#define RX_BD_CRC (1 << 1) /* RX CRC error */
157#define RX_BD_SF (1 << 2) /* short frame */
158#define RX_BD_TL (1 << 3) /* too long */
159#define RX_BD_DN (1 << 4) /* dribble nibble */
160#define RX_BD_IS (1 << 5) /* invalid symbol */
161#define RX_BD_OR (1 << 6) /* receiver overrun */
162#define RX_BD_MISS (1 << 7)
163#define RX_BD_CF (1 << 8) /* control frame */
164#define RX_BD_WRAP (1 << 13)
165#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
166#define RX_BD_EMPTY (1 << 15)
167#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
168
169#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
170 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
171
172#define ETHOC_BUFSIZ 1536
173#define ETHOC_ZLEN 64
174#define ETHOC_BD_BASE 0x400
175#define ETHOC_TIMEOUT (HZ / 2)
176#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
177
178/**
179 * struct ethoc - driver-private device structure
180 * @iobase: pointer to I/O memory region
181 * @membase: pointer to buffer memory region
Thomas Chou0baa0802009-10-04 23:33:20 +0000182 * @dma_alloc: dma allocated buffer size
Thomas Chouee02a4e2010-05-23 16:44:02 +0000183 * @io_region_size: I/O memory region size
Max Filippovbee7bac2014-01-31 09:41:07 +0400184 * @num_bd: number of buffer descriptors
Thierry Redinga1702852009-03-27 00:12:24 -0700185 * @num_tx: number of send buffers
186 * @cur_tx: last send buffer written
187 * @dty_tx: last buffer actually sent
188 * @num_rx: number of receive buffers
189 * @cur_rx: current receive buffer
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000190 * @vma: pointer to array of virtual memory addresses for buffers
Thierry Redinga1702852009-03-27 00:12:24 -0700191 * @netdev: pointer to network device structure
192 * @napi: NAPI structure
Thierry Redinga1702852009-03-27 00:12:24 -0700193 * @msg_enable: device state flags
Thierry Redinga1702852009-03-27 00:12:24 -0700194 * @lock: device lock
195 * @phy: attached PHY
196 * @mdio: MDIO bus for PHY access
197 * @phy_id: address of attached PHY
198 */
199struct ethoc {
200 void __iomem *iobase;
201 void __iomem *membase;
Thomas Chou0baa0802009-10-04 23:33:20 +0000202 int dma_alloc;
Thomas Chouee02a4e2010-05-23 16:44:02 +0000203 resource_size_t io_region_size;
Max Filippov06e60e592015-09-22 14:27:16 +0300204 bool big_endian;
Thierry Redinga1702852009-03-27 00:12:24 -0700205
Max Filippovbee7bac2014-01-31 09:41:07 +0400206 unsigned int num_bd;
Thierry Redinga1702852009-03-27 00:12:24 -0700207 unsigned int num_tx;
208 unsigned int cur_tx;
209 unsigned int dty_tx;
210
211 unsigned int num_rx;
212 unsigned int cur_rx;
213
Barry Grussling72aa8e12013-01-27 18:44:36 +0000214 void **vma;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000215
Thierry Redinga1702852009-03-27 00:12:24 -0700216 struct net_device *netdev;
217 struct napi_struct napi;
Thierry Redinga1702852009-03-27 00:12:24 -0700218 u32 msg_enable;
219
Thierry Redinga1702852009-03-27 00:12:24 -0700220 spinlock_t lock;
221
222 struct phy_device *phy;
223 struct mii_bus *mdio;
Max Filippova13aff02014-02-04 03:33:10 +0400224 struct clk *clk;
Thierry Redinga1702852009-03-27 00:12:24 -0700225 s8 phy_id;
226};
227
228/**
229 * struct ethoc_bd - buffer descriptor
230 * @stat: buffer statistics
231 * @addr: physical memory address
232 */
233struct ethoc_bd {
234 u32 stat;
235 u32 addr;
236};
237
Thomas Chou16dd18b2009-10-07 14:16:42 +0000238static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
Thierry Redinga1702852009-03-27 00:12:24 -0700239{
Max Filippov06e60e592015-09-22 14:27:16 +0300240 if (dev->big_endian)
241 return ioread32be(dev->iobase + offset);
242 else
243 return ioread32(dev->iobase + offset);
Thierry Redinga1702852009-03-27 00:12:24 -0700244}
245
Thomas Chou16dd18b2009-10-07 14:16:42 +0000246static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
Thierry Redinga1702852009-03-27 00:12:24 -0700247{
Max Filippov06e60e592015-09-22 14:27:16 +0300248 if (dev->big_endian)
249 iowrite32be(data, dev->iobase + offset);
250 else
251 iowrite32(data, dev->iobase + offset);
Thierry Redinga1702852009-03-27 00:12:24 -0700252}
253
Thomas Chou16dd18b2009-10-07 14:16:42 +0000254static inline void ethoc_read_bd(struct ethoc *dev, int index,
255 struct ethoc_bd *bd)
Thierry Redinga1702852009-03-27 00:12:24 -0700256{
257 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
258 bd->stat = ethoc_read(dev, offset + 0);
259 bd->addr = ethoc_read(dev, offset + 4);
260}
261
Thomas Chou16dd18b2009-10-07 14:16:42 +0000262static inline void ethoc_write_bd(struct ethoc *dev, int index,
Thierry Redinga1702852009-03-27 00:12:24 -0700263 const struct ethoc_bd *bd)
264{
265 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
266 ethoc_write(dev, offset + 0, bd->stat);
267 ethoc_write(dev, offset + 4, bd->addr);
268}
269
Thomas Chou16dd18b2009-10-07 14:16:42 +0000270static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700271{
272 u32 imask = ethoc_read(dev, INT_MASK);
273 imask |= mask;
274 ethoc_write(dev, INT_MASK, imask);
275}
276
Thomas Chou16dd18b2009-10-07 14:16:42 +0000277static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700278{
279 u32 imask = ethoc_read(dev, INT_MASK);
280 imask &= ~mask;
281 ethoc_write(dev, INT_MASK, imask);
282}
283
Thomas Chou16dd18b2009-10-07 14:16:42 +0000284static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
Thierry Redinga1702852009-03-27 00:12:24 -0700285{
286 ethoc_write(dev, INT_SOURCE, mask);
287}
288
Thomas Chou16dd18b2009-10-07 14:16:42 +0000289static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700290{
291 u32 mode = ethoc_read(dev, MODER);
292 mode |= MODER_RXEN | MODER_TXEN;
293 ethoc_write(dev, MODER, mode);
294}
295
Thomas Chou16dd18b2009-10-07 14:16:42 +0000296static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700297{
298 u32 mode = ethoc_read(dev, MODER);
299 mode &= ~(MODER_RXEN | MODER_TXEN);
300 ethoc_write(dev, MODER, mode);
301}
302
David S. Miller5cf3e032010-07-07 18:23:19 -0700303static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
Thierry Redinga1702852009-03-27 00:12:24 -0700304{
305 struct ethoc_bd bd;
306 int i;
Barry Grussling72aa8e12013-01-27 18:44:36 +0000307 void *vma;
Thierry Redinga1702852009-03-27 00:12:24 -0700308
309 dev->cur_tx = 0;
310 dev->dty_tx = 0;
311 dev->cur_rx = 0;
312
Jonas Bonnee4f56b2010-06-11 02:47:36 +0000313 ethoc_write(dev, TX_BD_NUM, dev->num_tx);
314
Thierry Redinga1702852009-03-27 00:12:24 -0700315 /* setup transmission buffers */
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000316 bd.addr = mem_start;
Thierry Redinga1702852009-03-27 00:12:24 -0700317 bd.stat = TX_BD_IRQ | TX_BD_CRC;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000318 vma = dev->membase;
Thierry Redinga1702852009-03-27 00:12:24 -0700319
320 for (i = 0; i < dev->num_tx; i++) {
321 if (i == dev->num_tx - 1)
322 bd.stat |= TX_BD_WRAP;
323
324 ethoc_write_bd(dev, i, &bd);
325 bd.addr += ETHOC_BUFSIZ;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000326
327 dev->vma[i] = vma;
328 vma += ETHOC_BUFSIZ;
Thierry Redinga1702852009-03-27 00:12:24 -0700329 }
330
Thierry Redinga1702852009-03-27 00:12:24 -0700331 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
332
333 for (i = 0; i < dev->num_rx; i++) {
334 if (i == dev->num_rx - 1)
335 bd.stat |= RX_BD_WRAP;
336
337 ethoc_write_bd(dev, dev->num_tx + i, &bd);
338 bd.addr += ETHOC_BUFSIZ;
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000339
340 dev->vma[dev->num_tx + i] = vma;
341 vma += ETHOC_BUFSIZ;
Thierry Redinga1702852009-03-27 00:12:24 -0700342 }
343
344 return 0;
345}
346
347static int ethoc_reset(struct ethoc *dev)
348{
349 u32 mode;
350
351 /* TODO: reset controller? */
352
353 ethoc_disable_rx_and_tx(dev);
354
355 /* TODO: setup registers */
356
357 /* enable FCS generation and automatic padding */
358 mode = ethoc_read(dev, MODER);
359 mode |= MODER_CRC | MODER_PAD;
360 ethoc_write(dev, MODER, mode);
361
362 /* set full-duplex mode */
363 mode = ethoc_read(dev, MODER);
364 mode |= MODER_FULLD;
365 ethoc_write(dev, MODER, mode);
366 ethoc_write(dev, IPGT, 0x15);
367
368 ethoc_ack_irq(dev, INT_MASK_ALL);
369 ethoc_enable_irq(dev, INT_MASK_ALL);
370 ethoc_enable_rx_and_tx(dev);
371 return 0;
372}
373
374static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
375 struct ethoc_bd *bd)
376{
377 struct net_device *netdev = dev->netdev;
378 unsigned int ret = 0;
379
380 if (bd->stat & RX_BD_TL) {
381 dev_err(&netdev->dev, "RX: frame too long\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000382 netdev->stats.rx_length_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700383 ret++;
384 }
385
386 if (bd->stat & RX_BD_SF) {
387 dev_err(&netdev->dev, "RX: frame too short\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000388 netdev->stats.rx_length_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700389 ret++;
390 }
391
392 if (bd->stat & RX_BD_DN) {
393 dev_err(&netdev->dev, "RX: dribble nibble\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000394 netdev->stats.rx_frame_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700395 }
396
397 if (bd->stat & RX_BD_CRC) {
398 dev_err(&netdev->dev, "RX: wrong CRC\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000399 netdev->stats.rx_crc_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700400 ret++;
401 }
402
403 if (bd->stat & RX_BD_OR) {
404 dev_err(&netdev->dev, "RX: overrun\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000405 netdev->stats.rx_over_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700406 ret++;
407 }
408
409 if (bd->stat & RX_BD_MISS)
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000410 netdev->stats.rx_missed_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700411
412 if (bd->stat & RX_BD_LC) {
413 dev_err(&netdev->dev, "RX: late collision\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000414 netdev->stats.collisions++;
Thierry Redinga1702852009-03-27 00:12:24 -0700415 ret++;
416 }
417
418 return ret;
419}
420
421static int ethoc_rx(struct net_device *dev, int limit)
422{
423 struct ethoc *priv = netdev_priv(dev);
424 int count;
425
426 for (count = 0; count < limit; ++count) {
427 unsigned int entry;
428 struct ethoc_bd bd;
429
Jonas Bonn6a632622010-11-25 02:30:32 +0000430 entry = priv->num_tx + priv->cur_rx;
Thierry Redinga1702852009-03-27 00:12:24 -0700431 ethoc_read_bd(priv, entry, &bd);
Jonas Bonn20f70dd2010-11-25 02:30:28 +0000432 if (bd.stat & RX_BD_EMPTY) {
433 ethoc_ack_irq(priv, INT_MASK_RX);
434 /* If packet (interrupt) came in between checking
435 * BD_EMTPY and clearing the interrupt source, then we
436 * risk missing the packet as the RX interrupt won't
437 * trigger right away when we reenable it; hence, check
438 * BD_EMTPY here again to make sure there isn't such a
439 * packet waiting for us...
440 */
441 ethoc_read_bd(priv, entry, &bd);
442 if (bd.stat & RX_BD_EMPTY)
443 break;
444 }
Thierry Redinga1702852009-03-27 00:12:24 -0700445
446 if (ethoc_update_rx_stats(priv, &bd) == 0) {
447 int size = bd.stat >> 16;
Eric Dumazet89d71a62009-10-13 05:34:20 +0000448 struct sk_buff *skb;
Thomas Chou050f91d2009-10-04 23:33:19 +0000449
450 size -= 4; /* strip the CRC */
Eric Dumazet89d71a62009-10-13 05:34:20 +0000451 skb = netdev_alloc_skb_ip_align(dev, size);
Thomas Chou050f91d2009-10-04 23:33:19 +0000452
Thierry Redinga1702852009-03-27 00:12:24 -0700453 if (likely(skb)) {
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000454 void *src = priv->vma[entry];
Thierry Redinga1702852009-03-27 00:12:24 -0700455 memcpy_fromio(skb_put(skb, size), src, size);
456 skb->protocol = eth_type_trans(skb, dev);
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000457 dev->stats.rx_packets++;
458 dev->stats.rx_bytes += size;
Thierry Redinga1702852009-03-27 00:12:24 -0700459 netif_receive_skb(skb);
460 } else {
461 if (net_ratelimit())
Barry Grussling72aa8e12013-01-27 18:44:36 +0000462 dev_warn(&dev->dev,
463 "low on memory - packet dropped\n");
Thierry Redinga1702852009-03-27 00:12:24 -0700464
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000465 dev->stats.rx_dropped++;
Thierry Redinga1702852009-03-27 00:12:24 -0700466 break;
467 }
468 }
469
470 /* clear the buffer descriptor so it can be reused */
471 bd.stat &= ~RX_BD_STATS;
472 bd.stat |= RX_BD_EMPTY;
473 ethoc_write_bd(priv, entry, &bd);
Jonas Bonn6a632622010-11-25 02:30:32 +0000474 if (++priv->cur_rx == priv->num_rx)
475 priv->cur_rx = 0;
Thierry Redinga1702852009-03-27 00:12:24 -0700476 }
477
478 return count;
479}
480
Jonas Bonn4f64bcb2010-11-25 02:30:31 +0000481static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
Thierry Redinga1702852009-03-27 00:12:24 -0700482{
483 struct net_device *netdev = dev->netdev;
484
485 if (bd->stat & TX_BD_LC) {
486 dev_err(&netdev->dev, "TX: late collision\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000487 netdev->stats.tx_window_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700488 }
489
490 if (bd->stat & TX_BD_RL) {
491 dev_err(&netdev->dev, "TX: retransmit limit\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000492 netdev->stats.tx_aborted_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700493 }
494
495 if (bd->stat & TX_BD_UR) {
496 dev_err(&netdev->dev, "TX: underrun\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000497 netdev->stats.tx_fifo_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700498 }
499
500 if (bd->stat & TX_BD_CS) {
501 dev_err(&netdev->dev, "TX: carrier sense lost\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000502 netdev->stats.tx_carrier_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700503 }
504
505 if (bd->stat & TX_BD_STATS)
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000506 netdev->stats.tx_errors++;
Thierry Redinga1702852009-03-27 00:12:24 -0700507
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000508 netdev->stats.collisions += (bd->stat >> 4) & 0xf;
509 netdev->stats.tx_bytes += bd->stat >> 16;
510 netdev->stats.tx_packets++;
Thierry Redinga1702852009-03-27 00:12:24 -0700511}
512
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000513static int ethoc_tx(struct net_device *dev, int limit)
Thierry Redinga1702852009-03-27 00:12:24 -0700514{
515 struct ethoc *priv = netdev_priv(dev);
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000516 int count;
517 struct ethoc_bd bd;
Thierry Redinga1702852009-03-27 00:12:24 -0700518
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000519 for (count = 0; count < limit; ++count) {
520 unsigned int entry;
Thierry Redinga1702852009-03-27 00:12:24 -0700521
Jonas Bonn6a632622010-11-25 02:30:32 +0000522 entry = priv->dty_tx & (priv->num_tx-1);
Thierry Redinga1702852009-03-27 00:12:24 -0700523
524 ethoc_read_bd(priv, entry, &bd);
Thierry Redinga1702852009-03-27 00:12:24 -0700525
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000526 if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
527 ethoc_ack_irq(priv, INT_MASK_TX);
528 /* If interrupt came in between reading in the BD
529 * and clearing the interrupt source, then we risk
530 * missing the event as the TX interrupt won't trigger
531 * right away when we reenable it; hence, check
532 * BD_EMPTY here again to make sure there isn't such an
533 * event pending...
534 */
535 ethoc_read_bd(priv, entry, &bd);
536 if (bd.stat & TX_BD_READY ||
537 (priv->dty_tx == priv->cur_tx))
538 break;
539 }
540
Jonas Bonn4f64bcb2010-11-25 02:30:31 +0000541 ethoc_update_tx_stats(priv, &bd);
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000542 priv->dty_tx++;
Thierry Redinga1702852009-03-27 00:12:24 -0700543 }
544
545 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
546 netif_wake_queue(dev);
547
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000548 return count;
Thierry Redinga1702852009-03-27 00:12:24 -0700549}
550
551static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
552{
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000553 struct net_device *dev = dev_id;
Thierry Redinga1702852009-03-27 00:12:24 -0700554 struct ethoc *priv = netdev_priv(dev);
555 u32 pending;
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000556 u32 mask;
Thierry Redinga1702852009-03-27 00:12:24 -0700557
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000558 /* Figure out what triggered the interrupt...
559 * The tricky bit here is that the interrupt source bits get
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300560 * set in INT_SOURCE for an event regardless of whether that
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000561 * event is masked or not. Thus, in order to figure out what
562 * triggered the interrupt, we need to remove the sources
563 * for all events that are currently masked. This behaviour
564 * is not particularly well documented but reasonable...
565 */
566 mask = ethoc_read(priv, INT_MASK);
Thierry Redinga1702852009-03-27 00:12:24 -0700567 pending = ethoc_read(priv, INT_SOURCE);
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000568 pending &= mask;
569
Barry Grussling72aa8e12013-01-27 18:44:36 +0000570 if (unlikely(pending == 0))
Thierry Redinga1702852009-03-27 00:12:24 -0700571 return IRQ_NONE;
Thierry Redinga1702852009-03-27 00:12:24 -0700572
Thomas Chou50c54a52009-10-07 14:16:43 +0000573 ethoc_ack_irq(priv, pending);
Thierry Redinga1702852009-03-27 00:12:24 -0700574
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000575 /* We always handle the dropped packet interrupt */
Thierry Redinga1702852009-03-27 00:12:24 -0700576 if (pending & INT_MASK_BUSY) {
577 dev_err(&dev->dev, "packet dropped\n");
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000578 dev->stats.rx_dropped++;
Thierry Redinga1702852009-03-27 00:12:24 -0700579 }
580
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000581 /* Handle receive/transmit event by switching to polling */
582 if (pending & (INT_MASK_TX | INT_MASK_RX)) {
583 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
584 napi_schedule(&priv->napi);
Thierry Redinga1702852009-03-27 00:12:24 -0700585 }
586
Thierry Redinga1702852009-03-27 00:12:24 -0700587 return IRQ_HANDLED;
588}
589
590static int ethoc_get_mac_address(struct net_device *dev, void *addr)
591{
592 struct ethoc *priv = netdev_priv(dev);
593 u8 *mac = (u8 *)addr;
594 u32 reg;
595
596 reg = ethoc_read(priv, MAC_ADDR0);
597 mac[2] = (reg >> 24) & 0xff;
598 mac[3] = (reg >> 16) & 0xff;
599 mac[4] = (reg >> 8) & 0xff;
600 mac[5] = (reg >> 0) & 0xff;
601
602 reg = ethoc_read(priv, MAC_ADDR1);
603 mac[0] = (reg >> 8) & 0xff;
604 mac[1] = (reg >> 0) & 0xff;
605
606 return 0;
607}
608
609static int ethoc_poll(struct napi_struct *napi, int budget)
610{
611 struct ethoc *priv = container_of(napi, struct ethoc, napi);
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000612 int rx_work_done = 0;
613 int tx_work_done = 0;
Thierry Redinga1702852009-03-27 00:12:24 -0700614
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000615 rx_work_done = ethoc_rx(priv->netdev, budget);
616 tx_work_done = ethoc_tx(priv->netdev, budget);
617
618 if (rx_work_done < budget && tx_work_done < budget) {
Thierry Redinga1702852009-03-27 00:12:24 -0700619 napi_complete(napi);
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000620 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
Thierry Redinga1702852009-03-27 00:12:24 -0700621 }
622
Jonas Bonnfa98eb02010-11-25 02:30:29 +0000623 return rx_work_done;
Thierry Redinga1702852009-03-27 00:12:24 -0700624}
625
626static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
627{
Thierry Redinga1702852009-03-27 00:12:24 -0700628 struct ethoc *priv = bus->priv;
Jonas Bonn8dac4282010-11-25 02:30:30 +0000629 int i;
Thierry Redinga1702852009-03-27 00:12:24 -0700630
631 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
632 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
633
Barry Grussling72aa8e12013-01-27 18:44:36 +0000634 for (i = 0; i < 5; i++) {
Thierry Redinga1702852009-03-27 00:12:24 -0700635 u32 status = ethoc_read(priv, MIISTATUS);
636 if (!(status & MIISTATUS_BUSY)) {
637 u32 data = ethoc_read(priv, MIIRX_DATA);
638 /* reset MII command register */
639 ethoc_write(priv, MIICOMMAND, 0);
640 return data;
641 }
Barry Grussling72aa8e12013-01-27 18:44:36 +0000642 usleep_range(100, 200);
Thierry Redinga1702852009-03-27 00:12:24 -0700643 }
644
645 return -EBUSY;
646}
647
648static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
649{
Thierry Redinga1702852009-03-27 00:12:24 -0700650 struct ethoc *priv = bus->priv;
Jonas Bonn8dac4282010-11-25 02:30:30 +0000651 int i;
Thierry Redinga1702852009-03-27 00:12:24 -0700652
653 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
654 ethoc_write(priv, MIITX_DATA, val);
655 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
656
Barry Grussling72aa8e12013-01-27 18:44:36 +0000657 for (i = 0; i < 5; i++) {
Thierry Redinga1702852009-03-27 00:12:24 -0700658 u32 stat = ethoc_read(priv, MIISTATUS);
Jonas Bonnb46773d2010-06-11 02:47:39 +0000659 if (!(stat & MIISTATUS_BUSY)) {
660 /* reset MII command register */
661 ethoc_write(priv, MIICOMMAND, 0);
Thierry Redinga1702852009-03-27 00:12:24 -0700662 return 0;
Jonas Bonnb46773d2010-06-11 02:47:39 +0000663 }
Barry Grussling72aa8e12013-01-27 18:44:36 +0000664 usleep_range(100, 200);
Thierry Redinga1702852009-03-27 00:12:24 -0700665 }
666
667 return -EBUSY;
668}
669
Thierry Redinga1702852009-03-27 00:12:24 -0700670static void ethoc_mdio_poll(struct net_device *dev)
671{
672}
673
Bill Pembertona0a4efe2012-12-03 09:24:09 -0500674static int ethoc_mdio_probe(struct net_device *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700675{
676 struct ethoc *priv = netdev_priv(dev);
677 struct phy_device *phy;
Jonas Bonn637f33b82010-06-11 02:47:37 +0000678 int err;
Thierry Redinga1702852009-03-27 00:12:24 -0700679
Barry Grussling72aa8e12013-01-27 18:44:36 +0000680 if (priv->phy_id != -1)
Andrew Lunn7f854422016-01-06 20:11:18 +0100681 phy = mdiobus_get_phy(priv->mdio, priv->phy_id);
Barry Grussling72aa8e12013-01-27 18:44:36 +0000682 else
Jonas Bonn637f33b82010-06-11 02:47:37 +0000683 phy = phy_find_first(priv->mdio);
Thierry Redinga1702852009-03-27 00:12:24 -0700684
685 if (!phy) {
686 dev_err(&dev->dev, "no PHY found\n");
687 return -ENXIO;
688 }
689
Florian Fainellif9a8f832013-01-14 00:52:52 +0000690 err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
691 PHY_INTERFACE_MODE_GMII);
Jonas Bonn637f33b82010-06-11 02:47:37 +0000692 if (err) {
Thierry Redinga1702852009-03-27 00:12:24 -0700693 dev_err(&dev->dev, "could not attach to PHY\n");
Jonas Bonn637f33b82010-06-11 02:47:37 +0000694 return err;
Thierry Redinga1702852009-03-27 00:12:24 -0700695 }
696
697 priv->phy = phy;
Max Filippov445a48c2014-02-04 03:33:09 +0400698 phy->advertising &= ~(ADVERTISED_1000baseT_Full |
699 ADVERTISED_1000baseT_Half);
700 phy->supported &= ~(SUPPORTED_1000baseT_Full |
701 SUPPORTED_1000baseT_Half);
702
Thierry Redinga1702852009-03-27 00:12:24 -0700703 return 0;
704}
705
706static int ethoc_open(struct net_device *dev)
707{
708 struct ethoc *priv = netdev_priv(dev);
Thierry Redinga1702852009-03-27 00:12:24 -0700709 int ret;
710
711 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
712 dev->name, dev);
713 if (ret)
714 return ret;
715
David S. Miller5cf3e032010-07-07 18:23:19 -0700716 ethoc_init_ring(priv, dev->mem_start);
Thierry Redinga1702852009-03-27 00:12:24 -0700717 ethoc_reset(priv);
718
719 if (netif_queue_stopped(dev)) {
720 dev_dbg(&dev->dev, " resuming queue\n");
721 netif_wake_queue(dev);
722 } else {
723 dev_dbg(&dev->dev, " starting queue\n");
724 netif_start_queue(dev);
725 }
726
727 phy_start(priv->phy);
728 napi_enable(&priv->napi);
729
730 if (netif_msg_ifup(priv)) {
731 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
732 dev->base_addr, dev->mem_start, dev->mem_end);
733 }
734
735 return 0;
736}
737
738static int ethoc_stop(struct net_device *dev)
739{
740 struct ethoc *priv = netdev_priv(dev);
741
742 napi_disable(&priv->napi);
743
744 if (priv->phy)
745 phy_stop(priv->phy);
746
747 ethoc_disable_rx_and_tx(priv);
748 free_irq(dev->irq, dev);
749
750 if (!netif_queue_stopped(dev))
751 netif_stop_queue(dev);
752
753 return 0;
754}
755
756static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
757{
758 struct ethoc *priv = netdev_priv(dev);
759 struct mii_ioctl_data *mdio = if_mii(ifr);
760 struct phy_device *phy = NULL;
761
762 if (!netif_running(dev))
763 return -EINVAL;
764
765 if (cmd != SIOCGMIIPHY) {
766 if (mdio->phy_id >= PHY_MAX_ADDR)
767 return -ERANGE;
768
Andrew Lunn7f854422016-01-06 20:11:18 +0100769 phy = mdiobus_get_phy(priv->mdio, mdio->phy_id);
Thierry Redinga1702852009-03-27 00:12:24 -0700770 if (!phy)
771 return -ENODEV;
772 } else {
773 phy = priv->phy;
774 }
775
Richard Cochran28b04112010-07-17 08:48:55 +0000776 return phy_mii_ioctl(phy, ifr, cmd);
Thierry Redinga1702852009-03-27 00:12:24 -0700777}
778
Jiri Pirkoefc61a32013-01-06 03:25:45 +0000779static void ethoc_do_set_mac_address(struct net_device *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700780{
781 struct ethoc *priv = netdev_priv(dev);
Jiri Pirkoefc61a32013-01-06 03:25:45 +0000782 unsigned char *mac = dev->dev_addr;
Danny Kukawka939d2252012-02-17 05:43:29 +0000783
Thierry Redinga1702852009-03-27 00:12:24 -0700784 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
785 (mac[4] << 8) | (mac[5] << 0));
786 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
Jiri Pirkoefc61a32013-01-06 03:25:45 +0000787}
Thierry Redinga1702852009-03-27 00:12:24 -0700788
Jiri Pirkoefc61a32013-01-06 03:25:45 +0000789static int ethoc_set_mac_address(struct net_device *dev, void *p)
790{
791 const struct sockaddr *addr = p;
Danny Kukawka939d2252012-02-17 05:43:29 +0000792
Jiri Pirkoefc61a32013-01-06 03:25:45 +0000793 if (!is_valid_ether_addr(addr->sa_data))
794 return -EADDRNOTAVAIL;
795 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
796 ethoc_do_set_mac_address(dev);
Thierry Redinga1702852009-03-27 00:12:24 -0700797 return 0;
798}
799
800static void ethoc_set_multicast_list(struct net_device *dev)
801{
802 struct ethoc *priv = netdev_priv(dev);
803 u32 mode = ethoc_read(priv, MODER);
Jiri Pirko22bedad32010-04-01 21:22:57 +0000804 struct netdev_hw_addr *ha;
Thierry Redinga1702852009-03-27 00:12:24 -0700805 u32 hash[2] = { 0, 0 };
806
807 /* set loopback mode if requested */
808 if (dev->flags & IFF_LOOPBACK)
809 mode |= MODER_LOOP;
810 else
811 mode &= ~MODER_LOOP;
812
813 /* receive broadcast frames if requested */
814 if (dev->flags & IFF_BROADCAST)
815 mode &= ~MODER_BRO;
816 else
817 mode |= MODER_BRO;
818
819 /* enable promiscuous mode if requested */
820 if (dev->flags & IFF_PROMISC)
821 mode |= MODER_PRO;
822 else
823 mode &= ~MODER_PRO;
824
825 ethoc_write(priv, MODER, mode);
826
827 /* receive multicast frames */
828 if (dev->flags & IFF_ALLMULTI) {
829 hash[0] = 0xffffffff;
830 hash[1] = 0xffffffff;
831 } else {
Jiri Pirko22bedad32010-04-01 21:22:57 +0000832 netdev_for_each_mc_addr(ha, dev) {
833 u32 crc = ether_crc(ETH_ALEN, ha->addr);
Thierry Redinga1702852009-03-27 00:12:24 -0700834 int bit = (crc >> 26) & 0x3f;
835 hash[bit >> 5] |= 1 << (bit & 0x1f);
836 }
837 }
838
839 ethoc_write(priv, ETH_HASH0, hash[0]);
840 ethoc_write(priv, ETH_HASH1, hash[1]);
841}
842
843static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
844{
845 return -ENOSYS;
846}
847
848static void ethoc_tx_timeout(struct net_device *dev)
849{
850 struct ethoc *priv = netdev_priv(dev);
851 u32 pending = ethoc_read(priv, INT_SOURCE);
852 if (likely(pending))
853 ethoc_interrupt(dev->irq, dev);
854}
855
Stephen Hemminger613573252009-08-31 19:50:58 +0000856static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
Thierry Redinga1702852009-03-27 00:12:24 -0700857{
858 struct ethoc *priv = netdev_priv(dev);
859 struct ethoc_bd bd;
860 unsigned int entry;
861 void *dest;
862
Florian Fainelliee6c21b2016-07-12 16:04:36 -0700863 if (skb_put_padto(skb, ETHOC_ZLEN)) {
864 dev->stats.tx_errors++;
865 goto out_no_free;
866 }
867
Thierry Redinga1702852009-03-27 00:12:24 -0700868 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
Kulikov Vasiliy57616ee2010-07-05 02:13:31 +0000869 dev->stats.tx_errors++;
Patrick McHardy3790c8c2009-06-12 03:00:35 +0000870 goto out;
Thierry Redinga1702852009-03-27 00:12:24 -0700871 }
872
873 entry = priv->cur_tx % priv->num_tx;
874 spin_lock_irq(&priv->lock);
875 priv->cur_tx++;
876
877 ethoc_read_bd(priv, entry, &bd);
878 if (unlikely(skb->len < ETHOC_ZLEN))
879 bd.stat |= TX_BD_PAD;
880 else
881 bd.stat &= ~TX_BD_PAD;
882
Jonas Bonnf8555ad02010-06-11 02:47:35 +0000883 dest = priv->vma[entry];
Thierry Redinga1702852009-03-27 00:12:24 -0700884 memcpy_toio(dest, skb->data, skb->len);
885
886 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
887 bd.stat |= TX_BD_LEN(skb->len);
888 ethoc_write_bd(priv, entry, &bd);
889
890 bd.stat |= TX_BD_READY;
891 ethoc_write_bd(priv, entry, &bd);
892
893 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
894 dev_dbg(&dev->dev, "stopping queue\n");
895 netif_stop_queue(dev);
896 }
897
Thierry Redinga1702852009-03-27 00:12:24 -0700898 spin_unlock_irq(&priv->lock);
Richard Cochran68f51392011-06-12 02:19:04 +0000899 skb_tx_timestamp(skb);
Patrick McHardy3790c8c2009-06-12 03:00:35 +0000900out:
901 dev_kfree_skb(skb);
Florian Fainelliee6c21b2016-07-12 16:04:36 -0700902out_no_free:
Thierry Redinga1702852009-03-27 00:12:24 -0700903 return NETDEV_TX_OK;
904}
905
Max Filippov01cd7d52014-01-31 09:41:05 +0400906static int ethoc_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
907{
908 struct ethoc *priv = netdev_priv(dev);
909 struct phy_device *phydev = priv->phy;
910
911 if (!phydev)
912 return -EOPNOTSUPP;
913
914 return phy_ethtool_gset(phydev, cmd);
915}
916
917static int ethoc_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
918{
919 struct ethoc *priv = netdev_priv(dev);
920 struct phy_device *phydev = priv->phy;
921
922 if (!phydev)
923 return -EOPNOTSUPP;
924
925 return phy_ethtool_sset(phydev, cmd);
926}
927
Max Filippov11129092014-01-31 09:41:06 +0400928static int ethoc_get_regs_len(struct net_device *netdev)
929{
930 return ETH_END;
931}
932
933static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
934 void *p)
935{
936 struct ethoc *priv = netdev_priv(dev);
937 u32 *regs_buff = p;
938 unsigned i;
939
940 regs->version = 0;
941 for (i = 0; i < ETH_END / sizeof(u32); ++i)
942 regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
943}
944
Max Filippovbee7bac2014-01-31 09:41:07 +0400945static void ethoc_get_ringparam(struct net_device *dev,
946 struct ethtool_ringparam *ring)
947{
948 struct ethoc *priv = netdev_priv(dev);
949
950 ring->rx_max_pending = priv->num_bd - 1;
951 ring->rx_mini_max_pending = 0;
952 ring->rx_jumbo_max_pending = 0;
953 ring->tx_max_pending = priv->num_bd - 1;
954
955 ring->rx_pending = priv->num_rx;
956 ring->rx_mini_pending = 0;
957 ring->rx_jumbo_pending = 0;
958 ring->tx_pending = priv->num_tx;
959}
960
961static int ethoc_set_ringparam(struct net_device *dev,
962 struct ethtool_ringparam *ring)
963{
964 struct ethoc *priv = netdev_priv(dev);
965
966 if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
967 ring->tx_pending + ring->rx_pending > priv->num_bd)
968 return -EINVAL;
969 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
970 return -EINVAL;
971
972 if (netif_running(dev)) {
973 netif_tx_disable(dev);
974 ethoc_disable_rx_and_tx(priv);
975 ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
976 synchronize_irq(dev->irq);
977 }
978
979 priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
980 priv->num_rx = ring->rx_pending;
981 ethoc_init_ring(priv, dev->mem_start);
982
983 if (netif_running(dev)) {
984 ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
985 ethoc_enable_rx_and_tx(priv);
986 netif_wake_queue(dev);
987 }
988 return 0;
989}
990
Max Filippovfba91102014-01-31 09:41:04 +0400991const struct ethtool_ops ethoc_ethtool_ops = {
Max Filippov01cd7d52014-01-31 09:41:05 +0400992 .get_settings = ethoc_get_settings,
993 .set_settings = ethoc_set_settings,
Max Filippov11129092014-01-31 09:41:06 +0400994 .get_regs_len = ethoc_get_regs_len,
995 .get_regs = ethoc_get_regs,
Max Filippovfba91102014-01-31 09:41:04 +0400996 .get_link = ethtool_op_get_link,
Max Filippovbee7bac2014-01-31 09:41:07 +0400997 .get_ringparam = ethoc_get_ringparam,
998 .set_ringparam = ethoc_set_ringparam,
Max Filippovfba91102014-01-31 09:41:04 +0400999 .get_ts_info = ethtool_op_get_ts_info,
1000};
1001
Thierry Redinga1702852009-03-27 00:12:24 -07001002static const struct net_device_ops ethoc_netdev_ops = {
1003 .ndo_open = ethoc_open,
1004 .ndo_stop = ethoc_stop,
1005 .ndo_do_ioctl = ethoc_ioctl,
Thierry Redinga1702852009-03-27 00:12:24 -07001006 .ndo_set_mac_address = ethoc_set_mac_address,
Jiri Pirkoafc4b132011-08-16 06:29:01 +00001007 .ndo_set_rx_mode = ethoc_set_multicast_list,
Thierry Redinga1702852009-03-27 00:12:24 -07001008 .ndo_change_mtu = ethoc_change_mtu,
1009 .ndo_tx_timeout = ethoc_tx_timeout,
Thierry Redinga1702852009-03-27 00:12:24 -07001010 .ndo_start_xmit = ethoc_start_xmit,
1011};
1012
1013/**
Ben Hutchings49ce9c22012-07-10 10:56:00 +00001014 * ethoc_probe - initialize OpenCores ethernet MAC
Thierry Redinga1702852009-03-27 00:12:24 -07001015 * pdev: platform device
1016 */
Bill Pembertona0a4efe2012-12-03 09:24:09 -05001017static int ethoc_probe(struct platform_device *pdev)
Thierry Redinga1702852009-03-27 00:12:24 -07001018{
1019 struct net_device *netdev = NULL;
1020 struct resource *res = NULL;
1021 struct resource *mmio = NULL;
1022 struct resource *mem = NULL;
1023 struct ethoc *priv = NULL;
Jonas Bonnc527f812010-06-11 02:47:34 +00001024 int num_bd;
Thierry Redinga1702852009-03-27 00:12:24 -07001025 int ret = 0;
Danny Kukawka939d2252012-02-17 05:43:29 +00001026 bool random_mac = false;
Max Filippova13aff02014-02-04 03:33:10 +04001027 struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1028 u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
Thierry Redinga1702852009-03-27 00:12:24 -07001029
1030 /* allocate networking device */
1031 netdev = alloc_etherdev(sizeof(struct ethoc));
1032 if (!netdev) {
Thierry Redinga1702852009-03-27 00:12:24 -07001033 ret = -ENOMEM;
1034 goto out;
1035 }
1036
1037 SET_NETDEV_DEV(netdev, &pdev->dev);
1038 platform_set_drvdata(pdev, netdev);
1039
1040 /* obtain I/O memory space */
1041 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1042 if (!res) {
1043 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
1044 ret = -ENXIO;
1045 goto free;
1046 }
1047
1048 mmio = devm_request_mem_region(&pdev->dev, res->start,
Tobias Klauserd8645842010-01-15 01:48:22 -08001049 resource_size(res), res->name);
Julia Lawall463889e2009-07-27 06:13:30 +00001050 if (!mmio) {
Thierry Redinga1702852009-03-27 00:12:24 -07001051 dev_err(&pdev->dev, "cannot request I/O memory space\n");
1052 ret = -ENXIO;
1053 goto free;
1054 }
1055
1056 netdev->base_addr = mmio->start;
1057
1058 /* obtain buffer memory space */
1059 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
Thomas Chou0baa0802009-10-04 23:33:20 +00001060 if (res) {
1061 mem = devm_request_mem_region(&pdev->dev, res->start,
Tobias Klauserd8645842010-01-15 01:48:22 -08001062 resource_size(res), res->name);
Thomas Chou0baa0802009-10-04 23:33:20 +00001063 if (!mem) {
1064 dev_err(&pdev->dev, "cannot request memory space\n");
1065 ret = -ENXIO;
1066 goto free;
1067 }
1068
1069 netdev->mem_start = mem->start;
1070 netdev->mem_end = mem->end;
Thierry Redinga1702852009-03-27 00:12:24 -07001071 }
1072
Thierry Redinga1702852009-03-27 00:12:24 -07001073
1074 /* obtain device IRQ number */
1075 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1076 if (!res) {
1077 dev_err(&pdev->dev, "cannot obtain IRQ\n");
1078 ret = -ENXIO;
1079 goto free;
1080 }
1081
1082 netdev->irq = res->start;
1083
1084 /* setup driver-private data */
1085 priv = netdev_priv(netdev);
1086 priv->netdev = netdev;
Thomas Chou0baa0802009-10-04 23:33:20 +00001087 priv->dma_alloc = 0;
Joe Perches28f65c112011-06-09 09:13:32 -07001088 priv->io_region_size = resource_size(mmio);
Thierry Redinga1702852009-03-27 00:12:24 -07001089
1090 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
Tobias Klauserd8645842010-01-15 01:48:22 -08001091 resource_size(mmio));
Thierry Redinga1702852009-03-27 00:12:24 -07001092 if (!priv->iobase) {
1093 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
1094 ret = -ENXIO;
Florian Fainelli386512d2016-07-12 16:04:35 -07001095 goto free;
Thierry Redinga1702852009-03-27 00:12:24 -07001096 }
1097
Thomas Chou0baa0802009-10-04 23:33:20 +00001098 if (netdev->mem_end) {
1099 priv->membase = devm_ioremap_nocache(&pdev->dev,
Tobias Klauserd8645842010-01-15 01:48:22 -08001100 netdev->mem_start, resource_size(mem));
Thomas Chou0baa0802009-10-04 23:33:20 +00001101 if (!priv->membase) {
1102 dev_err(&pdev->dev, "cannot remap memory space\n");
1103 ret = -ENXIO;
Florian Fainelli386512d2016-07-12 16:04:35 -07001104 goto free;
Thomas Chou0baa0802009-10-04 23:33:20 +00001105 }
1106 } else {
1107 /* Allocate buffer memory */
Jonas Bonna71fba92010-06-11 02:47:40 +00001108 priv->membase = dmam_alloc_coherent(&pdev->dev,
Thomas Chou0baa0802009-10-04 23:33:20 +00001109 buffer_size, (void *)&netdev->mem_start,
1110 GFP_KERNEL);
1111 if (!priv->membase) {
1112 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
1113 buffer_size);
1114 ret = -ENOMEM;
Florian Fainelli386512d2016-07-12 16:04:35 -07001115 goto free;
Thomas Chou0baa0802009-10-04 23:33:20 +00001116 }
1117 netdev->mem_end = netdev->mem_start + buffer_size;
1118 priv->dma_alloc = buffer_size;
Thierry Redinga1702852009-03-27 00:12:24 -07001119 }
1120
Max Filippov06e60e592015-09-22 14:27:16 +03001121 priv->big_endian = pdata ? pdata->big_endian :
1122 of_device_is_big_endian(pdev->dev.of_node);
1123
Jonas Bonnc527f812010-06-11 02:47:34 +00001124 /* calculate the number of TX/RX buffers, maximum 128 supported */
1125 num_bd = min_t(unsigned int,
1126 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
Jonas Bonn6a632622010-11-25 02:30:32 +00001127 if (num_bd < 4) {
1128 ret = -ENODEV;
Florian Fainelli386512d2016-07-12 16:04:35 -07001129 goto free;
Jonas Bonn6a632622010-11-25 02:30:32 +00001130 }
Max Filippovbee7bac2014-01-31 09:41:07 +04001131 priv->num_bd = num_bd;
Jonas Bonn6a632622010-11-25 02:30:32 +00001132 /* num_tx must be a power of two */
1133 priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
Jonas Bonnc527f812010-06-11 02:47:34 +00001134 priv->num_rx = num_bd - priv->num_tx;
1135
Jonas Bonn6a632622010-11-25 02:30:32 +00001136 dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
1137 priv->num_tx, priv->num_rx);
1138
Barry Grussling72aa8e12013-01-27 18:44:36 +00001139 priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void *), GFP_KERNEL);
Jonas Bonnf8555ad02010-06-11 02:47:35 +00001140 if (!priv->vma) {
1141 ret = -ENOMEM;
Florian Fainelli386512d2016-07-12 16:04:35 -07001142 goto free;
Jonas Bonnf8555ad02010-06-11 02:47:35 +00001143 }
1144
Thierry Redinga1702852009-03-27 00:12:24 -07001145 /* Allow the platform setup code to pass in a MAC address. */
Max Filippova13aff02014-02-04 03:33:10 +04001146 if (pdata) {
Thierry Redinga1702852009-03-27 00:12:24 -07001147 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
1148 priv->phy_id = pdata->phy_id;
Jonas Bonne0f42582010-11-25 02:30:25 +00001149 } else {
Barry Grussling72aa8e12013-01-27 18:44:36 +00001150 const uint8_t *mac;
Jonas Bonne0f42582010-11-25 02:30:25 +00001151
1152 mac = of_get_property(pdev->dev.of_node,
1153 "local-mac-address",
1154 NULL);
1155 if (mac)
1156 memcpy(netdev->dev_addr, mac, IFHWADDRLEN);
Tobias Klauser444c5f92015-09-09 11:24:29 +02001157 priv->phy_id = -1;
Thierry Redinga1702852009-03-27 00:12:24 -07001158 }
1159
1160 /* Check that the given MAC address is valid. If it isn't, read the
Barry Grussling72aa8e12013-01-27 18:44:36 +00001161 * current MAC from the controller.
1162 */
Thierry Redinga1702852009-03-27 00:12:24 -07001163 if (!is_valid_ether_addr(netdev->dev_addr))
1164 ethoc_get_mac_address(netdev, netdev->dev_addr);
1165
1166 /* Check the MAC again for validity, if it still isn't choose and
Barry Grussling72aa8e12013-01-27 18:44:36 +00001167 * program a random one.
1168 */
Danny Kukawka939d2252012-02-17 05:43:29 +00001169 if (!is_valid_ether_addr(netdev->dev_addr)) {
Joe Perches7efd26d2012-07-12 19:33:06 +00001170 eth_random_addr(netdev->dev_addr);
Danny Kukawka939d2252012-02-17 05:43:29 +00001171 random_mac = true;
1172 }
Thierry Redinga1702852009-03-27 00:12:24 -07001173
Jiri Pirkoefc61a32013-01-06 03:25:45 +00001174 ethoc_do_set_mac_address(netdev);
Danny Kukawka939d2252012-02-17 05:43:29 +00001175
1176 if (random_mac)
Jiri Pirkoe41b2d72013-01-01 03:30:15 +00001177 netdev->addr_assign_type = NET_ADDR_RANDOM;
Thierry Redinga1702852009-03-27 00:12:24 -07001178
Max Filippova13aff02014-02-04 03:33:10 +04001179 /* Allow the platform setup code to adjust MII management bus clock. */
1180 if (!eth_clkfreq) {
1181 struct clk *clk = devm_clk_get(&pdev->dev, NULL);
1182
1183 if (!IS_ERR(clk)) {
1184 priv->clk = clk;
1185 clk_prepare_enable(clk);
1186 eth_clkfreq = clk_get_rate(clk);
1187 }
1188 }
1189 if (eth_clkfreq) {
1190 u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);
1191
1192 if (!clkdiv)
1193 clkdiv = 2;
1194 dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
1195 ethoc_write(priv, MIIMODER,
1196 (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
1197 clkdiv);
1198 }
1199
Thierry Redinga1702852009-03-27 00:12:24 -07001200 /* register MII bus */
1201 priv->mdio = mdiobus_alloc();
1202 if (!priv->mdio) {
1203 ret = -ENOMEM;
Colin Ian Kingbfa49cf2016-06-01 14:16:50 +01001204 goto free2;
Thierry Redinga1702852009-03-27 00:12:24 -07001205 }
1206
1207 priv->mdio->name = "ethoc-mdio";
1208 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1209 priv->mdio->name, pdev->id);
1210 priv->mdio->read = ethoc_mdio_read;
1211 priv->mdio->write = ethoc_mdio_write;
Thierry Redinga1702852009-03-27 00:12:24 -07001212 priv->mdio->priv = priv;
1213
Thierry Redinga1702852009-03-27 00:12:24 -07001214 ret = mdiobus_register(priv->mdio);
1215 if (ret) {
1216 dev_err(&netdev->dev, "failed to register MDIO bus\n");
Colin Ian Kingbfa49cf2016-06-01 14:16:50 +01001217 goto free2;
Thierry Redinga1702852009-03-27 00:12:24 -07001218 }
1219
1220 ret = ethoc_mdio_probe(netdev);
1221 if (ret) {
1222 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1223 goto error;
1224 }
1225
Thierry Redinga1702852009-03-27 00:12:24 -07001226 /* setup the net_device structure */
1227 netdev->netdev_ops = &ethoc_netdev_ops;
1228 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1229 netdev->features |= 0;
Max Filippovfba91102014-01-31 09:41:04 +04001230 netdev->ethtool_ops = &ethoc_ethtool_ops;
Thierry Redinga1702852009-03-27 00:12:24 -07001231
1232 /* setup NAPI */
Thierry Redinga1702852009-03-27 00:12:24 -07001233 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1234
Thierry Redinga1702852009-03-27 00:12:24 -07001235 spin_lock_init(&priv->lock);
1236
1237 ret = register_netdev(netdev);
1238 if (ret < 0) {
1239 dev_err(&netdev->dev, "failed to register interface\n");
Thomas Chouee02a4e2010-05-23 16:44:02 +00001240 goto error2;
Thierry Redinga1702852009-03-27 00:12:24 -07001241 }
1242
1243 goto out;
1244
Thomas Chouee02a4e2010-05-23 16:44:02 +00001245error2:
1246 netif_napi_del(&priv->napi);
Thierry Redinga1702852009-03-27 00:12:24 -07001247error:
1248 mdiobus_unregister(priv->mdio);
Thierry Redinga1702852009-03-27 00:12:24 -07001249 mdiobus_free(priv->mdio);
Colin Ian Kingbfa49cf2016-06-01 14:16:50 +01001250free2:
Max Filippova13aff02014-02-04 03:33:10 +04001251 if (priv->clk)
1252 clk_disable_unprepare(priv->clk);
Colin Ian Kingbfa49cf2016-06-01 14:16:50 +01001253free:
Thierry Redinga1702852009-03-27 00:12:24 -07001254 free_netdev(netdev);
1255out:
1256 return ret;
1257}
1258
1259/**
Ben Hutchings49ce9c22012-07-10 10:56:00 +00001260 * ethoc_remove - shutdown OpenCores ethernet MAC
Thierry Redinga1702852009-03-27 00:12:24 -07001261 * @pdev: platform device
1262 */
Bill Pembertona0a4efe2012-12-03 09:24:09 -05001263static int ethoc_remove(struct platform_device *pdev)
Thierry Redinga1702852009-03-27 00:12:24 -07001264{
1265 struct net_device *netdev = platform_get_drvdata(pdev);
1266 struct ethoc *priv = netdev_priv(netdev);
1267
Thierry Redinga1702852009-03-27 00:12:24 -07001268 if (netdev) {
Thomas Chouee02a4e2010-05-23 16:44:02 +00001269 netif_napi_del(&priv->napi);
Thierry Redinga1702852009-03-27 00:12:24 -07001270 phy_disconnect(priv->phy);
1271 priv->phy = NULL;
1272
1273 if (priv->mdio) {
1274 mdiobus_unregister(priv->mdio);
Thierry Redinga1702852009-03-27 00:12:24 -07001275 mdiobus_free(priv->mdio);
1276 }
Max Filippova13aff02014-02-04 03:33:10 +04001277 if (priv->clk)
1278 clk_disable_unprepare(priv->clk);
Thierry Redinga1702852009-03-27 00:12:24 -07001279 unregister_netdev(netdev);
1280 free_netdev(netdev);
1281 }
1282
1283 return 0;
1284}
1285
1286#ifdef CONFIG_PM
1287static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1288{
1289 return -ENOSYS;
1290}
1291
1292static int ethoc_resume(struct platform_device *pdev)
1293{
1294 return -ENOSYS;
1295}
1296#else
1297# define ethoc_suspend NULL
1298# define ethoc_resume NULL
1299#endif
1300
Fabian Frederickfa2b1832015-03-17 19:37:35 +01001301static const struct of_device_id ethoc_match[] = {
Grant Likelyc9e358d2011-01-21 09:24:48 -07001302 { .compatible = "opencores,ethoc", },
Jonas Bonne0f42582010-11-25 02:30:25 +00001303 {},
1304};
1305MODULE_DEVICE_TABLE(of, ethoc_match);
Jonas Bonne0f42582010-11-25 02:30:25 +00001306
Thierry Redinga1702852009-03-27 00:12:24 -07001307static struct platform_driver ethoc_driver = {
1308 .probe = ethoc_probe,
Bill Pembertona0a4efe2012-12-03 09:24:09 -05001309 .remove = ethoc_remove,
Thierry Redinga1702852009-03-27 00:12:24 -07001310 .suspend = ethoc_suspend,
1311 .resume = ethoc_resume,
1312 .driver = {
1313 .name = "ethoc",
Jonas Bonne0f42582010-11-25 02:30:25 +00001314 .of_match_table = ethoc_match,
Thierry Redinga1702852009-03-27 00:12:24 -07001315 },
1316};
1317
Axel Lindb62f682011-11-27 16:44:17 +00001318module_platform_driver(ethoc_driver);
Thierry Redinga1702852009-03-27 00:12:24 -07001319
1320MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1321MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1322MODULE_LICENSE("GPL v2");
1323