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Ikjoon Jang043ebcf2020-08-26 16:54:50 +08001# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Serial NOR flash controller for MediaTek ARM SoCs
8
9maintainers:
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
12
13description: |
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
17 for devices other than SPI NOR flash due to limited transfer
18 capability of this controller.
19
20allOf:
Rob Herring22a41e92022-03-25 16:56:52 -050021 - $ref: /schemas/spi/spi-controller.yaml#
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080022
23properties:
24 compatible:
25 oneOf:
Allen-KH Cheng82cef0a2022-07-15 19:54:43 +080026 - enum:
27 - mediatek,mt8173-nor
28 - mediatek,mt8186-nor
29 - mediatek,mt8192-nor
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080030 - items:
31 - enum:
32 - mediatek,mt2701-nor
33 - mediatek,mt2712-nor
34 - mediatek,mt7622-nor
35 - mediatek,mt7623-nor
36 - mediatek,mt7629-nor
Seiya Wang5ac1b902021-03-16 19:14:38 +080037 - mediatek,mt8195-nor
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080038 - const: mediatek,mt8173-nor
Allen-KH Cheng82cef0a2022-07-15 19:54:43 +080039 - items:
40 - enum:
41 - mediatek,mt8188-nor
42 - const: mediatek,mt8186-nor
43
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080044 reg:
45 maxItems: 1
46
47 interrupts:
48 maxItems: 1
49
50 clocks:
Tinghan Shen6008cb42021-12-20 20:18:23 +080051 minItems: 2
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080052 items:
53 - description: clock used for spi bus
54 - description: clock used for controller
Tinghan Shen6008cb42021-12-20 20:18:23 +080055 - description: clock used for nor dma bus. this depends on hardware
56 design, so this is optional.
Guochun Maoceab11a2022-01-18 22:28:17 +080057 - description: clock used for controller axi slave bus.
58 this depends on hardware design, so it is optional.
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080059
60 clock-names:
Tinghan Shen6008cb42021-12-20 20:18:23 +080061 minItems: 2
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080062 items:
63 - const: spi
64 - const: sf
Tinghan Shen6008cb42021-12-20 20:18:23 +080065 - const: axi
Guochun Maoceab11a2022-01-18 22:28:17 +080066 - const: axi_s
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080067
68required:
69 - compatible
70 - reg
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080071 - clocks
72 - clock-names
73
74unevaluatedProperties: false
75
76examples:
77 - |
78 #include <dt-bindings/clock/mt8173-clk.h>
79
80 soc {
81 #address-cells = <2>;
82 #size-cells = <2>;
83
84 nor_flash: spi@1100d000 {
85 compatible = "mediatek,mt8173-nor";
86 reg = <0 0x1100d000 0 0xe0>;
Rob Herring3e718b42022-01-06 12:25:17 -060087 interrupts = <1>;
Ikjoon Jang043ebcf2020-08-26 16:54:50 +080088 clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
89 clock-names = "spi", "sf";
90 #address-cells = <1>;
91 #size-cells = <0>;
92
93 flash@0 {
94 compatible = "jedec,spi-nor";
95 reg = <0>;
96 };
97 };
98 };