Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Power Management Service Unit(PMSU) support for Armada 370/XP platforms. |
| 3 | * |
| 4 | * Copyright (C) 2012 Marvell |
| 5 | * |
| 6 | * Yehuda Yitschak <yehuday@marvell.com> |
| 7 | * Gregory Clement <gregory.clement@free-electrons.com> |
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 9 | * |
| 10 | * This file is licensed under the terms of the GNU General Public |
| 11 | * License version 2. This program is licensed "as is" without any |
| 12 | * warranty of any kind, whether express or implied. |
| 13 | * |
| 14 | * The Armada 370 and Armada XP SOCs have a power management service |
| 15 | * unit which is responsible for powering down and waking up CPUs and |
| 16 | * other SOC units |
| 17 | */ |
| 18 | |
Thomas Petazzoni | bd045a1 | 2014-04-14 15:50:30 +0200 | [diff] [blame] | 19 | #define pr_fmt(fmt) "mvebu-pmsu: " fmt |
| 20 | |
Thomas Petazzoni | a509ea8 | 2014-07-09 17:45:10 +0200 | [diff] [blame] | 21 | #include <linux/clk.h> |
Gregory CLEMENT | d163ee1 | 2014-04-14 17:10:12 +0200 | [diff] [blame] | 22 | #include <linux/cpu_pm.h> |
Thomas Petazzoni | a509ea8 | 2014-07-09 17:45:10 +0200 | [diff] [blame] | 23 | #include <linux/delay.h> |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 24 | #include <linux/init.h> |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 25 | #include <linux/io.h> |
Gregory CLEMENT | 3e32842 | 2014-07-23 15:00:39 +0200 | [diff] [blame] | 26 | #include <linux/kernel.h> |
Gregory CLEMENT | 3076cc5 | 2014-07-23 15:00:40 +0200 | [diff] [blame] | 27 | #include <linux/mbus.h> |
Ben Dooks | 53e2fd8 | 2016-06-07 20:03:45 +0100 | [diff] [blame] | 28 | #include <linux/mvebu-pmsu.h> |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 29 | #include <linux/of_address.h> |
Thomas Petazzoni | a509ea8 | 2014-07-09 17:45:10 +0200 | [diff] [blame] | 30 | #include <linux/of_device.h> |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 31 | #include <linux/platform_device.h> |
Thomas Petazzoni | 49754ff | 2014-04-14 15:50:29 +0200 | [diff] [blame] | 32 | #include <linux/resource.h> |
Thomas Petazzoni | a509ea8 | 2014-07-09 17:45:10 +0200 | [diff] [blame] | 33 | #include <linux/slab.h> |
Gregory CLEMENT | 3e32842 | 2014-07-23 15:00:39 +0200 | [diff] [blame] | 34 | #include <linux/smp.h> |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 35 | #include <asm/cacheflush.h> |
| 36 | #include <asm/cp15.h> |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 37 | #include <asm/smp_scu.h> |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 38 | #include <asm/smp_plat.h> |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 39 | #include <asm/suspend.h> |
| 40 | #include <asm/tlbflush.h> |
Thomas Petazzoni | 49754ff | 2014-04-14 15:50:29 +0200 | [diff] [blame] | 41 | #include "common.h" |
Ben Dooks | 53e2fd8 | 2016-06-07 20:03:45 +0100 | [diff] [blame] | 42 | #include "pmsu.h" |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 43 | |
Gregory CLEMENT | 0c3acc7 | 2014-04-14 15:50:31 +0200 | [diff] [blame] | 44 | #define PMSU_BASE_OFFSET 0x100 |
| 45 | #define PMSU_REG_SIZE 0x1000 |
| 46 | |
Gregory CLEMENT | f713c7e | 2014-04-14 17:10:10 +0200 | [diff] [blame] | 47 | /* PMSU MP registers */ |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 48 | #define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104) |
| 49 | #define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18) |
| 50 | #define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16) |
| 51 | #define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20) |
| 52 | |
| 53 | #define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108) |
| 54 | |
| 55 | #define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0) |
| 56 | |
| 57 | #define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c) |
| 58 | #define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16) |
| 59 | #define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17) |
| 60 | #define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20) |
| 61 | #define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21) |
| 62 | #define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22) |
| 63 | #define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24) |
| 64 | #define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25) |
| 65 | |
Thomas Petazzoni | a509ea8 | 2014-07-09 17:45:10 +0200 | [diff] [blame] | 66 | #define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120) |
| 67 | #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE BIT(1) |
| 68 | #define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK BIT(17) |
| 69 | |
Gregory CLEMENT | f713c7e | 2014-04-14 17:10:10 +0200 | [diff] [blame] | 70 | #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124) |
| 71 | |
| 72 | /* PMSU fabric registers */ |
| 73 | #define L2C_NFABRIC_PM_CTL 0x4 |
| 74 | #define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20) |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 75 | |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 76 | /* PMSU delay registers */ |
| 77 | #define PMSU_POWERDOWN_DELAY 0xF04 |
| 78 | #define PMSU_POWERDOWN_DELAY_PMU BIT(1) |
| 79 | #define PMSU_POWERDOWN_DELAY_MASK 0xFFFE |
| 80 | #define PMSU_DFLT_ARMADA38X_DELAY 0x64 |
| 81 | |
| 82 | /* CA9 MPcore SoC Control registers */ |
| 83 | |
| 84 | #define MPCORE_RESET_CTL 0x64 |
| 85 | #define MPCORE_RESET_CTL_L2 BIT(0) |
| 86 | #define MPCORE_RESET_CTL_DEBUG BIT(16) |
| 87 | |
Gregory CLEMENT | 3076cc5 | 2014-07-23 15:00:40 +0200 | [diff] [blame] | 88 | #define SRAM_PHYS_BASE 0xFFFF0000 |
| 89 | #define BOOTROM_BASE 0xFFF00000 |
| 90 | #define BOOTROM_SIZE 0x100000 |
| 91 | |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 92 | #define ARMADA_370_CRYPT0_ENG_TARGET 0x9 |
| 93 | #define ARMADA_370_CRYPT0_ENG_ATTR 0x1 |
| 94 | |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 95 | extern void ll_disable_coherency(void); |
| 96 | extern void ll_enable_coherency(void); |
| 97 | |
Thomas Petazzoni | 6509dc7 | 2014-06-30 14:09:25 +0200 | [diff] [blame] | 98 | extern void armada_370_xp_cpu_resume(void); |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 99 | extern void armada_38x_cpu_resume(void); |
| 100 | |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 101 | static phys_addr_t pmsu_mp_phys_base; |
| 102 | static void __iomem *pmsu_mp_base; |
Thomas Petazzoni | 6509dc7 | 2014-06-30 14:09:25 +0200 | [diff] [blame] | 103 | |
Gregory CLEMENT | 752a993 | 2014-07-23 15:00:44 +0200 | [diff] [blame] | 104 | static void *mvebu_cpu_resume; |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 105 | |
Uwe Kleine-König | 444d2d3 | 2015-02-18 21:19:56 +0100 | [diff] [blame] | 106 | static const struct of_device_id of_pmsu_table[] = { |
Gregory CLEMENT | 0c3acc7 | 2014-04-14 15:50:31 +0200 | [diff] [blame] | 107 | { .compatible = "marvell,armada-370-pmsu", }, |
| 108 | { .compatible = "marvell,armada-370-xp-pmsu", }, |
Thomas Petazzoni | b4bca24 | 2014-04-14 15:54:04 +0200 | [diff] [blame] | 109 | { .compatible = "marvell,armada-380-pmsu", }, |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 110 | { /* end of list */ }, |
| 111 | }; |
| 112 | |
Thomas Petazzoni | 05ad690 | 2014-04-14 15:53:58 +0200 | [diff] [blame] | 113 | void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) |
Gregory CLEMENT | 02e7b06 | 2014-04-14 15:50:33 +0200 | [diff] [blame] | 114 | { |
Florian Fainelli | 64fc2a9 | 2017-01-15 03:59:29 +0100 | [diff] [blame] | 115 | writel(__pa_symbol(boot_addr), pmsu_mp_base + |
Gregory CLEMENT | 02e7b06 | 2014-04-14 15:50:33 +0200 | [diff] [blame] | 116 | PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); |
| 117 | } |
| 118 | |
Ethan Tuttle | d0d378f | 2018-06-19 21:31:08 -0700 | [diff] [blame] | 119 | extern unsigned char mvebu_boot_wa_start[]; |
| 120 | extern unsigned char mvebu_boot_wa_end[]; |
Gregory CLEMENT | 3076cc5 | 2014-07-23 15:00:40 +0200 | [diff] [blame] | 121 | |
| 122 | /* |
| 123 | * This function sets up the boot address workaround needed for SMP |
| 124 | * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the |
| 125 | * BootROM Mbus window, and instead remaps a crypto SRAM into which a |
| 126 | * custom piece of code is copied to replace the problematic BootROM. |
| 127 | */ |
| 128 | int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target, |
| 129 | unsigned int crypto_eng_attribute, |
| 130 | phys_addr_t resume_addr_reg) |
| 131 | { |
| 132 | void __iomem *sram_virt_base; |
Ethan Tuttle | d0d378f | 2018-06-19 21:31:08 -0700 | [diff] [blame] | 133 | u32 code_len = mvebu_boot_wa_end - mvebu_boot_wa_start; |
Gregory CLEMENT | 3076cc5 | 2014-07-23 15:00:40 +0200 | [diff] [blame] | 134 | |
| 135 | mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE); |
| 136 | mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute, |
| 137 | SRAM_PHYS_BASE, SZ_64K); |
| 138 | |
| 139 | sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K); |
| 140 | if (!sram_virt_base) { |
| 141 | pr_err("Unable to map SRAM to setup the boot address WA\n"); |
| 142 | return -ENOMEM; |
| 143 | } |
| 144 | |
| 145 | memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len); |
| 146 | |
| 147 | /* |
| 148 | * The last word of the code copied in SRAM must contain the |
| 149 | * physical base address of the PMSU register. We |
| 150 | * intentionally store this address in the native endianness |
| 151 | * of the system. |
| 152 | */ |
| 153 | __raw_writel((unsigned long)resume_addr_reg, |
| 154 | sram_virt_base + code_len - 4); |
| 155 | |
| 156 | iounmap(sram_virt_base); |
| 157 | |
| 158 | return 0; |
| 159 | } |
| 160 | |
Gregory CLEMENT | 898ef3e | 2014-07-23 15:00:42 +0200 | [diff] [blame] | 161 | static int __init mvebu_v7_pmsu_init(void) |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 162 | { |
| 163 | struct device_node *np; |
Thomas Petazzoni | bd045a1 | 2014-04-14 15:50:30 +0200 | [diff] [blame] | 164 | struct resource res; |
| 165 | int ret = 0; |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 166 | |
| 167 | np = of_find_matching_node(NULL, of_pmsu_table); |
Thomas Petazzoni | bd045a1 | 2014-04-14 15:50:30 +0200 | [diff] [blame] | 168 | if (!np) |
| 169 | return 0; |
| 170 | |
| 171 | pr_info("Initializing Power Management Service Unit\n"); |
| 172 | |
| 173 | if (of_address_to_resource(np, 0, &res)) { |
| 174 | pr_err("unable to get resource\n"); |
| 175 | ret = -ENOENT; |
| 176 | goto out; |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 177 | } |
| 178 | |
Gregory CLEMENT | 0c3acc7 | 2014-04-14 15:50:31 +0200 | [diff] [blame] | 179 | if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) { |
| 180 | pr_warn(FW_WARN "deprecated pmsu binding\n"); |
| 181 | res.start = res.start - PMSU_BASE_OFFSET; |
| 182 | res.end = res.start + PMSU_REG_SIZE - 1; |
| 183 | } |
| 184 | |
Thomas Petazzoni | bd045a1 | 2014-04-14 15:50:30 +0200 | [diff] [blame] | 185 | if (!request_mem_region(res.start, resource_size(&res), |
| 186 | np->full_name)) { |
| 187 | pr_err("unable to request region\n"); |
| 188 | ret = -EBUSY; |
| 189 | goto out; |
| 190 | } |
| 191 | |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 192 | pmsu_mp_phys_base = res.start; |
| 193 | |
Thomas Petazzoni | bd045a1 | 2014-04-14 15:50:30 +0200 | [diff] [blame] | 194 | pmsu_mp_base = ioremap(res.start, resource_size(&res)); |
| 195 | if (!pmsu_mp_base) { |
| 196 | pr_err("unable to map registers\n"); |
| 197 | release_mem_region(res.start, resource_size(&res)); |
| 198 | ret = -ENOMEM; |
| 199 | goto out; |
| 200 | } |
| 201 | |
| 202 | out: |
| 203 | of_node_put(np); |
| 204 | return ret; |
Gregory CLEMENT | 7444dad | 2012-08-02 11:17:51 +0300 | [diff] [blame] | 205 | } |
| 206 | |
Gregory CLEMENT | 898ef3e | 2014-07-23 15:00:42 +0200 | [diff] [blame] | 207 | static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void) |
Gregory CLEMENT | f713c7e | 2014-04-14 17:10:10 +0200 | [diff] [blame] | 208 | { |
| 209 | u32 reg; |
| 210 | |
| 211 | if (pmsu_mp_base == NULL) |
| 212 | return; |
| 213 | |
| 214 | /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */ |
| 215 | reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); |
| 216 | reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN; |
| 217 | writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); |
| 218 | } |
| 219 | |
Gregory CLEMENT | 5da964e | 2014-07-23 15:00:45 +0200 | [diff] [blame] | 220 | enum pmsu_idle_prepare_flags { |
| 221 | PMSU_PREPARE_NORMAL = 0, |
| 222 | PMSU_PREPARE_DEEP_IDLE = BIT(0), |
| 223 | PMSU_PREPARE_SNOOP_DISABLE = BIT(1), |
| 224 | }; |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 225 | |
| 226 | /* No locking is needed because we only access per-CPU registers */ |
Gregory CLEMENT | 5da964e | 2014-07-23 15:00:45 +0200 | [diff] [blame] | 227 | static int mvebu_v7_pmsu_idle_prepare(unsigned long flags) |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 228 | { |
| 229 | unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); |
| 230 | u32 reg; |
| 231 | |
| 232 | if (pmsu_mp_base == NULL) |
Thomas Petazzoni | bbb9228 | 2014-05-30 22:18:15 +0200 | [diff] [blame] | 233 | return -EINVAL; |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 234 | |
| 235 | /* |
| 236 | * Adjust the PMSU configuration to wait for WFI signal, enable |
| 237 | * IRQ and FIQ as wakeup events, set wait for snoop queue empty |
| 238 | * indication and mask IRQ and FIQ from CPU |
| 239 | */ |
| 240 | reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); |
| 241 | reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT | |
| 242 | PMSU_STATUS_AND_MASK_IRQ_WAKEUP | |
| 243 | PMSU_STATUS_AND_MASK_FIQ_WAKEUP | |
| 244 | PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT | |
| 245 | PMSU_STATUS_AND_MASK_IRQ_MASK | |
| 246 | PMSU_STATUS_AND_MASK_FIQ_MASK; |
| 247 | writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); |
| 248 | |
| 249 | reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); |
| 250 | /* ask HW to power down the L2 Cache if needed */ |
Gregory CLEMENT | 5da964e | 2014-07-23 15:00:45 +0200 | [diff] [blame] | 251 | if (flags & PMSU_PREPARE_DEEP_IDLE) |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 252 | reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN; |
| 253 | |
| 254 | /* request power down */ |
| 255 | reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ; |
| 256 | writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); |
| 257 | |
Gregory CLEMENT | 5da964e | 2014-07-23 15:00:45 +0200 | [diff] [blame] | 258 | if (flags & PMSU_PREPARE_SNOOP_DISABLE) { |
| 259 | /* Disable snoop disable by HW - SW is taking care of it */ |
| 260 | reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); |
| 261 | reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP; |
| 262 | writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); |
| 263 | } |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 264 | |
Gregory CLEMENT | 9ce3588 | 2014-07-23 15:00:38 +0200 | [diff] [blame] | 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | int armada_370_xp_pmsu_idle_enter(unsigned long deepidle) |
| 269 | { |
Gregory CLEMENT | 5da964e | 2014-07-23 15:00:45 +0200 | [diff] [blame] | 270 | unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE; |
Gregory CLEMENT | 9ce3588 | 2014-07-23 15:00:38 +0200 | [diff] [blame] | 271 | int ret; |
| 272 | |
Gregory CLEMENT | 5da964e | 2014-07-23 15:00:45 +0200 | [diff] [blame] | 273 | if (deepidle) |
| 274 | flags |= PMSU_PREPARE_DEEP_IDLE; |
| 275 | |
| 276 | ret = mvebu_v7_pmsu_idle_prepare(flags); |
Gregory CLEMENT | 9ce3588 | 2014-07-23 15:00:38 +0200 | [diff] [blame] | 277 | if (ret) |
| 278 | return ret; |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 279 | |
| 280 | v7_exit_coherency_flush(all); |
| 281 | |
| 282 | ll_disable_coherency(); |
| 283 | |
| 284 | dsb(); |
| 285 | |
| 286 | wfi(); |
| 287 | |
| 288 | /* If we are here, wfi failed. As processors run out of |
| 289 | * coherency for some time, tlbs might be stale, so flush them |
| 290 | */ |
| 291 | local_flush_tlb_all(); |
| 292 | |
| 293 | ll_enable_coherency(); |
| 294 | |
| 295 | /* Test the CR_C bit and set it if it was cleared */ |
| 296 | asm volatile( |
Gregory CLEMENT | 0d461e1 | 2014-07-04 16:22:16 +0200 | [diff] [blame] | 297 | "mrc p15, 0, r0, c1, c0, 0 \n\t" |
Gregory CLEMENT | 7ee20ff | 2015-08-10 15:47:51 +0200 | [diff] [blame] | 298 | "tst r0, %0 \n\t" |
Gregory CLEMENT | 0d461e1 | 2014-07-04 16:22:16 +0200 | [diff] [blame] | 299 | "orreq r0, r0, #(1 << 2) \n\t" |
| 300 | "mcreq p15, 0, r0, c1, c0, 0 \n\t" |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 301 | "isb " |
Gregory CLEMENT | 7ee20ff | 2015-08-10 15:47:51 +0200 | [diff] [blame] | 302 | : : "Ir" (CR_C) : "r0"); |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 303 | |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 304 | pr_debug("Failed to suspend the system\n"); |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 305 | |
| 306 | return 0; |
| 307 | } |
| 308 | |
| 309 | static int armada_370_xp_cpu_suspend(unsigned long deepidle) |
| 310 | { |
Thomas Petazzoni | bbb9228 | 2014-05-30 22:18:15 +0200 | [diff] [blame] | 311 | return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter); |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 312 | } |
| 313 | |
Gregory CLEMENT | 626d686 | 2014-10-30 12:39:44 +0100 | [diff] [blame] | 314 | int armada_38x_do_cpu_suspend(unsigned long deepidle) |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 315 | { |
| 316 | unsigned long flags = 0; |
| 317 | |
| 318 | if (deepidle) |
| 319 | flags |= PMSU_PREPARE_DEEP_IDLE; |
| 320 | |
| 321 | mvebu_v7_pmsu_idle_prepare(flags); |
| 322 | /* |
| 323 | * Already flushed cache, but do it again as the outer cache |
| 324 | * functions dirty the cache with spinlocks |
| 325 | */ |
| 326 | v7_exit_coherency_flush(louis); |
| 327 | |
| 328 | scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF); |
| 329 | |
| 330 | cpu_do_idle(); |
| 331 | |
| 332 | return 1; |
| 333 | } |
| 334 | |
| 335 | static int armada_38x_cpu_suspend(unsigned long deepidle) |
| 336 | { |
| 337 | return cpu_suspend(false, armada_38x_do_cpu_suspend); |
| 338 | } |
| 339 | |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 340 | /* No locking is needed because we only access per-CPU registers */ |
Gregory CLEMENT | 898ef3e | 2014-07-23 15:00:42 +0200 | [diff] [blame] | 341 | void mvebu_v7_pmsu_idle_exit(void) |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 342 | { |
| 343 | unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); |
| 344 | u32 reg; |
| 345 | |
| 346 | if (pmsu_mp_base == NULL) |
| 347 | return; |
Gregory CLEMENT | c3e04ca | 2014-04-14 17:10:11 +0200 | [diff] [blame] | 348 | /* cancel ask HW to power down the L2 Cache if possible */ |
| 349 | reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); |
| 350 | reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN; |
| 351 | writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); |
| 352 | |
| 353 | /* cancel Enable wakeup events and mask interrupts */ |
| 354 | reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); |
| 355 | reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP); |
| 356 | reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT; |
| 357 | reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT; |
| 358 | reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK); |
| 359 | writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); |
| 360 | } |
| 361 | |
Gregory CLEMENT | 898ef3e | 2014-07-23 15:00:42 +0200 | [diff] [blame] | 362 | static int mvebu_v7_cpu_pm_notify(struct notifier_block *self, |
Gregory CLEMENT | d163ee1 | 2014-04-14 17:10:12 +0200 | [diff] [blame] | 363 | unsigned long action, void *hcpu) |
| 364 | { |
| 365 | if (action == CPU_PM_ENTER) { |
| 366 | unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); |
Gregory CLEMENT | 752a993 | 2014-07-23 15:00:44 +0200 | [diff] [blame] | 367 | mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume); |
Gregory CLEMENT | d163ee1 | 2014-04-14 17:10:12 +0200 | [diff] [blame] | 368 | } else if (action == CPU_PM_EXIT) { |
Gregory CLEMENT | 898ef3e | 2014-07-23 15:00:42 +0200 | [diff] [blame] | 369 | mvebu_v7_pmsu_idle_exit(); |
Gregory CLEMENT | d163ee1 | 2014-04-14 17:10:12 +0200 | [diff] [blame] | 370 | } |
| 371 | |
| 372 | return NOTIFY_OK; |
| 373 | } |
| 374 | |
Gregory CLEMENT | 898ef3e | 2014-07-23 15:00:42 +0200 | [diff] [blame] | 375 | static struct notifier_block mvebu_v7_cpu_pm_notifier = { |
| 376 | .notifier_call = mvebu_v7_cpu_pm_notify, |
Gregory CLEMENT | d163ee1 | 2014-04-14 17:10:12 +0200 | [diff] [blame] | 377 | }; |
| 378 | |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 379 | static struct platform_device mvebu_v7_cpuidle_device; |
| 380 | |
Vincent Donnefort | 9d2ea95 | 2015-10-23 12:59:58 +0200 | [diff] [blame] | 381 | static int broken_idle(struct device_node *np) |
| 382 | { |
| 383 | if (of_property_read_bool(np, "broken-idle")) { |
| 384 | pr_warn("CPU idle is currently broken: disabling\n"); |
| 385 | return 1; |
| 386 | } |
| 387 | |
| 388 | return 0; |
| 389 | } |
| 390 | |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 391 | static __init int armada_370_cpuidle_init(void) |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 392 | { |
| 393 | struct device_node *np; |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 394 | phys_addr_t redirect_reg; |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 395 | |
| 396 | np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"); |
| 397 | if (!np) |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 398 | return -ENODEV; |
Vincent Donnefort | 9d2ea95 | 2015-10-23 12:59:58 +0200 | [diff] [blame] | 399 | |
| 400 | if (broken_idle(np)) |
| 401 | goto end; |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 402 | |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 403 | /* |
| 404 | * On Armada 370, there is "a slow exit process from the deep |
| 405 | * idle state due to heavy L1/L2 cache cleanup operations |
| 406 | * performed by the BootROM software". To avoid this, we |
| 407 | * replace the restart code of the bootrom by a a simple jump |
| 408 | * to the boot address. Then the code located at this boot |
| 409 | * address will take care of the initialization. |
| 410 | */ |
| 411 | redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0); |
| 412 | mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET, |
| 413 | ARMADA_370_CRYPT0_ENG_ATTR, |
| 414 | redirect_reg); |
| 415 | |
| 416 | mvebu_cpu_resume = armada_370_xp_cpu_resume; |
| 417 | mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend; |
| 418 | mvebu_v7_cpuidle_device.name = "cpuidle-armada-370"; |
| 419 | |
Vincent Donnefort | 9d2ea95 | 2015-10-23 12:59:58 +0200 | [diff] [blame] | 420 | end: |
| 421 | of_node_put(np); |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 422 | return 0; |
| 423 | } |
| 424 | |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 425 | static __init int armada_38x_cpuidle_init(void) |
| 426 | { |
| 427 | struct device_node *np; |
| 428 | void __iomem *mpsoc_base; |
| 429 | u32 reg; |
| 430 | |
Thomas Petazzoni | a17683ba | 2015-06-12 15:38:34 +0200 | [diff] [blame] | 431 | pr_warn("CPU idle is currently broken on Armada 38x: disabling\n"); |
Gregory CLEMENT | 548ae94 | 2015-01-30 12:34:25 +0100 | [diff] [blame] | 432 | return 0; |
| 433 | |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 434 | np = of_find_compatible_node(NULL, NULL, |
| 435 | "marvell,armada-380-coherency-fabric"); |
| 436 | if (!np) |
| 437 | return -ENODEV; |
Vincent Donnefort | 9d2ea95 | 2015-10-23 12:59:58 +0200 | [diff] [blame] | 438 | |
| 439 | if (broken_idle(np)) |
| 440 | goto end; |
| 441 | |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 442 | of_node_put(np); |
| 443 | |
| 444 | np = of_find_compatible_node(NULL, NULL, |
| 445 | "marvell,armada-380-mpcore-soc-ctrl"); |
| 446 | if (!np) |
| 447 | return -ENODEV; |
| 448 | mpsoc_base = of_iomap(np, 0); |
| 449 | BUG_ON(!mpsoc_base); |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 450 | |
| 451 | /* Set up reset mask when powering down the cpus */ |
| 452 | reg = readl(mpsoc_base + MPCORE_RESET_CTL); |
| 453 | reg |= MPCORE_RESET_CTL_L2; |
| 454 | reg |= MPCORE_RESET_CTL_DEBUG; |
| 455 | writel(reg, mpsoc_base + MPCORE_RESET_CTL); |
| 456 | iounmap(mpsoc_base); |
| 457 | |
| 458 | /* Set up delay */ |
| 459 | reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY); |
| 460 | reg &= ~PMSU_POWERDOWN_DELAY_MASK; |
| 461 | reg |= PMSU_DFLT_ARMADA38X_DELAY; |
| 462 | reg |= PMSU_POWERDOWN_DELAY_PMU; |
| 463 | writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY); |
| 464 | |
| 465 | mvebu_cpu_resume = armada_38x_cpu_resume; |
| 466 | mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend; |
| 467 | mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x"; |
| 468 | |
Vincent Donnefort | 9d2ea95 | 2015-10-23 12:59:58 +0200 | [diff] [blame] | 469 | end: |
| 470 | of_node_put(np); |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 471 | return 0; |
| 472 | } |
| 473 | |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 474 | static __init int armada_xp_cpuidle_init(void) |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 475 | { |
| 476 | struct device_node *np; |
| 477 | |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 478 | np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"); |
| 479 | if (!np) |
Gregory CLEMENT | 54a4d1b | 2014-07-23 15:00:43 +0200 | [diff] [blame] | 480 | return -ENODEV; |
Vincent Donnefort | 9d2ea95 | 2015-10-23 12:59:58 +0200 | [diff] [blame] | 481 | |
| 482 | if (broken_idle(np)) |
| 483 | goto end; |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 484 | |
Gregory CLEMENT | 752a993 | 2014-07-23 15:00:44 +0200 | [diff] [blame] | 485 | mvebu_cpu_resume = armada_370_xp_cpu_resume; |
Gregory CLEMENT | 54a4d1b | 2014-07-23 15:00:43 +0200 | [diff] [blame] | 486 | mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend; |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 487 | mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp"; |
Gregory CLEMENT | 54a4d1b | 2014-07-23 15:00:43 +0200 | [diff] [blame] | 488 | |
Vincent Donnefort | 9d2ea95 | 2015-10-23 12:59:58 +0200 | [diff] [blame] | 489 | end: |
| 490 | of_node_put(np); |
Gregory CLEMENT | 54a4d1b | 2014-07-23 15:00:43 +0200 | [diff] [blame] | 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | static int __init mvebu_v7_cpu_pm_init(void) |
| 495 | { |
| 496 | struct device_node *np; |
| 497 | int ret; |
| 498 | |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 499 | np = of_find_matching_node(NULL, of_pmsu_table); |
| 500 | if (!np) |
| 501 | return 0; |
| 502 | of_node_put(np); |
| 503 | |
Gregory CLEMENT | 548ae94 | 2015-01-30 12:34:25 +0100 | [diff] [blame] | 504 | /* |
| 505 | * Currently the CPU idle support for Armada 38x is broken, as |
| 506 | * the CPU hotplug uses some of the CPU idle functions it is |
| 507 | * broken too, so let's disable it |
| 508 | */ |
| 509 | if (of_machine_is_compatible("marvell,armada380")) { |
| 510 | cpu_hotplug_disable(); |
Thomas Petazzoni | a17683ba | 2015-06-12 15:38:34 +0200 | [diff] [blame] | 511 | pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling\n"); |
Gregory CLEMENT | 548ae94 | 2015-01-30 12:34:25 +0100 | [diff] [blame] | 512 | } |
| 513 | |
Gregory CLEMENT | 54a4d1b | 2014-07-23 15:00:43 +0200 | [diff] [blame] | 514 | if (of_machine_is_compatible("marvell,armadaxp")) |
| 515 | ret = armada_xp_cpuidle_init(); |
Gregory CLEMENT | 3b9e4b1 | 2014-07-23 15:00:51 +0200 | [diff] [blame] | 516 | else if (of_machine_is_compatible("marvell,armada370")) |
| 517 | ret = armada_370_cpuidle_init(); |
Gregory CLEMENT | e53b1fd | 2014-07-23 15:00:52 +0200 | [diff] [blame] | 518 | else if (of_machine_is_compatible("marvell,armada380")) |
| 519 | ret = armada_38x_cpuidle_init(); |
Gregory CLEMENT | 54a4d1b | 2014-07-23 15:00:43 +0200 | [diff] [blame] | 520 | else |
| 521 | return 0; |
| 522 | |
| 523 | if (ret) |
| 524 | return ret; |
| 525 | |
Gregory CLEMENT | 898ef3e | 2014-07-23 15:00:42 +0200 | [diff] [blame] | 526 | mvebu_v7_pmsu_enable_l2_powerdown_onidle(); |
Gregory CLEMENT | 548ae94 | 2015-01-30 12:34:25 +0100 | [diff] [blame] | 527 | if (mvebu_v7_cpuidle_device.name) |
| 528 | platform_device_register(&mvebu_v7_cpuidle_device); |
Gregory CLEMENT | 898ef3e | 2014-07-23 15:00:42 +0200 | [diff] [blame] | 529 | cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier); |
Gregory CLEMENT | 8c16bab | 2014-04-14 17:10:14 +0200 | [diff] [blame] | 530 | |
| 531 | return 0; |
| 532 | } |
| 533 | |
Gregory CLEMENT | 898ef3e | 2014-07-23 15:00:42 +0200 | [diff] [blame] | 534 | arch_initcall(mvebu_v7_cpu_pm_init); |
| 535 | early_initcall(mvebu_v7_pmsu_init); |
Thomas Petazzoni | a509ea8 | 2014-07-09 17:45:10 +0200 | [diff] [blame] | 536 | |
| 537 | static void mvebu_pmsu_dfs_request_local(void *data) |
| 538 | { |
| 539 | u32 reg; |
| 540 | u32 cpu = smp_processor_id(); |
| 541 | unsigned long flags; |
| 542 | |
| 543 | local_irq_save(flags); |
| 544 | |
| 545 | /* Prepare to enter idle */ |
| 546 | reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); |
| 547 | reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT | |
| 548 | PMSU_STATUS_AND_MASK_IRQ_MASK | |
| 549 | PMSU_STATUS_AND_MASK_FIQ_MASK; |
| 550 | writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); |
| 551 | |
| 552 | /* Request the DFS transition */ |
| 553 | reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu)); |
| 554 | reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ; |
| 555 | writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu)); |
| 556 | |
| 557 | /* The fact of entering idle will trigger the DFS transition */ |
| 558 | wfi(); |
| 559 | |
| 560 | /* |
| 561 | * We're back from idle, the DFS transition has completed, |
| 562 | * clear the idle wait indication. |
| 563 | */ |
| 564 | reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); |
| 565 | reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT; |
| 566 | writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); |
| 567 | |
| 568 | local_irq_restore(flags); |
| 569 | } |
| 570 | |
| 571 | int mvebu_pmsu_dfs_request(int cpu) |
| 572 | { |
| 573 | unsigned long timeout; |
| 574 | int hwcpu = cpu_logical_map(cpu); |
| 575 | u32 reg; |
| 576 | |
| 577 | /* Clear any previous DFS DONE event */ |
| 578 | reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); |
| 579 | reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE; |
| 580 | writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); |
| 581 | |
| 582 | /* Mask the DFS done interrupt, since we are going to poll */ |
| 583 | reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); |
| 584 | reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK; |
| 585 | writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); |
| 586 | |
| 587 | /* Trigger the DFS on the appropriate CPU */ |
| 588 | smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local, |
| 589 | NULL, false); |
| 590 | |
| 591 | /* Poll until the DFS done event is generated */ |
| 592 | timeout = jiffies + HZ; |
| 593 | while (time_before(jiffies, timeout)) { |
| 594 | reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); |
| 595 | if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE) |
| 596 | break; |
| 597 | udelay(10); |
| 598 | } |
| 599 | |
| 600 | if (time_after(jiffies, timeout)) |
| 601 | return -ETIME; |
| 602 | |
| 603 | /* Restore the DFS mask to its original state */ |
| 604 | reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); |
| 605 | reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK; |
| 606 | writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); |
| 607 | |
| 608 | return 0; |
| 609 | } |