Steven J. Hill | 2299c49 | 2012-08-31 16:13:07 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
| 5 | * |
| 6 | * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org) |
| 7 | * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. |
| 8 | */ |
Matt Redfearn | 1f19aee | 2017-11-09 11:02:44 +0000 | [diff] [blame] | 9 | |
| 10 | #define pr_fmt(fmt) "irq-mips-gic: " fmt |
| 11 | |
Geert Uytterhoeven | 357a9c4 | 2021-11-22 16:54:07 +0100 | [diff] [blame] | 12 | #include <linux/bitfield.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 13 | #include <linux/bitmap.h> |
Andrew Bresticker | fb8f7be1 | 2014-10-20 12:03:55 -0700 | [diff] [blame] | 14 | #include <linux/clocksource.h> |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 15 | #include <linux/cpuhotplug.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 16 | #include <linux/init.h> |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 17 | #include <linux/interrupt.h> |
Andrew Bresticker | fb8f7be1 | 2014-10-20 12:03:55 -0700 | [diff] [blame] | 18 | #include <linux/irq.h> |
Joel Porquet | 41a83e06 | 2015-07-07 17:11:46 -0400 | [diff] [blame] | 19 | #include <linux/irqchip.h> |
Marc Zyngier | 1982752 | 2018-09-13 09:30:34 +0100 | [diff] [blame] | 20 | #include <linux/irqdomain.h> |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 21 | #include <linux/of_address.h> |
Paul Burton | aa49373 | 2017-08-12 21:36:42 -0700 | [diff] [blame] | 22 | #include <linux/percpu.h> |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 23 | #include <linux/sched.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 24 | #include <linux/smp.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 25 | |
Paul Burton | e83f7e0 | 2017-08-12 19:49:41 -0700 | [diff] [blame] | 26 | #include <asm/mips-cps.h> |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 27 | #include <asm/setup.h> |
| 28 | #include <asm/traps.h> |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 29 | |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 30 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
| 31 | |
Paul Burton | b11d4c1 | 2017-08-12 21:36:29 -0700 | [diff] [blame] | 32 | #define GIC_MAX_INTRS 256 |
Paul Burton | aa49373 | 2017-08-12 21:36:42 -0700 | [diff] [blame] | 33 | #define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS) |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 34 | |
Paul Burton | b11d4c1 | 2017-08-12 21:36:29 -0700 | [diff] [blame] | 35 | /* Add 2 to convert GIC CPU pin to core interrupt */ |
| 36 | #define GIC_CPU_PIN_OFFSET 2 |
Jeffrey Deans | 822350b | 2014-07-17 09:20:53 +0100 | [diff] [blame] | 37 | |
Paul Burton | b11d4c1 | 2017-08-12 21:36:29 -0700 | [diff] [blame] | 38 | /* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */ |
| 39 | #define GIC_PIN_TO_VEC_OFFSET 1 |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 40 | |
Paul Burton | b11d4c1 | 2017-08-12 21:36:29 -0700 | [diff] [blame] | 41 | /* Convert between local/shared IRQ number and GIC HW IRQ number. */ |
| 42 | #define GIC_LOCAL_HWIRQ_BASE 0 |
| 43 | #define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x)) |
| 44 | #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE) |
| 45 | #define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS |
| 46 | #define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x)) |
| 47 | #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE) |
| 48 | |
Paul Burton | 582e2b4 | 2017-08-12 21:36:10 -0700 | [diff] [blame] | 49 | void __iomem *mips_gic_base; |
Steven J. Hill | 0b271f5 | 2012-08-31 16:05:37 -0500 | [diff] [blame] | 50 | |
Wei Yongjun | b0e453f | 2020-07-14 22:22:45 +0800 | [diff] [blame] | 51 | static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks); |
Jeffrey Deans | 822350b | 2014-07-17 09:20:53 +0100 | [diff] [blame] | 52 | |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 53 | static DEFINE_RAW_SPINLOCK(gic_lock); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 54 | static struct irq_domain *gic_irq_domain; |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 55 | static int gic_shared_intrs; |
Andrew Bresticker | 3263d08 | 2014-09-18 14:47:28 -0700 | [diff] [blame] | 56 | static unsigned int gic_cpu_pin; |
Andrew Bresticker | 4a6a3ea3 | 2014-09-18 14:47:26 -0700 | [diff] [blame] | 57 | static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; |
Samuel Holland | 8190cc5 | 2022-07-01 15:00:49 -0500 | [diff] [blame] | 58 | |
| 59 | #ifdef CONFIG_GENERIC_IRQ_IPI |
Paul Burton | 61dc367 | 2017-10-31 09:41:51 -0700 | [diff] [blame] | 60 | static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS); |
| 61 | static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS); |
Samuel Holland | 8190cc5 | 2022-07-01 15:00:49 -0500 | [diff] [blame] | 62 | #endif /* CONFIG_GENERIC_IRQ_IPI */ |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 63 | |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 64 | static struct gic_all_vpes_chip_data { |
| 65 | u32 map; |
| 66 | bool mask; |
| 67 | } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; |
| 68 | |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 69 | static void gic_clear_pcpu_masks(unsigned int intr) |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 70 | { |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 71 | unsigned int i; |
Andrew Bresticker | 5f68fea | 2014-10-20 12:03:52 -0700 | [diff] [blame] | 72 | |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 73 | /* Clear the interrupt's bit in all pcpu_masks */ |
| 74 | for_each_possible_cpu(i) |
| 75 | clear_bit(intr, per_cpu_ptr(pcpu_masks, i)); |
Paul Burton | 835d2b4 | 2016-02-03 03:15:28 +0000 | [diff] [blame] | 76 | } |
| 77 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 78 | static bool gic_local_irq_is_routable(int intr) |
| 79 | { |
| 80 | u32 vpe_ctl; |
| 81 | |
| 82 | /* All local interrupts are routable in EIC mode. */ |
| 83 | if (cpu_has_veic) |
| 84 | return true; |
| 85 | |
Paul Burton | 0d0cf58 | 2017-08-12 21:36:26 -0700 | [diff] [blame] | 86 | vpe_ctl = read_gic_vl_ctl(); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 87 | switch (intr) { |
| 88 | case GIC_LOCAL_INT_TIMER: |
Paul Burton | 0d0cf58 | 2017-08-12 21:36:26 -0700 | [diff] [blame] | 89 | return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 90 | case GIC_LOCAL_INT_PERFCTR: |
Paul Burton | 0d0cf58 | 2017-08-12 21:36:26 -0700 | [diff] [blame] | 91 | return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 92 | case GIC_LOCAL_INT_FDC: |
Paul Burton | 0d0cf58 | 2017-08-12 21:36:26 -0700 | [diff] [blame] | 93 | return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 94 | case GIC_LOCAL_INT_SWINT0: |
| 95 | case GIC_LOCAL_INT_SWINT1: |
Paul Burton | 0d0cf58 | 2017-08-12 21:36:26 -0700 | [diff] [blame] | 96 | return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 97 | default: |
| 98 | return true; |
| 99 | } |
| 100 | } |
| 101 | |
Andrew Bresticker | 3263d08 | 2014-09-18 14:47:28 -0700 | [diff] [blame] | 102 | static void gic_bind_eic_interrupt(int irq, int set) |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 103 | { |
| 104 | /* Convert irq vector # to hw int # */ |
| 105 | irq -= GIC_PIN_TO_VEC_OFFSET; |
| 106 | |
| 107 | /* Set irq to use shadow set */ |
Paul Burton | 0d0cf58 | 2017-08-12 21:36:26 -0700 | [diff] [blame] | 108 | write_gic_vl_eic_shadow_set(irq, set); |
Steven J. Hill | 98b67c3 | 2012-08-31 16:18:49 -0500 | [diff] [blame] | 109 | } |
| 110 | |
Qais Yousef | bb11cff | 2015-12-08 13:20:28 +0000 | [diff] [blame] | 111 | static void gic_send_ipi(struct irq_data *d, unsigned int cpu) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 112 | { |
Qais Yousef | bb11cff | 2015-12-08 13:20:28 +0000 | [diff] [blame] | 113 | irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d)); |
| 114 | |
Paul Burton | 3680746 | 2017-08-12 21:36:24 -0700 | [diff] [blame] | 115 | write_gic_wedge(GIC_WEDGE_RW | hwirq); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 116 | } |
| 117 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 118 | int gic_get_c0_compare_int(void) |
| 119 | { |
| 120 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) |
| 121 | return MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
| 122 | return irq_create_mapping(gic_irq_domain, |
| 123 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER)); |
| 124 | } |
| 125 | |
| 126 | int gic_get_c0_perfcount_int(void) |
| 127 | { |
| 128 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) { |
James Hogan | 7e3e6cb | 2015-01-27 21:45:50 +0000 | [diff] [blame] | 129 | /* Is the performance counter shared with the timer? */ |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 130 | if (cp0_perfcount_irq < 0) |
| 131 | return -1; |
| 132 | return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; |
| 133 | } |
| 134 | return irq_create_mapping(gic_irq_domain, |
| 135 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR)); |
| 136 | } |
| 137 | |
James Hogan | 6429e2b | 2015-01-29 11:14:09 +0000 | [diff] [blame] | 138 | int gic_get_c0_fdc_int(void) |
| 139 | { |
| 140 | if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) { |
| 141 | /* Is the FDC IRQ even present? */ |
| 142 | if (cp0_fdc_irq < 0) |
| 143 | return -1; |
| 144 | return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; |
| 145 | } |
| 146 | |
James Hogan | 6429e2b | 2015-01-29 11:14:09 +0000 | [diff] [blame] | 147 | return irq_create_mapping(gic_irq_domain, |
| 148 | GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC)); |
| 149 | } |
| 150 | |
Rabin Vincent | 1b3ed36 | 2015-06-12 10:01:56 +0200 | [diff] [blame] | 151 | static void gic_handle_shared_int(bool chained) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 152 | { |
Marc Zyngier | 046a6ee | 2021-05-04 17:42:18 +0100 | [diff] [blame] | 153 | unsigned int intr; |
Andrew Bresticker | 8f5ee79 | 2014-10-20 12:03:56 -0700 | [diff] [blame] | 154 | unsigned long *pcpu_mask; |
Andrew Bresticker | 8f5ee79 | 2014-10-20 12:03:56 -0700 | [diff] [blame] | 155 | DECLARE_BITMAP(pending, GIC_MAX_INTRS); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 156 | |
| 157 | /* Get per-cpu bitmaps */ |
Paul Burton | aa49373 | 2017-08-12 21:36:42 -0700 | [diff] [blame] | 158 | pcpu_mask = this_cpu_ptr(pcpu_masks); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 159 | |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 160 | if (mips_cm_is64) |
Paul Burton | e98fcb2 | 2017-08-12 21:36:16 -0700 | [diff] [blame] | 161 | __ioread64_copy(pending, addr_gic_pend(), |
| 162 | DIV_ROUND_UP(gic_shared_intrs, 64)); |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 163 | else |
Paul Burton | e98fcb2 | 2017-08-12 21:36:16 -0700 | [diff] [blame] | 164 | __ioread32_copy(pending, addr_gic_pend(), |
| 165 | DIV_ROUND_UP(gic_shared_intrs, 32)); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 166 | |
Andrew Bresticker | fbd5524 | 2014-09-18 14:47:25 -0700 | [diff] [blame] | 167 | bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 168 | |
Paul Burton | cae750b | 2016-08-19 18:11:19 +0100 | [diff] [blame] | 169 | for_each_set_bit(intr, pending, gic_shared_intrs) { |
Rabin Vincent | 1b3ed36 | 2015-06-12 10:01:56 +0200 | [diff] [blame] | 170 | if (chained) |
Marc Zyngier | 046a6ee | 2021-05-04 17:42:18 +0100 | [diff] [blame] | 171 | generic_handle_domain_irq(gic_irq_domain, |
| 172 | GIC_SHARED_TO_HWIRQ(intr)); |
Rabin Vincent | 1b3ed36 | 2015-06-12 10:01:56 +0200 | [diff] [blame] | 173 | else |
Marc Zyngier | 1fee9db | 2021-07-06 11:38:59 +0100 | [diff] [blame] | 174 | do_domain_IRQ(gic_irq_domain, |
| 175 | GIC_SHARED_TO_HWIRQ(intr)); |
Qais Yousef | d7eb4f2 | 2015-01-19 11:51:29 +0000 | [diff] [blame] | 176 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 177 | } |
| 178 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 179 | static void gic_mask_irq(struct irq_data *d) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 180 | { |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 181 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
| 182 | |
Paul Burton | 90019f8 | 2017-09-05 11:28:46 -0700 | [diff] [blame] | 183 | write_gic_rmask(intr); |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 184 | gic_clear_pcpu_masks(intr); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 185 | } |
| 186 | |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 187 | static void gic_unmask_irq(struct irq_data *d) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 188 | { |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 189 | unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); |
| 190 | unsigned int cpu; |
| 191 | |
Paul Burton | 90019f8 | 2017-09-05 11:28:46 -0700 | [diff] [blame] | 192 | write_gic_smask(intr); |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 193 | |
| 194 | gic_clear_pcpu_masks(intr); |
Paul Burton | d9f8293 | 2017-09-21 23:24:40 -0700 | [diff] [blame] | 195 | cpu = cpumask_first(irq_data_get_effective_affinity_mask(d)); |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 196 | set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 197 | } |
| 198 | |
Andrew Bresticker | 5561c9e | 2014-09-18 14:47:20 -0700 | [diff] [blame] | 199 | static void gic_ack_irq(struct irq_data *d) |
| 200 | { |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 201 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 202 | |
Paul Burton | 3680746 | 2017-08-12 21:36:24 -0700 | [diff] [blame] | 203 | write_gic_wedge(irq); |
Andrew Bresticker | 5561c9e | 2014-09-18 14:47:20 -0700 | [diff] [blame] | 204 | } |
| 205 | |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 206 | static int gic_set_type(struct irq_data *d, unsigned int type) |
| 207 | { |
Paul Burton | 5af3e93 | 2017-10-31 09:41:50 -0700 | [diff] [blame] | 208 | unsigned int irq, pol, trig, dual; |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 209 | unsigned long flags; |
Paul Burton | 5af3e93 | 2017-10-31 09:41:50 -0700 | [diff] [blame] | 210 | |
| 211 | irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 212 | |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 213 | raw_spin_lock_irqsave(&gic_lock, flags); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 214 | switch (type & IRQ_TYPE_SENSE_MASK) { |
| 215 | case IRQ_TYPE_EDGE_FALLING: |
Paul Burton | 5af3e93 | 2017-10-31 09:41:50 -0700 | [diff] [blame] | 216 | pol = GIC_POL_FALLING_EDGE; |
| 217 | trig = GIC_TRIG_EDGE; |
| 218 | dual = GIC_DUAL_SINGLE; |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 219 | break; |
| 220 | case IRQ_TYPE_EDGE_RISING: |
Paul Burton | 5af3e93 | 2017-10-31 09:41:50 -0700 | [diff] [blame] | 221 | pol = GIC_POL_RISING_EDGE; |
| 222 | trig = GIC_TRIG_EDGE; |
| 223 | dual = GIC_DUAL_SINGLE; |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 224 | break; |
| 225 | case IRQ_TYPE_EDGE_BOTH: |
Paul Burton | 5af3e93 | 2017-10-31 09:41:50 -0700 | [diff] [blame] | 226 | pol = 0; /* Doesn't matter */ |
| 227 | trig = GIC_TRIG_EDGE; |
| 228 | dual = GIC_DUAL_DUAL; |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 229 | break; |
| 230 | case IRQ_TYPE_LEVEL_LOW: |
Paul Burton | 5af3e93 | 2017-10-31 09:41:50 -0700 | [diff] [blame] | 231 | pol = GIC_POL_ACTIVE_LOW; |
| 232 | trig = GIC_TRIG_LEVEL; |
| 233 | dual = GIC_DUAL_SINGLE; |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 234 | break; |
| 235 | case IRQ_TYPE_LEVEL_HIGH: |
| 236 | default: |
Paul Burton | 5af3e93 | 2017-10-31 09:41:50 -0700 | [diff] [blame] | 237 | pol = GIC_POL_ACTIVE_HIGH; |
| 238 | trig = GIC_TRIG_LEVEL; |
| 239 | dual = GIC_DUAL_SINGLE; |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 240 | break; |
| 241 | } |
| 242 | |
Paul Burton | 5af3e93 | 2017-10-31 09:41:50 -0700 | [diff] [blame] | 243 | change_gic_pol(irq, pol); |
| 244 | change_gic_trig(irq, trig); |
| 245 | change_gic_dual(irq, dual); |
| 246 | |
| 247 | if (trig == GIC_TRIG_EDGE) |
Thomas Gleixner | a595fc5 | 2015-06-23 14:41:25 +0200 | [diff] [blame] | 248 | irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller, |
| 249 | handle_edge_irq, NULL); |
| 250 | else |
| 251 | irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, |
| 252 | handle_level_irq, NULL); |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 253 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 254 | |
| 255 | return 0; |
| 256 | } |
| 257 | |
| 258 | #ifdef CONFIG_SMP |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 259 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, |
| 260 | bool force) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 261 | { |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 262 | unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); |
Paul Burton | 07df8bf | 2017-08-18 14:04:35 -0700 | [diff] [blame] | 263 | unsigned long flags; |
| 264 | unsigned int cpu; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 265 | |
Paul Burton | 07df8bf | 2017-08-18 14:04:35 -0700 | [diff] [blame] | 266 | cpu = cpumask_first_and(cpumask, cpu_online_mask); |
| 267 | if (cpu >= NR_CPUS) |
Andrew Bresticker | 14d160a | 2014-09-18 14:47:22 -0700 | [diff] [blame] | 268 | return -EINVAL; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 269 | |
| 270 | /* Assumption : cpumask refers to a single CPU */ |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 271 | raw_spin_lock_irqsave(&gic_lock, flags); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 272 | |
Tony Wu | c214c03 | 2013-06-21 10:13:08 +0000 | [diff] [blame] | 273 | /* Re-route this IRQ */ |
Paul Burton | 07df8bf | 2017-08-18 14:04:35 -0700 | [diff] [blame] | 274 | write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 275 | |
Tony Wu | c214c03 | 2013-06-21 10:13:08 +0000 | [diff] [blame] | 276 | /* Update the pcpu_masks */ |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 277 | gic_clear_pcpu_masks(irq); |
| 278 | if (read_gic_mask(irq)) |
Paul Burton | 07df8bf | 2017-08-18 14:04:35 -0700 | [diff] [blame] | 279 | set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); |
Tony Wu | c214c03 | 2013-06-21 10:13:08 +0000 | [diff] [blame] | 280 | |
Marc Zyngier | 18416e4 | 2017-08-18 09:39:24 +0100 | [diff] [blame] | 281 | irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 282 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 283 | |
Paul Burton | 7f15a64 | 2017-08-12 21:36:46 -0700 | [diff] [blame] | 284 | return IRQ_SET_MASK_OK; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 285 | } |
| 286 | #endif |
| 287 | |
Andrew Bresticker | 4a6a3ea3 | 2014-09-18 14:47:26 -0700 | [diff] [blame] | 288 | static struct irq_chip gic_level_irq_controller = { |
| 289 | .name = "MIPS GIC", |
| 290 | .irq_mask = gic_mask_irq, |
| 291 | .irq_unmask = gic_unmask_irq, |
| 292 | .irq_set_type = gic_set_type, |
| 293 | #ifdef CONFIG_SMP |
| 294 | .irq_set_affinity = gic_set_affinity, |
| 295 | #endif |
| 296 | }; |
| 297 | |
| 298 | static struct irq_chip gic_edge_irq_controller = { |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 299 | .name = "MIPS GIC", |
Andrew Bresticker | 5561c9e | 2014-09-18 14:47:20 -0700 | [diff] [blame] | 300 | .irq_ack = gic_ack_irq, |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 301 | .irq_mask = gic_mask_irq, |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 302 | .irq_unmask = gic_unmask_irq, |
Andrew Bresticker | 95150ae | 2014-09-18 14:47:21 -0700 | [diff] [blame] | 303 | .irq_set_type = gic_set_type, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 304 | #ifdef CONFIG_SMP |
Thomas Gleixner | 161d049 | 2011-03-23 21:08:58 +0000 | [diff] [blame] | 305 | .irq_set_affinity = gic_set_affinity, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 306 | #endif |
Qais Yousef | bb11cff | 2015-12-08 13:20:28 +0000 | [diff] [blame] | 307 | .ipi_send_single = gic_send_ipi, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 308 | }; |
| 309 | |
Rabin Vincent | 1b3ed36 | 2015-06-12 10:01:56 +0200 | [diff] [blame] | 310 | static void gic_handle_local_int(bool chained) |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 311 | { |
| 312 | unsigned long pending, masked; |
Marc Zyngier | 046a6ee | 2021-05-04 17:42:18 +0100 | [diff] [blame] | 313 | unsigned int intr; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 314 | |
Paul Burton | 9da3c64 | 2017-08-12 21:36:25 -0700 | [diff] [blame] | 315 | pending = read_gic_vl_pend(); |
| 316 | masked = read_gic_vl_mask(); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 317 | |
| 318 | bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS); |
| 319 | |
Paul Burton | 0f4ed15 | 2016-09-13 17:54:27 +0100 | [diff] [blame] | 320 | for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) { |
Rabin Vincent | 1b3ed36 | 2015-06-12 10:01:56 +0200 | [diff] [blame] | 321 | if (chained) |
Marc Zyngier | 046a6ee | 2021-05-04 17:42:18 +0100 | [diff] [blame] | 322 | generic_handle_domain_irq(gic_irq_domain, |
| 323 | GIC_LOCAL_TO_HWIRQ(intr)); |
Rabin Vincent | 1b3ed36 | 2015-06-12 10:01:56 +0200 | [diff] [blame] | 324 | else |
Marc Zyngier | 1fee9db | 2021-07-06 11:38:59 +0100 | [diff] [blame] | 325 | do_domain_IRQ(gic_irq_domain, |
| 326 | GIC_LOCAL_TO_HWIRQ(intr)); |
Qais Yousef | d7eb4f2 | 2015-01-19 11:51:29 +0000 | [diff] [blame] | 327 | } |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 328 | } |
| 329 | |
| 330 | static void gic_mask_local_irq(struct irq_data *d) |
| 331 | { |
| 332 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
| 333 | |
Paul Burton | 9da3c64 | 2017-08-12 21:36:25 -0700 | [diff] [blame] | 334 | write_gic_vl_rmask(BIT(intr)); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | static void gic_unmask_local_irq(struct irq_data *d) |
| 338 | { |
| 339 | int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
| 340 | |
Paul Burton | 9da3c64 | 2017-08-12 21:36:25 -0700 | [diff] [blame] | 341 | write_gic_vl_smask(BIT(intr)); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | static struct irq_chip gic_local_irq_controller = { |
| 345 | .name = "MIPS GIC Local", |
| 346 | .irq_mask = gic_mask_local_irq, |
| 347 | .irq_unmask = gic_unmask_local_irq, |
| 348 | }; |
| 349 | |
| 350 | static void gic_mask_local_irq_all_vpes(struct irq_data *d) |
| 351 | { |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 352 | struct gic_all_vpes_chip_data *cd; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 353 | unsigned long flags; |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 354 | int intr, cpu; |
| 355 | |
| 356 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
| 357 | cd = irq_data_get_irq_chip_data(d); |
| 358 | cd->mask = false; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 359 | |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 360 | raw_spin_lock_irqsave(&gic_lock, flags); |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 361 | for_each_online_cpu(cpu) { |
| 362 | write_gic_vl_other(mips_cm_vp_id(cpu)); |
Paul Burton | 9da3c64 | 2017-08-12 21:36:25 -0700 | [diff] [blame] | 363 | write_gic_vo_rmask(BIT(intr)); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 364 | } |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 365 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | static void gic_unmask_local_irq_all_vpes(struct irq_data *d) |
| 369 | { |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 370 | struct gic_all_vpes_chip_data *cd; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 371 | unsigned long flags; |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 372 | int intr, cpu; |
| 373 | |
| 374 | intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); |
| 375 | cd = irq_data_get_irq_chip_data(d); |
| 376 | cd->mask = true; |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 377 | |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 378 | raw_spin_lock_irqsave(&gic_lock, flags); |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 379 | for_each_online_cpu(cpu) { |
| 380 | write_gic_vl_other(mips_cm_vp_id(cpu)); |
Paul Burton | 9da3c64 | 2017-08-12 21:36:25 -0700 | [diff] [blame] | 381 | write_gic_vo_smask(BIT(intr)); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 382 | } |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 383 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 384 | } |
| 385 | |
Marc Zyngier | dd098a0 | 2021-10-21 18:04:13 +0100 | [diff] [blame] | 386 | static void gic_all_vpes_irq_cpu_online(void) |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 387 | { |
Marc Zyngier | dd098a0 | 2021-10-21 18:04:13 +0100 | [diff] [blame] | 388 | static const unsigned int local_intrs[] = { |
| 389 | GIC_LOCAL_INT_TIMER, |
| 390 | GIC_LOCAL_INT_PERFCTR, |
| 391 | GIC_LOCAL_INT_FDC, |
| 392 | }; |
| 393 | unsigned long flags; |
| 394 | int i; |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 395 | |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 396 | raw_spin_lock_irqsave(&gic_lock, flags); |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 397 | |
Marc Zyngier | dd098a0 | 2021-10-21 18:04:13 +0100 | [diff] [blame] | 398 | for (i = 0; i < ARRAY_SIZE(local_intrs); i++) { |
| 399 | unsigned int intr = local_intrs[i]; |
| 400 | struct gic_all_vpes_chip_data *cd; |
| 401 | |
Jiaxun Yang | 2c6c9c0 | 2023-04-24 11:31:55 +0100 | [diff] [blame] | 402 | if (!gic_local_irq_is_routable(intr)) |
| 403 | continue; |
Marc Zyngier | dd098a0 | 2021-10-21 18:04:13 +0100 | [diff] [blame] | 404 | cd = &gic_all_vpes_chip_data[intr]; |
| 405 | write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); |
| 406 | if (cd->mask) |
| 407 | write_gic_vl_smask(BIT(intr)); |
| 408 | } |
| 409 | |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 410 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 411 | } |
| 412 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 413 | static struct irq_chip gic_all_vpes_local_irq_controller = { |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 414 | .name = "MIPS GIC Local", |
| 415 | .irq_mask = gic_mask_local_irq_all_vpes, |
| 416 | .irq_unmask = gic_unmask_local_irq_all_vpes, |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 417 | }; |
| 418 | |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 419 | static void __gic_irq_dispatch(void) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 420 | { |
Rabin Vincent | 1b3ed36 | 2015-06-12 10:01:56 +0200 | [diff] [blame] | 421 | gic_handle_local_int(false); |
| 422 | gic_handle_shared_int(false); |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 423 | } |
| 424 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 425 | static void gic_irq_dispatch(struct irq_desc *desc) |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 426 | { |
Rabin Vincent | 1b3ed36 | 2015-06-12 10:01:56 +0200 | [diff] [blame] | 427 | gic_handle_local_int(true); |
| 428 | gic_handle_shared_int(true); |
Andrew Bresticker | 18743d2 | 2014-09-18 14:47:24 -0700 | [diff] [blame] | 429 | } |
| 430 | |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 431 | static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 432 | irq_hw_number_t hw, unsigned int cpu) |
Andrew Bresticker | e9de688 | 2014-09-18 14:47:27 -0700 | [diff] [blame] | 433 | { |
| 434 | int intr = GIC_HWIRQ_TO_SHARED(hw); |
Paul Burton | d9f8293 | 2017-09-21 23:24:40 -0700 | [diff] [blame] | 435 | struct irq_data *data; |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 436 | unsigned long flags; |
| 437 | |
Paul Burton | d9f8293 | 2017-09-21 23:24:40 -0700 | [diff] [blame] | 438 | data = irq_get_irq_data(virq); |
| 439 | |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 440 | raw_spin_lock_irqsave(&gic_lock, flags); |
Paul Burton | d3e8cf4 | 2017-08-12 21:36:22 -0700 | [diff] [blame] | 441 | write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); |
Paul Burton | 7778c4b | 2017-08-18 14:02:21 -0700 | [diff] [blame] | 442 | write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); |
Paul Burton | d9f8293 | 2017-09-21 23:24:40 -0700 | [diff] [blame] | 443 | irq_data_update_effective_affinity(data, cpumask_of(cpu)); |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 444 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 445 | |
| 446 | return 0; |
| 447 | } |
| 448 | |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 449 | static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
Qais Yousef | c98c1822 | 2015-12-08 13:20:24 +0000 | [diff] [blame] | 450 | const u32 *intspec, unsigned int intsize, |
| 451 | irq_hw_number_t *out_hwirq, |
| 452 | unsigned int *out_type) |
| 453 | { |
| 454 | if (intsize != 3) |
| 455 | return -EINVAL; |
| 456 | |
| 457 | if (intspec[0] == GIC_SHARED) |
| 458 | *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]); |
| 459 | else if (intspec[0] == GIC_LOCAL) |
| 460 | *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]); |
| 461 | else |
| 462 | return -EINVAL; |
| 463 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
| 464 | |
| 465 | return 0; |
| 466 | } |
| 467 | |
Matt Redfearn | 8ada00a | 2017-04-20 10:07:36 +0100 | [diff] [blame] | 468 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, |
| 469 | irq_hw_number_t hwirq) |
Qais Yousef | c98c1822 | 2015-12-08 13:20:24 +0000 | [diff] [blame] | 470 | { |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 471 | struct gic_all_vpes_chip_data *cd; |
Paul Burton | 63b746b1 | 2017-10-31 09:41:44 -0700 | [diff] [blame] | 472 | unsigned long flags; |
| 473 | unsigned int intr; |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 474 | int err, cpu; |
Paul Burton | 63b746b1 | 2017-10-31 09:41:44 -0700 | [diff] [blame] | 475 | u32 map; |
Qais Yousef | c98c1822 | 2015-12-08 13:20:24 +0000 | [diff] [blame] | 476 | |
Matt Redfearn | 8ada00a | 2017-04-20 10:07:36 +0100 | [diff] [blame] | 477 | if (hwirq >= GIC_SHARED_HWIRQ_BASE) { |
Samuel Holland | 8190cc5 | 2022-07-01 15:00:49 -0500 | [diff] [blame] | 478 | #ifdef CONFIG_GENERIC_IRQ_IPI |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 479 | /* verify that shared irqs don't conflict with an IPI irq */ |
| 480 | if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv)) |
| 481 | return -EBUSY; |
Samuel Holland | 8190cc5 | 2022-07-01 15:00:49 -0500 | [diff] [blame] | 482 | #endif /* CONFIG_GENERIC_IRQ_IPI */ |
Qais Yousef | c98c1822 | 2015-12-08 13:20:24 +0000 | [diff] [blame] | 483 | |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 484 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, |
| 485 | &gic_level_irq_controller, |
| 486 | NULL); |
| 487 | if (err) |
| 488 | return err; |
| 489 | |
Marc Zyngier | 18416e4 | 2017-08-18 09:39:24 +0100 | [diff] [blame] | 490 | irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 491 | return gic_shared_irq_domain_map(d, virq, hwirq, 0); |
Qais Yousef | c98c1822 | 2015-12-08 13:20:24 +0000 | [diff] [blame] | 492 | } |
| 493 | |
Paul Burton | 63b746b1 | 2017-10-31 09:41:44 -0700 | [diff] [blame] | 494 | intr = GIC_HWIRQ_TO_LOCAL(hwirq); |
| 495 | map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin; |
| 496 | |
Marc Zyngier | dd098a0 | 2021-10-21 18:04:13 +0100 | [diff] [blame] | 497 | /* |
wangjianli | 915649d | 2022-10-22 13:46:55 +0800 | [diff] [blame] | 498 | * If adding support for more per-cpu interrupts, keep the |
Marc Zyngier | dd098a0 | 2021-10-21 18:04:13 +0100 | [diff] [blame] | 499 | * array in gic_all_vpes_irq_cpu_online() in sync. |
| 500 | */ |
Paul Burton | 63b746b1 | 2017-10-31 09:41:44 -0700 | [diff] [blame] | 501 | switch (intr) { |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 502 | case GIC_LOCAL_INT_TIMER: |
| 503 | case GIC_LOCAL_INT_PERFCTR: |
| 504 | case GIC_LOCAL_INT_FDC: |
| 505 | /* |
| 506 | * HACK: These are all really percpu interrupts, but |
| 507 | * the rest of the MIPS kernel code does not use the |
| 508 | * percpu IRQ API for them. |
| 509 | */ |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 510 | cd = &gic_all_vpes_chip_data[intr]; |
| 511 | cd->map = map; |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 512 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, |
| 513 | &gic_all_vpes_local_irq_controller, |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 514 | cd); |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 515 | if (err) |
| 516 | return err; |
| 517 | |
| 518 | irq_set_handler(virq, handle_percpu_irq); |
| 519 | break; |
| 520 | |
| 521 | default: |
| 522 | err = irq_domain_set_hwirq_and_chip(d, virq, hwirq, |
| 523 | &gic_local_irq_controller, |
| 524 | NULL); |
| 525 | if (err) |
| 526 | return err; |
| 527 | |
| 528 | irq_set_handler(virq, handle_percpu_devid_irq); |
| 529 | irq_set_percpu_devid(virq); |
| 530 | break; |
| 531 | } |
| 532 | |
Paul Burton | 63b746b1 | 2017-10-31 09:41:44 -0700 | [diff] [blame] | 533 | if (!gic_local_irq_is_routable(intr)) |
| 534 | return -EPERM; |
| 535 | |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 536 | raw_spin_lock_irqsave(&gic_lock, flags); |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 537 | for_each_online_cpu(cpu) { |
| 538 | write_gic_vl_other(mips_cm_vp_id(cpu)); |
Paul Burton | 6d4d367 | 2019-06-05 09:34:10 +0100 | [diff] [blame] | 539 | write_gic_vo_map(mips_gic_vx_map_reg(intr), map); |
Paul Burton | 63b746b1 | 2017-10-31 09:41:44 -0700 | [diff] [blame] | 540 | } |
Jiaxun Yang | 3d6a0e4 | 2023-04-24 11:31:56 +0100 | [diff] [blame] | 541 | raw_spin_unlock_irqrestore(&gic_lock, flags); |
Paul Burton | 63b746b1 | 2017-10-31 09:41:44 -0700 | [diff] [blame] | 542 | |
| 543 | return 0; |
Qais Yousef | c98c1822 | 2015-12-08 13:20:24 +0000 | [diff] [blame] | 544 | } |
| 545 | |
Matt Redfearn | 8ada00a | 2017-04-20 10:07:36 +0100 | [diff] [blame] | 546 | static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq, |
| 547 | unsigned int nr_irqs, void *arg) |
| 548 | { |
| 549 | struct irq_fwspec *fwspec = arg; |
| 550 | irq_hw_number_t hwirq; |
| 551 | |
| 552 | if (fwspec->param[0] == GIC_SHARED) |
| 553 | hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]); |
| 554 | else |
| 555 | hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]); |
| 556 | |
| 557 | return gic_irq_domain_map(d, virq, hwirq); |
| 558 | } |
| 559 | |
Arnd Bergmann | 90e921d | 2023-08-10 14:33:55 +0200 | [diff] [blame] | 560 | static void gic_irq_domain_free(struct irq_domain *d, unsigned int virq, |
Qais Yousef | c98c1822 | 2015-12-08 13:20:24 +0000 | [diff] [blame] | 561 | unsigned int nr_irqs) |
| 562 | { |
Qais Yousef | c98c1822 | 2015-12-08 13:20:24 +0000 | [diff] [blame] | 563 | } |
| 564 | |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 565 | static const struct irq_domain_ops gic_irq_domain_ops = { |
| 566 | .xlate = gic_irq_domain_xlate, |
| 567 | .alloc = gic_irq_domain_alloc, |
| 568 | .free = gic_irq_domain_free, |
Matt Redfearn | 8ada00a | 2017-04-20 10:07:36 +0100 | [diff] [blame] | 569 | .map = gic_irq_domain_map, |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 570 | }; |
| 571 | |
Samuel Holland | 8190cc5 | 2022-07-01 15:00:49 -0500 | [diff] [blame] | 572 | #ifdef CONFIG_GENERIC_IRQ_IPI |
| 573 | |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 574 | static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, |
| 575 | const u32 *intspec, unsigned int intsize, |
| 576 | irq_hw_number_t *out_hwirq, |
| 577 | unsigned int *out_type) |
| 578 | { |
| 579 | /* |
| 580 | * There's nothing to translate here. hwirq is dynamically allocated and |
| 581 | * the irq type is always edge triggered. |
| 582 | * */ |
| 583 | *out_hwirq = 0; |
| 584 | *out_type = IRQ_TYPE_EDGE_RISING; |
| 585 | |
| 586 | return 0; |
| 587 | } |
| 588 | |
| 589 | static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq, |
| 590 | unsigned int nr_irqs, void *arg) |
| 591 | { |
| 592 | struct cpumask *ipimask = arg; |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 593 | irq_hw_number_t hwirq, base_hwirq; |
| 594 | int cpu, ret, i; |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 595 | |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 596 | base_hwirq = find_first_bit(ipi_available, gic_shared_intrs); |
| 597 | if (base_hwirq == gic_shared_intrs) |
| 598 | return -ENOMEM; |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 599 | |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 600 | /* check that we have enough space */ |
| 601 | for (i = base_hwirq; i < nr_irqs; i++) { |
| 602 | if (!test_bit(i, ipi_available)) |
| 603 | return -EBUSY; |
| 604 | } |
| 605 | bitmap_clear(ipi_available, base_hwirq, nr_irqs); |
| 606 | |
| 607 | /* map the hwirq for each cpu consecutively */ |
| 608 | i = 0; |
| 609 | for_each_cpu(cpu, ipimask) { |
| 610 | hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i); |
| 611 | |
| 612 | ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq, |
| 613 | &gic_edge_irq_controller, |
| 614 | NULL); |
| 615 | if (ret) |
| 616 | goto error; |
| 617 | |
| 618 | ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq, |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 619 | &gic_edge_irq_controller, |
| 620 | NULL); |
| 621 | if (ret) |
| 622 | goto error; |
| 623 | |
| 624 | ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING); |
| 625 | if (ret) |
| 626 | goto error; |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 627 | |
| 628 | ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu); |
| 629 | if (ret) |
| 630 | goto error; |
| 631 | |
| 632 | i++; |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 633 | } |
| 634 | |
| 635 | return 0; |
| 636 | error: |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 637 | bitmap_set(ipi_available, base_hwirq, nr_irqs); |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 638 | return ret; |
| 639 | } |
| 640 | |
Wei Yongjun | b0e453f | 2020-07-14 22:22:45 +0800 | [diff] [blame] | 641 | static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq, |
| 642 | unsigned int nr_irqs) |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 643 | { |
Paul Burton | b87281e | 2017-04-20 10:07:35 +0100 | [diff] [blame] | 644 | irq_hw_number_t base_hwirq; |
| 645 | struct irq_data *data; |
| 646 | |
| 647 | data = irq_get_irq_data(virq); |
| 648 | if (!data) |
| 649 | return; |
| 650 | |
| 651 | base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data)); |
| 652 | bitmap_set(ipi_available, base_hwirq, nr_irqs); |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 653 | } |
| 654 | |
Wei Yongjun | b0e453f | 2020-07-14 22:22:45 +0800 | [diff] [blame] | 655 | static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node, |
| 656 | enum irq_domain_bus_token bus_token) |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 657 | { |
| 658 | bool is_ipi; |
| 659 | |
| 660 | switch (bus_token) { |
| 661 | case DOMAIN_BUS_IPI: |
| 662 | is_ipi = d->bus_token == bus_token; |
Paul Burton | 547aefc | 2016-07-05 14:26:00 +0100 | [diff] [blame] | 663 | return (!node || to_of_node(d->fwnode) == node) && is_ipi; |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 664 | break; |
| 665 | default: |
| 666 | return 0; |
| 667 | } |
| 668 | } |
| 669 | |
Tobias Klauser | 0b7e815 | 2017-06-02 10:20:56 +0200 | [diff] [blame] | 670 | static const struct irq_domain_ops gic_ipi_domain_ops = { |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 671 | .xlate = gic_ipi_domain_xlate, |
| 672 | .alloc = gic_ipi_domain_alloc, |
| 673 | .free = gic_ipi_domain_free, |
| 674 | .match = gic_ipi_domain_match, |
Andrew Bresticker | c49581a | 2014-09-18 14:47:23 -0700 | [diff] [blame] | 675 | }; |
| 676 | |
Samuel Holland | 8190cc5 | 2022-07-01 15:00:49 -0500 | [diff] [blame] | 677 | static int gic_register_ipi_domain(struct device_node *node) |
| 678 | { |
| 679 | struct irq_domain *gic_ipi_domain; |
| 680 | unsigned int v[2], num_ipis; |
| 681 | |
| 682 | gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain, |
| 683 | IRQ_DOMAIN_FLAG_IPI_PER_CPU, |
| 684 | GIC_NUM_LOCAL_INTRS + gic_shared_intrs, |
| 685 | node, &gic_ipi_domain_ops, NULL); |
| 686 | if (!gic_ipi_domain) { |
| 687 | pr_err("Failed to add IPI domain"); |
| 688 | return -ENXIO; |
| 689 | } |
| 690 | |
| 691 | irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI); |
| 692 | |
| 693 | if (node && |
| 694 | !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) { |
| 695 | bitmap_set(ipi_resrv, v[0], v[1]); |
| 696 | } else { |
| 697 | /* |
| 698 | * Reserve 2 interrupts per possible CPU/VP for use as IPIs, |
| 699 | * meeting the requirements of arch/mips SMP. |
| 700 | */ |
| 701 | num_ipis = 2 * num_possible_cpus(); |
| 702 | bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis); |
| 703 | } |
| 704 | |
| 705 | bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS); |
| 706 | |
| 707 | return 0; |
| 708 | } |
| 709 | |
| 710 | #else /* !CONFIG_GENERIC_IRQ_IPI */ |
| 711 | |
| 712 | static inline int gic_register_ipi_domain(struct device_node *node) |
| 713 | { |
| 714 | return 0; |
| 715 | } |
| 716 | |
| 717 | #endif /* !CONFIG_GENERIC_IRQ_IPI */ |
| 718 | |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 719 | static int gic_cpu_startup(unsigned int cpu) |
| 720 | { |
Paul Burton | 890f6b5 | 2017-10-31 09:41:47 -0700 | [diff] [blame] | 721 | /* Enable or disable EIC */ |
| 722 | change_gic_vl_ctl(GIC_VX_CTL_EIC, |
| 723 | cpu_has_veic ? GIC_VX_CTL_EIC : 0); |
| 724 | |
Paul Burton | 25ac19e | 2017-10-31 09:41:46 -0700 | [diff] [blame] | 725 | /* Clear all local IRQ masks (ie. disable all local interrupts) */ |
| 726 | write_gic_vl_rmask(~0); |
| 727 | |
Marc Zyngier | dd098a0 | 2021-10-21 18:04:13 +0100 | [diff] [blame] | 728 | /* Enable desired interrupts */ |
| 729 | gic_all_vpes_irq_cpu_online(); |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 730 | |
| 731 | return 0; |
| 732 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 733 | |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 734 | static int __init gic_of_init(struct device_node *node, |
| 735 | struct device_node *parent) |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 736 | { |
Samuel Holland | 8190cc5 | 2022-07-01 15:00:49 -0500 | [diff] [blame] | 737 | unsigned int cpu_vec, i, gicconfig; |
Paul Burton | b2b2e58 | 2017-08-12 21:36:44 -0700 | [diff] [blame] | 738 | unsigned long reserved; |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 739 | phys_addr_t gic_base; |
| 740 | struct resource res; |
| 741 | size_t gic_len; |
Samuel Holland | 8190cc5 | 2022-07-01 15:00:49 -0500 | [diff] [blame] | 742 | int ret; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 743 | |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 744 | /* Find the first available CPU vector. */ |
Paul Burton | b2b2e58 | 2017-08-12 21:36:44 -0700 | [diff] [blame] | 745 | i = 0; |
Paul Burton | a08588e | 2017-09-21 23:24:39 -0700 | [diff] [blame] | 746 | reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0); |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 747 | while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", |
| 748 | i++, &cpu_vec)) |
| 749 | reserved |= BIT(cpu_vec); |
Alex Smith | c0a9f72 | 2015-10-12 10:40:43 +0100 | [diff] [blame] | 750 | |
Paul Burton | b2b2e58 | 2017-08-12 21:36:44 -0700 | [diff] [blame] | 751 | cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM)); |
| 752 | if (cpu_vec == hweight_long(ST0_IM)) { |
Matt Redfearn | 1f19aee | 2017-11-09 11:02:44 +0000 | [diff] [blame] | 753 | pr_err("No CPU vectors available\n"); |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 754 | return -ENODEV; |
| 755 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 756 | |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 757 | if (of_address_to_resource(node, 0, &res)) { |
| 758 | /* |
| 759 | * Probe the CM for the GIC base address if not specified |
| 760 | * in the device-tree. |
| 761 | */ |
| 762 | if (mips_cm_present()) { |
| 763 | gic_base = read_gcr_gic_base() & |
| 764 | ~CM_GCR_GIC_BASE_GICEN; |
| 765 | gic_len = 0x20000; |
Matt Redfearn | 666740f | 2017-11-09 11:02:45 +0000 | [diff] [blame] | 766 | pr_warn("Using inherited base address %pa\n", |
| 767 | &gic_base); |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 768 | } else { |
Matt Redfearn | 1f19aee | 2017-11-09 11:02:44 +0000 | [diff] [blame] | 769 | pr_err("Failed to get memory range\n"); |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 770 | return -ENODEV; |
| 771 | } |
| 772 | } else { |
| 773 | gic_base = res.start; |
| 774 | gic_len = resource_size(&res); |
| 775 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 776 | |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 777 | if (mips_cm_present()) { |
| 778 | write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN); |
| 779 | /* Ensure GIC region is enabled before trying to access it */ |
| 780 | __sync(); |
| 781 | } |
| 782 | |
Christoph Hellwig | 4bdc0d6 | 2020-01-06 09:43:50 +0100 | [diff] [blame] | 783 | mips_gic_base = ioremap(gic_base, gic_len); |
William Dean | 71349cc | 2022-07-23 18:01:28 +0800 | [diff] [blame] | 784 | if (!mips_gic_base) { |
| 785 | pr_err("Failed to ioremap gic_base\n"); |
| 786 | return -ENOMEM; |
| 787 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 788 | |
Paul Burton | 3680746 | 2017-08-12 21:36:24 -0700 | [diff] [blame] | 789 | gicconfig = read_gic_config(); |
Geert Uytterhoeven | 357a9c4 | 2021-11-22 16:54:07 +0100 | [diff] [blame] | 790 | gic_shared_intrs = FIELD_GET(GIC_CONFIG_NUMINTERRUPTS, gicconfig); |
Paul Burton | 3680746 | 2017-08-12 21:36:24 -0700 | [diff] [blame] | 791 | gic_shared_intrs = (gic_shared_intrs + 1) * 8; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 792 | |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 793 | if (cpu_has_veic) { |
| 794 | /* Always use vector 1 in EIC mode */ |
| 795 | gic_cpu_pin = 0; |
| 796 | set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, |
| 797 | __gic_irq_dispatch); |
| 798 | } else { |
| 799 | gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; |
| 800 | irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, |
| 801 | gic_irq_dispatch); |
| 802 | } |
| 803 | |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 804 | gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 805 | gic_shared_intrs, 0, |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 806 | &gic_irq_domain_ops, NULL); |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 807 | if (!gic_irq_domain) { |
Matt Redfearn | 1f19aee | 2017-11-09 11:02:44 +0000 | [diff] [blame] | 808 | pr_err("Failed to add IRQ domain"); |
Paul Burton | fbea754 | 2017-08-12 21:36:40 -0700 | [diff] [blame] | 809 | return -ENXIO; |
| 810 | } |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 811 | |
Samuel Holland | 8190cc5 | 2022-07-01 15:00:49 -0500 | [diff] [blame] | 812 | ret = gic_register_ipi_domain(node); |
| 813 | if (ret) |
| 814 | return ret; |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 815 | |
Paul Burton | 87888bc | 2017-08-12 21:36:41 -0700 | [diff] [blame] | 816 | board_bind_eic_interrupt = &gic_bind_eic_interrupt; |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 817 | |
Paul Burton | 87888bc | 2017-08-12 21:36:41 -0700 | [diff] [blame] | 818 | /* Setup defaults */ |
| 819 | for (i = 0; i < gic_shared_intrs; i++) { |
| 820 | change_gic_pol(i, GIC_POL_ACTIVE_HIGH); |
| 821 | change_gic_trig(i, GIC_TRIG_LEVEL); |
Paul Burton | 90019f8 | 2017-09-05 11:28:46 -0700 | [diff] [blame] | 822 | write_gic_rmask(i); |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 823 | } |
| 824 | |
Paul Burton | da61fcf | 2017-10-31 09:41:45 -0700 | [diff] [blame] | 825 | return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING, |
| 826 | "irqchip/mips/gic:starting", |
| 827 | gic_cpu_startup, NULL); |
Andrew Bresticker | a705727 | 2014-11-12 11:43:38 -0800 | [diff] [blame] | 828 | } |
| 829 | IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init); |