blob: 76253e864f23049b0bd8246465690741654bafe2 [file] [log] [blame]
Steven J. Hill2299c492012-08-31 16:13:07 -05001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 */
Matt Redfearn1f19aee2017-11-09 11:02:44 +00009
10#define pr_fmt(fmt) "irq-mips-gic: " fmt
11
Geert Uytterhoeven357a9c42021-11-22 16:54:07 +010012#include <linux/bitfield.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010013#include <linux/bitmap.h>
Andrew Brestickerfb8f7be12014-10-20 12:03:55 -070014#include <linux/clocksource.h>
Paul Burtonda61fcf2017-10-31 09:41:45 -070015#include <linux/cpuhotplug.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010016#include <linux/init.h>
Andrew Bresticker18743d22014-09-18 14:47:24 -070017#include <linux/interrupt.h>
Andrew Brestickerfb8f7be12014-10-20 12:03:55 -070018#include <linux/irq.h>
Joel Porquet41a83e062015-07-07 17:11:46 -040019#include <linux/irqchip.h>
Marc Zyngier19827522018-09-13 09:30:34 +010020#include <linux/irqdomain.h>
Andrew Brestickera7057272014-11-12 11:43:38 -080021#include <linux/of_address.h>
Paul Burtonaa493732017-08-12 21:36:42 -070022#include <linux/percpu.h>
Andrew Bresticker18743d22014-09-18 14:47:24 -070023#include <linux/sched.h>
Ralf Baechle631330f2009-06-19 14:05:26 +010024#include <linux/smp.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010025
Paul Burtone83f7e02017-08-12 19:49:41 -070026#include <asm/mips-cps.h>
Steven J. Hill98b67c32012-08-31 16:18:49 -050027#include <asm/setup.h>
28#include <asm/traps.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010029
Andrew Brestickera7057272014-11-12 11:43:38 -080030#include <dt-bindings/interrupt-controller/mips-gic.h>
31
Paul Burtonb11d4c12017-08-12 21:36:29 -070032#define GIC_MAX_INTRS 256
Paul Burtonaa493732017-08-12 21:36:42 -070033#define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS)
Steven J. Hill98b67c32012-08-31 16:18:49 -050034
Paul Burtonb11d4c12017-08-12 21:36:29 -070035/* Add 2 to convert GIC CPU pin to core interrupt */
36#define GIC_CPU_PIN_OFFSET 2
Jeffrey Deans822350b2014-07-17 09:20:53 +010037
Paul Burtonb11d4c12017-08-12 21:36:29 -070038/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
39#define GIC_PIN_TO_VEC_OFFSET 1
Qais Yousef2af70a92015-12-08 13:20:23 +000040
Paul Burtonb11d4c12017-08-12 21:36:29 -070041/* Convert between local/shared IRQ number and GIC HW IRQ number. */
42#define GIC_LOCAL_HWIRQ_BASE 0
43#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
44#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
45#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
46#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
47#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
48
Paul Burton582e2b42017-08-12 21:36:10 -070049void __iomem *mips_gic_base;
Steven J. Hill0b271f52012-08-31 16:05:37 -050050
Wei Yongjunb0e453f2020-07-14 22:22:45 +080051static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
Jeffrey Deans822350b2014-07-17 09:20:53 +010052
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +010053static DEFINE_RAW_SPINLOCK(gic_lock);
Andrew Brestickerc49581a2014-09-18 14:47:23 -070054static struct irq_domain *gic_irq_domain;
Andrew Brestickerfbd55242014-09-18 14:47:25 -070055static int gic_shared_intrs;
Andrew Bresticker3263d082014-09-18 14:47:28 -070056static unsigned int gic_cpu_pin;
Andrew Bresticker4a6a3ea32014-09-18 14:47:26 -070057static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
Samuel Holland8190cc52022-07-01 15:00:49 -050058
59#ifdef CONFIG_GENERIC_IRQ_IPI
Paul Burton61dc3672017-10-31 09:41:51 -070060static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
61static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
Samuel Holland8190cc52022-07-01 15:00:49 -050062#endif /* CONFIG_GENERIC_IRQ_IPI */
Ralf Baechle39b8d522008-04-28 17:14:26 +010063
Paul Burtonda61fcf2017-10-31 09:41:45 -070064static struct gic_all_vpes_chip_data {
65 u32 map;
66 bool mask;
67} gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
68
Paul Burton7778c4b2017-08-18 14:02:21 -070069static void gic_clear_pcpu_masks(unsigned int intr)
Andrew Bresticker5f68fea2014-10-20 12:03:52 -070070{
Paul Burton7778c4b2017-08-18 14:02:21 -070071 unsigned int i;
Andrew Bresticker5f68fea2014-10-20 12:03:52 -070072
Paul Burton7778c4b2017-08-18 14:02:21 -070073 /* Clear the interrupt's bit in all pcpu_masks */
74 for_each_possible_cpu(i)
75 clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
Paul Burton835d2b42016-02-03 03:15:28 +000076}
77
Andrew Brestickere9de6882014-09-18 14:47:27 -070078static bool gic_local_irq_is_routable(int intr)
79{
80 u32 vpe_ctl;
81
82 /* All local interrupts are routable in EIC mode. */
83 if (cpu_has_veic)
84 return true;
85
Paul Burton0d0cf582017-08-12 21:36:26 -070086 vpe_ctl = read_gic_vl_ctl();
Andrew Brestickere9de6882014-09-18 14:47:27 -070087 switch (intr) {
88 case GIC_LOCAL_INT_TIMER:
Paul Burton0d0cf582017-08-12 21:36:26 -070089 return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
Andrew Brestickere9de6882014-09-18 14:47:27 -070090 case GIC_LOCAL_INT_PERFCTR:
Paul Burton0d0cf582017-08-12 21:36:26 -070091 return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
Andrew Brestickere9de6882014-09-18 14:47:27 -070092 case GIC_LOCAL_INT_FDC:
Paul Burton0d0cf582017-08-12 21:36:26 -070093 return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
Andrew Brestickere9de6882014-09-18 14:47:27 -070094 case GIC_LOCAL_INT_SWINT0:
95 case GIC_LOCAL_INT_SWINT1:
Paul Burton0d0cf582017-08-12 21:36:26 -070096 return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
Andrew Brestickere9de6882014-09-18 14:47:27 -070097 default:
98 return true;
99 }
100}
101
Andrew Bresticker3263d082014-09-18 14:47:28 -0700102static void gic_bind_eic_interrupt(int irq, int set)
Steven J. Hill98b67c32012-08-31 16:18:49 -0500103{
104 /* Convert irq vector # to hw int # */
105 irq -= GIC_PIN_TO_VEC_OFFSET;
106
107 /* Set irq to use shadow set */
Paul Burton0d0cf582017-08-12 21:36:26 -0700108 write_gic_vl_eic_shadow_set(irq, set);
Steven J. Hill98b67c32012-08-31 16:18:49 -0500109}
110
Qais Yousefbb11cff2015-12-08 13:20:28 +0000111static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
Ralf Baechle39b8d522008-04-28 17:14:26 +0100112{
Qais Yousefbb11cff2015-12-08 13:20:28 +0000113 irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
114
Paul Burton36807462017-08-12 21:36:24 -0700115 write_gic_wedge(GIC_WEDGE_RW | hwirq);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100116}
117
Andrew Brestickere9de6882014-09-18 14:47:27 -0700118int gic_get_c0_compare_int(void)
119{
120 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
121 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
122 return irq_create_mapping(gic_irq_domain,
123 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
124}
125
126int gic_get_c0_perfcount_int(void)
127{
128 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
James Hogan7e3e6cb2015-01-27 21:45:50 +0000129 /* Is the performance counter shared with the timer? */
Andrew Brestickere9de6882014-09-18 14:47:27 -0700130 if (cp0_perfcount_irq < 0)
131 return -1;
132 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
133 }
134 return irq_create_mapping(gic_irq_domain,
135 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
136}
137
James Hogan6429e2b2015-01-29 11:14:09 +0000138int gic_get_c0_fdc_int(void)
139{
140 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
141 /* Is the FDC IRQ even present? */
142 if (cp0_fdc_irq < 0)
143 return -1;
144 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
145 }
146
James Hogan6429e2b2015-01-29 11:14:09 +0000147 return irq_create_mapping(gic_irq_domain,
148 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
149}
150
Rabin Vincent1b3ed362015-06-12 10:01:56 +0200151static void gic_handle_shared_int(bool chained)
Ralf Baechle39b8d522008-04-28 17:14:26 +0100152{
Marc Zyngier046a6ee2021-05-04 17:42:18 +0100153 unsigned int intr;
Andrew Bresticker8f5ee792014-10-20 12:03:56 -0700154 unsigned long *pcpu_mask;
Andrew Bresticker8f5ee792014-10-20 12:03:56 -0700155 DECLARE_BITMAP(pending, GIC_MAX_INTRS);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100156
157 /* Get per-cpu bitmaps */
Paul Burtonaa493732017-08-12 21:36:42 -0700158 pcpu_mask = this_cpu_ptr(pcpu_masks);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100159
Paul Burton7778c4b2017-08-18 14:02:21 -0700160 if (mips_cm_is64)
Paul Burtone98fcb22017-08-12 21:36:16 -0700161 __ioread64_copy(pending, addr_gic_pend(),
162 DIV_ROUND_UP(gic_shared_intrs, 64));
Paul Burton7778c4b2017-08-18 14:02:21 -0700163 else
Paul Burtone98fcb22017-08-12 21:36:16 -0700164 __ioread32_copy(pending, addr_gic_pend(),
165 DIV_ROUND_UP(gic_shared_intrs, 32));
Ralf Baechle39b8d522008-04-28 17:14:26 +0100166
Andrew Brestickerfbd55242014-09-18 14:47:25 -0700167 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100168
Paul Burtoncae750b2016-08-19 18:11:19 +0100169 for_each_set_bit(intr, pending, gic_shared_intrs) {
Rabin Vincent1b3ed362015-06-12 10:01:56 +0200170 if (chained)
Marc Zyngier046a6ee2021-05-04 17:42:18 +0100171 generic_handle_domain_irq(gic_irq_domain,
172 GIC_SHARED_TO_HWIRQ(intr));
Rabin Vincent1b3ed362015-06-12 10:01:56 +0200173 else
Marc Zyngier1fee9db2021-07-06 11:38:59 +0100174 do_domain_IRQ(gic_irq_domain,
175 GIC_SHARED_TO_HWIRQ(intr));
Qais Yousefd7eb4f22015-01-19 11:51:29 +0000176 }
Ralf Baechle39b8d522008-04-28 17:14:26 +0100177}
178
Thomas Gleixner161d0492011-03-23 21:08:58 +0000179static void gic_mask_irq(struct irq_data *d)
Ralf Baechle39b8d522008-04-28 17:14:26 +0100180{
Paul Burton7778c4b2017-08-18 14:02:21 -0700181 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
182
Paul Burton90019f82017-09-05 11:28:46 -0700183 write_gic_rmask(intr);
Paul Burton7778c4b2017-08-18 14:02:21 -0700184 gic_clear_pcpu_masks(intr);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100185}
186
Thomas Gleixner161d0492011-03-23 21:08:58 +0000187static void gic_unmask_irq(struct irq_data *d)
Ralf Baechle39b8d522008-04-28 17:14:26 +0100188{
Paul Burton7778c4b2017-08-18 14:02:21 -0700189 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
190 unsigned int cpu;
191
Paul Burton90019f82017-09-05 11:28:46 -0700192 write_gic_smask(intr);
Paul Burton7778c4b2017-08-18 14:02:21 -0700193
194 gic_clear_pcpu_masks(intr);
Paul Burtond9f82932017-09-21 23:24:40 -0700195 cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
Paul Burton7778c4b2017-08-18 14:02:21 -0700196 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
Ralf Baechle39b8d522008-04-28 17:14:26 +0100197}
198
Andrew Bresticker5561c9e2014-09-18 14:47:20 -0700199static void gic_ack_irq(struct irq_data *d)
200{
Andrew Brestickere9de6882014-09-18 14:47:27 -0700201 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
Andrew Brestickerc49581a2014-09-18 14:47:23 -0700202
Paul Burton36807462017-08-12 21:36:24 -0700203 write_gic_wedge(irq);
Andrew Bresticker5561c9e2014-09-18 14:47:20 -0700204}
205
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700206static int gic_set_type(struct irq_data *d, unsigned int type)
207{
Paul Burton5af3e932017-10-31 09:41:50 -0700208 unsigned int irq, pol, trig, dual;
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700209 unsigned long flags;
Paul Burton5af3e932017-10-31 09:41:50 -0700210
211 irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100212
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100213 raw_spin_lock_irqsave(&gic_lock, flags);
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700214 switch (type & IRQ_TYPE_SENSE_MASK) {
215 case IRQ_TYPE_EDGE_FALLING:
Paul Burton5af3e932017-10-31 09:41:50 -0700216 pol = GIC_POL_FALLING_EDGE;
217 trig = GIC_TRIG_EDGE;
218 dual = GIC_DUAL_SINGLE;
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700219 break;
220 case IRQ_TYPE_EDGE_RISING:
Paul Burton5af3e932017-10-31 09:41:50 -0700221 pol = GIC_POL_RISING_EDGE;
222 trig = GIC_TRIG_EDGE;
223 dual = GIC_DUAL_SINGLE;
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700224 break;
225 case IRQ_TYPE_EDGE_BOTH:
Paul Burton5af3e932017-10-31 09:41:50 -0700226 pol = 0; /* Doesn't matter */
227 trig = GIC_TRIG_EDGE;
228 dual = GIC_DUAL_DUAL;
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700229 break;
230 case IRQ_TYPE_LEVEL_LOW:
Paul Burton5af3e932017-10-31 09:41:50 -0700231 pol = GIC_POL_ACTIVE_LOW;
232 trig = GIC_TRIG_LEVEL;
233 dual = GIC_DUAL_SINGLE;
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700234 break;
235 case IRQ_TYPE_LEVEL_HIGH:
236 default:
Paul Burton5af3e932017-10-31 09:41:50 -0700237 pol = GIC_POL_ACTIVE_HIGH;
238 trig = GIC_TRIG_LEVEL;
239 dual = GIC_DUAL_SINGLE;
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700240 break;
241 }
242
Paul Burton5af3e932017-10-31 09:41:50 -0700243 change_gic_pol(irq, pol);
244 change_gic_trig(irq, trig);
245 change_gic_dual(irq, dual);
246
247 if (trig == GIC_TRIG_EDGE)
Thomas Gleixnera595fc52015-06-23 14:41:25 +0200248 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
249 handle_edge_irq, NULL);
250 else
251 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
252 handle_level_irq, NULL);
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100253 raw_spin_unlock_irqrestore(&gic_lock, flags);
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700254
255 return 0;
256}
257
258#ifdef CONFIG_SMP
Thomas Gleixner161d0492011-03-23 21:08:58 +0000259static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
260 bool force)
Ralf Baechle39b8d522008-04-28 17:14:26 +0100261{
Andrew Brestickere9de6882014-09-18 14:47:27 -0700262 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
Paul Burton07df8bf2017-08-18 14:04:35 -0700263 unsigned long flags;
264 unsigned int cpu;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100265
Paul Burton07df8bf2017-08-18 14:04:35 -0700266 cpu = cpumask_first_and(cpumask, cpu_online_mask);
267 if (cpu >= NR_CPUS)
Andrew Bresticker14d160a2014-09-18 14:47:22 -0700268 return -EINVAL;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100269
270 /* Assumption : cpumask refers to a single CPU */
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100271 raw_spin_lock_irqsave(&gic_lock, flags);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100272
Tony Wuc214c032013-06-21 10:13:08 +0000273 /* Re-route this IRQ */
Paul Burton07df8bf2017-08-18 14:04:35 -0700274 write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
Ralf Baechle39b8d522008-04-28 17:14:26 +0100275
Tony Wuc214c032013-06-21 10:13:08 +0000276 /* Update the pcpu_masks */
Paul Burton7778c4b2017-08-18 14:02:21 -0700277 gic_clear_pcpu_masks(irq);
278 if (read_gic_mask(irq))
Paul Burton07df8bf2017-08-18 14:04:35 -0700279 set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
Tony Wuc214c032013-06-21 10:13:08 +0000280
Marc Zyngier18416e42017-08-18 09:39:24 +0100281 irq_data_update_effective_affinity(d, cpumask_of(cpu));
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100282 raw_spin_unlock_irqrestore(&gic_lock, flags);
Ralf Baechle39b8d522008-04-28 17:14:26 +0100283
Paul Burton7f15a642017-08-12 21:36:46 -0700284 return IRQ_SET_MASK_OK;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100285}
286#endif
287
Andrew Bresticker4a6a3ea32014-09-18 14:47:26 -0700288static struct irq_chip gic_level_irq_controller = {
289 .name = "MIPS GIC",
290 .irq_mask = gic_mask_irq,
291 .irq_unmask = gic_unmask_irq,
292 .irq_set_type = gic_set_type,
293#ifdef CONFIG_SMP
294 .irq_set_affinity = gic_set_affinity,
295#endif
296};
297
298static struct irq_chip gic_edge_irq_controller = {
Thomas Gleixner161d0492011-03-23 21:08:58 +0000299 .name = "MIPS GIC",
Andrew Bresticker5561c9e2014-09-18 14:47:20 -0700300 .irq_ack = gic_ack_irq,
Thomas Gleixner161d0492011-03-23 21:08:58 +0000301 .irq_mask = gic_mask_irq,
Thomas Gleixner161d0492011-03-23 21:08:58 +0000302 .irq_unmask = gic_unmask_irq,
Andrew Bresticker95150ae2014-09-18 14:47:21 -0700303 .irq_set_type = gic_set_type,
Ralf Baechle39b8d522008-04-28 17:14:26 +0100304#ifdef CONFIG_SMP
Thomas Gleixner161d0492011-03-23 21:08:58 +0000305 .irq_set_affinity = gic_set_affinity,
Ralf Baechle39b8d522008-04-28 17:14:26 +0100306#endif
Qais Yousefbb11cff2015-12-08 13:20:28 +0000307 .ipi_send_single = gic_send_ipi,
Ralf Baechle39b8d522008-04-28 17:14:26 +0100308};
309
Rabin Vincent1b3ed362015-06-12 10:01:56 +0200310static void gic_handle_local_int(bool chained)
Andrew Brestickere9de6882014-09-18 14:47:27 -0700311{
312 unsigned long pending, masked;
Marc Zyngier046a6ee2021-05-04 17:42:18 +0100313 unsigned int intr;
Andrew Brestickere9de6882014-09-18 14:47:27 -0700314
Paul Burton9da3c642017-08-12 21:36:25 -0700315 pending = read_gic_vl_pend();
316 masked = read_gic_vl_mask();
Andrew Brestickere9de6882014-09-18 14:47:27 -0700317
318 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
319
Paul Burton0f4ed152016-09-13 17:54:27 +0100320 for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) {
Rabin Vincent1b3ed362015-06-12 10:01:56 +0200321 if (chained)
Marc Zyngier046a6ee2021-05-04 17:42:18 +0100322 generic_handle_domain_irq(gic_irq_domain,
323 GIC_LOCAL_TO_HWIRQ(intr));
Rabin Vincent1b3ed362015-06-12 10:01:56 +0200324 else
Marc Zyngier1fee9db2021-07-06 11:38:59 +0100325 do_domain_IRQ(gic_irq_domain,
326 GIC_LOCAL_TO_HWIRQ(intr));
Qais Yousefd7eb4f22015-01-19 11:51:29 +0000327 }
Andrew Brestickere9de6882014-09-18 14:47:27 -0700328}
329
330static void gic_mask_local_irq(struct irq_data *d)
331{
332 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
333
Paul Burton9da3c642017-08-12 21:36:25 -0700334 write_gic_vl_rmask(BIT(intr));
Andrew Brestickere9de6882014-09-18 14:47:27 -0700335}
336
337static void gic_unmask_local_irq(struct irq_data *d)
338{
339 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
340
Paul Burton9da3c642017-08-12 21:36:25 -0700341 write_gic_vl_smask(BIT(intr));
Andrew Brestickere9de6882014-09-18 14:47:27 -0700342}
343
344static struct irq_chip gic_local_irq_controller = {
345 .name = "MIPS GIC Local",
346 .irq_mask = gic_mask_local_irq,
347 .irq_unmask = gic_unmask_local_irq,
348};
349
350static void gic_mask_local_irq_all_vpes(struct irq_data *d)
351{
Paul Burtonda61fcf2017-10-31 09:41:45 -0700352 struct gic_all_vpes_chip_data *cd;
Andrew Brestickere9de6882014-09-18 14:47:27 -0700353 unsigned long flags;
Paul Burtonda61fcf2017-10-31 09:41:45 -0700354 int intr, cpu;
355
356 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
357 cd = irq_data_get_irq_chip_data(d);
358 cd->mask = false;
Andrew Brestickere9de6882014-09-18 14:47:27 -0700359
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100360 raw_spin_lock_irqsave(&gic_lock, flags);
Paul Burtonda61fcf2017-10-31 09:41:45 -0700361 for_each_online_cpu(cpu) {
362 write_gic_vl_other(mips_cm_vp_id(cpu));
Paul Burton9da3c642017-08-12 21:36:25 -0700363 write_gic_vo_rmask(BIT(intr));
Andrew Brestickere9de6882014-09-18 14:47:27 -0700364 }
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100365 raw_spin_unlock_irqrestore(&gic_lock, flags);
Andrew Brestickere9de6882014-09-18 14:47:27 -0700366}
367
368static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
369{
Paul Burtonda61fcf2017-10-31 09:41:45 -0700370 struct gic_all_vpes_chip_data *cd;
Andrew Brestickere9de6882014-09-18 14:47:27 -0700371 unsigned long flags;
Paul Burtonda61fcf2017-10-31 09:41:45 -0700372 int intr, cpu;
373
374 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
375 cd = irq_data_get_irq_chip_data(d);
376 cd->mask = true;
Andrew Brestickere9de6882014-09-18 14:47:27 -0700377
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100378 raw_spin_lock_irqsave(&gic_lock, flags);
Paul Burtonda61fcf2017-10-31 09:41:45 -0700379 for_each_online_cpu(cpu) {
380 write_gic_vl_other(mips_cm_vp_id(cpu));
Paul Burton9da3c642017-08-12 21:36:25 -0700381 write_gic_vo_smask(BIT(intr));
Andrew Brestickere9de6882014-09-18 14:47:27 -0700382 }
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100383 raw_spin_unlock_irqrestore(&gic_lock, flags);
Andrew Brestickere9de6882014-09-18 14:47:27 -0700384}
385
Marc Zyngierdd098a02021-10-21 18:04:13 +0100386static void gic_all_vpes_irq_cpu_online(void)
Paul Burtonda61fcf2017-10-31 09:41:45 -0700387{
Marc Zyngierdd098a02021-10-21 18:04:13 +0100388 static const unsigned int local_intrs[] = {
389 GIC_LOCAL_INT_TIMER,
390 GIC_LOCAL_INT_PERFCTR,
391 GIC_LOCAL_INT_FDC,
392 };
393 unsigned long flags;
394 int i;
Paul Burtonda61fcf2017-10-31 09:41:45 -0700395
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100396 raw_spin_lock_irqsave(&gic_lock, flags);
Paul Burtonda61fcf2017-10-31 09:41:45 -0700397
Marc Zyngierdd098a02021-10-21 18:04:13 +0100398 for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
399 unsigned int intr = local_intrs[i];
400 struct gic_all_vpes_chip_data *cd;
401
Jiaxun Yang2c6c9c02023-04-24 11:31:55 +0100402 if (!gic_local_irq_is_routable(intr))
403 continue;
Marc Zyngierdd098a02021-10-21 18:04:13 +0100404 cd = &gic_all_vpes_chip_data[intr];
405 write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
406 if (cd->mask)
407 write_gic_vl_smask(BIT(intr));
408 }
409
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100410 raw_spin_unlock_irqrestore(&gic_lock, flags);
Paul Burtonda61fcf2017-10-31 09:41:45 -0700411}
412
Andrew Brestickere9de6882014-09-18 14:47:27 -0700413static struct irq_chip gic_all_vpes_local_irq_controller = {
Paul Burtonda61fcf2017-10-31 09:41:45 -0700414 .name = "MIPS GIC Local",
415 .irq_mask = gic_mask_local_irq_all_vpes,
416 .irq_unmask = gic_unmask_local_irq_all_vpes,
Andrew Brestickere9de6882014-09-18 14:47:27 -0700417};
418
Andrew Bresticker18743d22014-09-18 14:47:24 -0700419static void __gic_irq_dispatch(void)
Ralf Baechle39b8d522008-04-28 17:14:26 +0100420{
Rabin Vincent1b3ed362015-06-12 10:01:56 +0200421 gic_handle_local_int(false);
422 gic_handle_shared_int(false);
Andrew Bresticker18743d22014-09-18 14:47:24 -0700423}
424
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200425static void gic_irq_dispatch(struct irq_desc *desc)
Andrew Bresticker18743d22014-09-18 14:47:24 -0700426{
Rabin Vincent1b3ed362015-06-12 10:01:56 +0200427 gic_handle_local_int(true);
428 gic_handle_shared_int(true);
Andrew Bresticker18743d22014-09-18 14:47:24 -0700429}
430
Andrew Brestickere9de6882014-09-18 14:47:27 -0700431static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
Paul Burton7778c4b2017-08-18 14:02:21 -0700432 irq_hw_number_t hw, unsigned int cpu)
Andrew Brestickere9de6882014-09-18 14:47:27 -0700433{
434 int intr = GIC_HWIRQ_TO_SHARED(hw);
Paul Burtond9f82932017-09-21 23:24:40 -0700435 struct irq_data *data;
Andrew Brestickerc49581a2014-09-18 14:47:23 -0700436 unsigned long flags;
437
Paul Burtond9f82932017-09-21 23:24:40 -0700438 data = irq_get_irq_data(virq);
439
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100440 raw_spin_lock_irqsave(&gic_lock, flags);
Paul Burtond3e8cf42017-08-12 21:36:22 -0700441 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
Paul Burton7778c4b2017-08-18 14:02:21 -0700442 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
Paul Burtond9f82932017-09-21 23:24:40 -0700443 irq_data_update_effective_affinity(data, cpumask_of(cpu));
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100444 raw_spin_unlock_irqrestore(&gic_lock, flags);
Andrew Brestickerc49581a2014-09-18 14:47:23 -0700445
446 return 0;
447}
448
Paul Burtonb87281e2017-04-20 10:07:35 +0100449static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
Qais Yousefc98c18222015-12-08 13:20:24 +0000450 const u32 *intspec, unsigned int intsize,
451 irq_hw_number_t *out_hwirq,
452 unsigned int *out_type)
453{
454 if (intsize != 3)
455 return -EINVAL;
456
457 if (intspec[0] == GIC_SHARED)
458 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
459 else if (intspec[0] == GIC_LOCAL)
460 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
461 else
462 return -EINVAL;
463 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
464
465 return 0;
466}
467
Matt Redfearn8ada00a2017-04-20 10:07:36 +0100468static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
469 irq_hw_number_t hwirq)
Qais Yousefc98c18222015-12-08 13:20:24 +0000470{
Paul Burtonda61fcf2017-10-31 09:41:45 -0700471 struct gic_all_vpes_chip_data *cd;
Paul Burton63b746b12017-10-31 09:41:44 -0700472 unsigned long flags;
473 unsigned int intr;
Paul Burtonda61fcf2017-10-31 09:41:45 -0700474 int err, cpu;
Paul Burton63b746b12017-10-31 09:41:44 -0700475 u32 map;
Qais Yousefc98c18222015-12-08 13:20:24 +0000476
Matt Redfearn8ada00a2017-04-20 10:07:36 +0100477 if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
Samuel Holland8190cc52022-07-01 15:00:49 -0500478#ifdef CONFIG_GENERIC_IRQ_IPI
Paul Burtonb87281e2017-04-20 10:07:35 +0100479 /* verify that shared irqs don't conflict with an IPI irq */
480 if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
481 return -EBUSY;
Samuel Holland8190cc52022-07-01 15:00:49 -0500482#endif /* CONFIG_GENERIC_IRQ_IPI */
Qais Yousefc98c18222015-12-08 13:20:24 +0000483
Paul Burtonb87281e2017-04-20 10:07:35 +0100484 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
485 &gic_level_irq_controller,
486 NULL);
487 if (err)
488 return err;
489
Marc Zyngier18416e42017-08-18 09:39:24 +0100490 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
Paul Burtonb87281e2017-04-20 10:07:35 +0100491 return gic_shared_irq_domain_map(d, virq, hwirq, 0);
Qais Yousefc98c18222015-12-08 13:20:24 +0000492 }
493
Paul Burton63b746b12017-10-31 09:41:44 -0700494 intr = GIC_HWIRQ_TO_LOCAL(hwirq);
495 map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
496
Marc Zyngierdd098a02021-10-21 18:04:13 +0100497 /*
wangjianli915649d2022-10-22 13:46:55 +0800498 * If adding support for more per-cpu interrupts, keep the
Marc Zyngierdd098a02021-10-21 18:04:13 +0100499 * array in gic_all_vpes_irq_cpu_online() in sync.
500 */
Paul Burton63b746b12017-10-31 09:41:44 -0700501 switch (intr) {
Paul Burtonb87281e2017-04-20 10:07:35 +0100502 case GIC_LOCAL_INT_TIMER:
503 case GIC_LOCAL_INT_PERFCTR:
504 case GIC_LOCAL_INT_FDC:
505 /*
506 * HACK: These are all really percpu interrupts, but
507 * the rest of the MIPS kernel code does not use the
508 * percpu IRQ API for them.
509 */
Paul Burtonda61fcf2017-10-31 09:41:45 -0700510 cd = &gic_all_vpes_chip_data[intr];
511 cd->map = map;
Paul Burtonb87281e2017-04-20 10:07:35 +0100512 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
513 &gic_all_vpes_local_irq_controller,
Paul Burtonda61fcf2017-10-31 09:41:45 -0700514 cd);
Paul Burtonb87281e2017-04-20 10:07:35 +0100515 if (err)
516 return err;
517
518 irq_set_handler(virq, handle_percpu_irq);
519 break;
520
521 default:
522 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
523 &gic_local_irq_controller,
524 NULL);
525 if (err)
526 return err;
527
528 irq_set_handler(virq, handle_percpu_devid_irq);
529 irq_set_percpu_devid(virq);
530 break;
531 }
532
Paul Burton63b746b12017-10-31 09:41:44 -0700533 if (!gic_local_irq_is_routable(intr))
534 return -EPERM;
535
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100536 raw_spin_lock_irqsave(&gic_lock, flags);
Paul Burtonda61fcf2017-10-31 09:41:45 -0700537 for_each_online_cpu(cpu) {
538 write_gic_vl_other(mips_cm_vp_id(cpu));
Paul Burton6d4d3672019-06-05 09:34:10 +0100539 write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
Paul Burton63b746b12017-10-31 09:41:44 -0700540 }
Jiaxun Yang3d6a0e42023-04-24 11:31:56 +0100541 raw_spin_unlock_irqrestore(&gic_lock, flags);
Paul Burton63b746b12017-10-31 09:41:44 -0700542
543 return 0;
Qais Yousefc98c18222015-12-08 13:20:24 +0000544}
545
Matt Redfearn8ada00a2017-04-20 10:07:36 +0100546static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
547 unsigned int nr_irqs, void *arg)
548{
549 struct irq_fwspec *fwspec = arg;
550 irq_hw_number_t hwirq;
551
552 if (fwspec->param[0] == GIC_SHARED)
553 hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);
554 else
555 hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);
556
557 return gic_irq_domain_map(d, virq, hwirq);
558}
559
Arnd Bergmann90e921d2023-08-10 14:33:55 +0200560static void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
Qais Yousefc98c18222015-12-08 13:20:24 +0000561 unsigned int nr_irqs)
562{
Qais Yousefc98c18222015-12-08 13:20:24 +0000563}
564
Paul Burtonb87281e2017-04-20 10:07:35 +0100565static const struct irq_domain_ops gic_irq_domain_ops = {
566 .xlate = gic_irq_domain_xlate,
567 .alloc = gic_irq_domain_alloc,
568 .free = gic_irq_domain_free,
Matt Redfearn8ada00a2017-04-20 10:07:36 +0100569 .map = gic_irq_domain_map,
Qais Yousef2af70a92015-12-08 13:20:23 +0000570};
571
Samuel Holland8190cc52022-07-01 15:00:49 -0500572#ifdef CONFIG_GENERIC_IRQ_IPI
573
Qais Yousef2af70a92015-12-08 13:20:23 +0000574static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
575 const u32 *intspec, unsigned int intsize,
576 irq_hw_number_t *out_hwirq,
577 unsigned int *out_type)
578{
579 /*
580 * There's nothing to translate here. hwirq is dynamically allocated and
581 * the irq type is always edge triggered.
582 * */
583 *out_hwirq = 0;
584 *out_type = IRQ_TYPE_EDGE_RISING;
585
586 return 0;
587}
588
589static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
590 unsigned int nr_irqs, void *arg)
591{
592 struct cpumask *ipimask = arg;
Paul Burtonb87281e2017-04-20 10:07:35 +0100593 irq_hw_number_t hwirq, base_hwirq;
594 int cpu, ret, i;
Qais Yousef2af70a92015-12-08 13:20:23 +0000595
Paul Burtonb87281e2017-04-20 10:07:35 +0100596 base_hwirq = find_first_bit(ipi_available, gic_shared_intrs);
597 if (base_hwirq == gic_shared_intrs)
598 return -ENOMEM;
Qais Yousef2af70a92015-12-08 13:20:23 +0000599
Paul Burtonb87281e2017-04-20 10:07:35 +0100600 /* check that we have enough space */
601 for (i = base_hwirq; i < nr_irqs; i++) {
602 if (!test_bit(i, ipi_available))
603 return -EBUSY;
604 }
605 bitmap_clear(ipi_available, base_hwirq, nr_irqs);
606
607 /* map the hwirq for each cpu consecutively */
608 i = 0;
609 for_each_cpu(cpu, ipimask) {
610 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
611
612 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
613 &gic_edge_irq_controller,
614 NULL);
615 if (ret)
616 goto error;
617
618 ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
Qais Yousef2af70a92015-12-08 13:20:23 +0000619 &gic_edge_irq_controller,
620 NULL);
621 if (ret)
622 goto error;
623
624 ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
625 if (ret)
626 goto error;
Paul Burtonb87281e2017-04-20 10:07:35 +0100627
628 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
629 if (ret)
630 goto error;
631
632 i++;
Qais Yousef2af70a92015-12-08 13:20:23 +0000633 }
634
635 return 0;
636error:
Paul Burtonb87281e2017-04-20 10:07:35 +0100637 bitmap_set(ipi_available, base_hwirq, nr_irqs);
Qais Yousef2af70a92015-12-08 13:20:23 +0000638 return ret;
639}
640
Wei Yongjunb0e453f2020-07-14 22:22:45 +0800641static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
642 unsigned int nr_irqs)
Qais Yousef2af70a92015-12-08 13:20:23 +0000643{
Paul Burtonb87281e2017-04-20 10:07:35 +0100644 irq_hw_number_t base_hwirq;
645 struct irq_data *data;
646
647 data = irq_get_irq_data(virq);
648 if (!data)
649 return;
650
651 base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
652 bitmap_set(ipi_available, base_hwirq, nr_irqs);
Qais Yousef2af70a92015-12-08 13:20:23 +0000653}
654
Wei Yongjunb0e453f2020-07-14 22:22:45 +0800655static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
656 enum irq_domain_bus_token bus_token)
Qais Yousef2af70a92015-12-08 13:20:23 +0000657{
658 bool is_ipi;
659
660 switch (bus_token) {
661 case DOMAIN_BUS_IPI:
662 is_ipi = d->bus_token == bus_token;
Paul Burton547aefc2016-07-05 14:26:00 +0100663 return (!node || to_of_node(d->fwnode) == node) && is_ipi;
Qais Yousef2af70a92015-12-08 13:20:23 +0000664 break;
665 default:
666 return 0;
667 }
668}
669
Tobias Klauser0b7e8152017-06-02 10:20:56 +0200670static const struct irq_domain_ops gic_ipi_domain_ops = {
Qais Yousef2af70a92015-12-08 13:20:23 +0000671 .xlate = gic_ipi_domain_xlate,
672 .alloc = gic_ipi_domain_alloc,
673 .free = gic_ipi_domain_free,
674 .match = gic_ipi_domain_match,
Andrew Brestickerc49581a2014-09-18 14:47:23 -0700675};
676
Samuel Holland8190cc52022-07-01 15:00:49 -0500677static int gic_register_ipi_domain(struct device_node *node)
678{
679 struct irq_domain *gic_ipi_domain;
680 unsigned int v[2], num_ipis;
681
682 gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
683 IRQ_DOMAIN_FLAG_IPI_PER_CPU,
684 GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
685 node, &gic_ipi_domain_ops, NULL);
686 if (!gic_ipi_domain) {
687 pr_err("Failed to add IPI domain");
688 return -ENXIO;
689 }
690
691 irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
692
693 if (node &&
694 !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
695 bitmap_set(ipi_resrv, v[0], v[1]);
696 } else {
697 /*
698 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
699 * meeting the requirements of arch/mips SMP.
700 */
701 num_ipis = 2 * num_possible_cpus();
702 bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
703 }
704
705 bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
706
707 return 0;
708}
709
710#else /* !CONFIG_GENERIC_IRQ_IPI */
711
712static inline int gic_register_ipi_domain(struct device_node *node)
713{
714 return 0;
715}
716
717#endif /* !CONFIG_GENERIC_IRQ_IPI */
718
Paul Burtonda61fcf2017-10-31 09:41:45 -0700719static int gic_cpu_startup(unsigned int cpu)
720{
Paul Burton890f6b52017-10-31 09:41:47 -0700721 /* Enable or disable EIC */
722 change_gic_vl_ctl(GIC_VX_CTL_EIC,
723 cpu_has_veic ? GIC_VX_CTL_EIC : 0);
724
Paul Burton25ac19e2017-10-31 09:41:46 -0700725 /* Clear all local IRQ masks (ie. disable all local interrupts) */
726 write_gic_vl_rmask(~0);
727
Marc Zyngierdd098a02021-10-21 18:04:13 +0100728 /* Enable desired interrupts */
729 gic_all_vpes_irq_cpu_online();
Paul Burtonda61fcf2017-10-31 09:41:45 -0700730
731 return 0;
732}
Ralf Baechle39b8d522008-04-28 17:14:26 +0100733
Paul Burtonfbea7542017-08-12 21:36:40 -0700734static int __init gic_of_init(struct device_node *node,
735 struct device_node *parent)
Ralf Baechle39b8d522008-04-28 17:14:26 +0100736{
Samuel Holland8190cc52022-07-01 15:00:49 -0500737 unsigned int cpu_vec, i, gicconfig;
Paul Burtonb2b2e582017-08-12 21:36:44 -0700738 unsigned long reserved;
Paul Burtonfbea7542017-08-12 21:36:40 -0700739 phys_addr_t gic_base;
740 struct resource res;
741 size_t gic_len;
Samuel Holland8190cc52022-07-01 15:00:49 -0500742 int ret;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100743
Paul Burtonfbea7542017-08-12 21:36:40 -0700744 /* Find the first available CPU vector. */
Paul Burtonb2b2e582017-08-12 21:36:44 -0700745 i = 0;
Paul Burtona08588e2017-09-21 23:24:39 -0700746 reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
Paul Burtonfbea7542017-08-12 21:36:40 -0700747 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
748 i++, &cpu_vec))
749 reserved |= BIT(cpu_vec);
Alex Smithc0a9f722015-10-12 10:40:43 +0100750
Paul Burtonb2b2e582017-08-12 21:36:44 -0700751 cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
752 if (cpu_vec == hweight_long(ST0_IM)) {
Matt Redfearn1f19aee2017-11-09 11:02:44 +0000753 pr_err("No CPU vectors available\n");
Paul Burtonfbea7542017-08-12 21:36:40 -0700754 return -ENODEV;
755 }
Ralf Baechle39b8d522008-04-28 17:14:26 +0100756
Paul Burtonfbea7542017-08-12 21:36:40 -0700757 if (of_address_to_resource(node, 0, &res)) {
758 /*
759 * Probe the CM for the GIC base address if not specified
760 * in the device-tree.
761 */
762 if (mips_cm_present()) {
763 gic_base = read_gcr_gic_base() &
764 ~CM_GCR_GIC_BASE_GICEN;
765 gic_len = 0x20000;
Matt Redfearn666740f2017-11-09 11:02:45 +0000766 pr_warn("Using inherited base address %pa\n",
767 &gic_base);
Paul Burtonfbea7542017-08-12 21:36:40 -0700768 } else {
Matt Redfearn1f19aee2017-11-09 11:02:44 +0000769 pr_err("Failed to get memory range\n");
Paul Burtonfbea7542017-08-12 21:36:40 -0700770 return -ENODEV;
771 }
772 } else {
773 gic_base = res.start;
774 gic_len = resource_size(&res);
775 }
Ralf Baechle39b8d522008-04-28 17:14:26 +0100776
Paul Burtonfbea7542017-08-12 21:36:40 -0700777 if (mips_cm_present()) {
778 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
779 /* Ensure GIC region is enabled before trying to access it */
780 __sync();
781 }
782
Christoph Hellwig4bdc0d62020-01-06 09:43:50 +0100783 mips_gic_base = ioremap(gic_base, gic_len);
William Dean71349cc2022-07-23 18:01:28 +0800784 if (!mips_gic_base) {
785 pr_err("Failed to ioremap gic_base\n");
786 return -ENOMEM;
787 }
Ralf Baechle39b8d522008-04-28 17:14:26 +0100788
Paul Burton36807462017-08-12 21:36:24 -0700789 gicconfig = read_gic_config();
Geert Uytterhoeven357a9c42021-11-22 16:54:07 +0100790 gic_shared_intrs = FIELD_GET(GIC_CONFIG_NUMINTERRUPTS, gicconfig);
Paul Burton36807462017-08-12 21:36:24 -0700791 gic_shared_intrs = (gic_shared_intrs + 1) * 8;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100792
Ralf Baechle39b8d522008-04-28 17:14:26 +0100793 if (cpu_has_veic) {
794 /* Always use vector 1 in EIC mode */
795 gic_cpu_pin = 0;
796 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
797 __gic_irq_dispatch);
798 } else {
799 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
800 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
801 gic_irq_dispatch);
802 }
803
Andrew Brestickera7057272014-11-12 11:43:38 -0800804 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
Paul Burtonfbea7542017-08-12 21:36:40 -0700805 gic_shared_intrs, 0,
Ralf Baechle39b8d522008-04-28 17:14:26 +0100806 &gic_irq_domain_ops, NULL);
Paul Burtonfbea7542017-08-12 21:36:40 -0700807 if (!gic_irq_domain) {
Matt Redfearn1f19aee2017-11-09 11:02:44 +0000808 pr_err("Failed to add IRQ domain");
Paul Burtonfbea7542017-08-12 21:36:40 -0700809 return -ENXIO;
810 }
Ralf Baechle39b8d522008-04-28 17:14:26 +0100811
Samuel Holland8190cc52022-07-01 15:00:49 -0500812 ret = gic_register_ipi_domain(node);
813 if (ret)
814 return ret;
Andrew Brestickera7057272014-11-12 11:43:38 -0800815
Paul Burton87888bc2017-08-12 21:36:41 -0700816 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
Andrew Brestickera7057272014-11-12 11:43:38 -0800817
Paul Burton87888bc2017-08-12 21:36:41 -0700818 /* Setup defaults */
819 for (i = 0; i < gic_shared_intrs; i++) {
820 change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
821 change_gic_trig(i, GIC_TRIG_LEVEL);
Paul Burton90019f82017-09-05 11:28:46 -0700822 write_gic_rmask(i);
Andrew Brestickera7057272014-11-12 11:43:38 -0800823 }
824
Paul Burtonda61fcf2017-10-31 09:41:45 -0700825 return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
826 "irqchip/mips/gic:starting",
827 gic_cpu_startup, NULL);
Andrew Brestickera7057272014-11-12 11:43:38 -0800828}
829IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);