Thomas Gleixner | 2874c5f | 2019-05-27 08:55:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 2 | /* |
| 3 | * FPU support code, moved here from head.S so that it can be used |
| 4 | * by chips which use other head-whatever.S files. |
| 5 | * |
Paul Mackerras | fea23bf | 2006-08-30 14:45:35 +1000 | [diff] [blame] | 6 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
| 7 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> |
| 8 | * Copyright (C) 1996 Paul Mackerras. |
| 9 | * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 10 | */ |
| 11 | |
Paul Mackerras | b3b8dc6 | 2005-10-10 22:20:10 +1000 | [diff] [blame] | 12 | #include <asm/reg.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 13 | #include <asm/page.h> |
| 14 | #include <asm/mmu.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 15 | #include <asm/cputable.h> |
| 16 | #include <asm/cache.h> |
| 17 | #include <asm/thread_info.h> |
| 18 | #include <asm/ppc_asm.h> |
| 19 | #include <asm/asm-offsets.h> |
Stephen Rothwell | 46f5221 | 2010-11-18 15:06:17 +0000 | [diff] [blame] | 20 | #include <asm/ptrace.h> |
Al Viro | 9445aa1 | 2016-01-13 23:33:46 -0500 | [diff] [blame] | 21 | #include <asm/export.h> |
Christophe Leroy | ec0c464 | 2018-07-05 16:24:57 +0000 | [diff] [blame] | 22 | #include <asm/asm-compat.h> |
Christophe Leroy | 2c86cd1 | 2018-07-05 16:25:01 +0000 | [diff] [blame] | 23 | #include <asm/feature-fixups.h> |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 24 | |
Michael Neuling | 72ffff5 | 2008-06-25 14:07:18 +1000 | [diff] [blame] | 25 | #ifdef CONFIG_VSX |
Michael Neuling | 0b7673c | 2012-06-25 13:33:23 +0000 | [diff] [blame] | 26 | #define __REST_32FPVSRS(n,c,base) \ |
Michael Neuling | 72ffff5 | 2008-06-25 14:07:18 +1000 | [diff] [blame] | 27 | BEGIN_FTR_SECTION \ |
| 28 | b 2f; \ |
| 29 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ |
| 30 | REST_32FPRS(n,base); \ |
| 31 | b 3f; \ |
| 32 | 2: REST_32VSRS(n,c,base); \ |
| 33 | 3: |
| 34 | |
Michael Neuling | 0b7673c | 2012-06-25 13:33:23 +0000 | [diff] [blame] | 35 | #define __SAVE_32FPVSRS(n,c,base) \ |
Michael Neuling | 72ffff5 | 2008-06-25 14:07:18 +1000 | [diff] [blame] | 36 | BEGIN_FTR_SECTION \ |
| 37 | b 2f; \ |
| 38 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ |
| 39 | SAVE_32FPRS(n,base); \ |
| 40 | b 3f; \ |
| 41 | 2: SAVE_32VSRS(n,c,base); \ |
| 42 | 3: |
| 43 | #else |
Michael Neuling | 0b7673c | 2012-06-25 13:33:23 +0000 | [diff] [blame] | 44 | #define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) |
| 45 | #define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) |
Michael Neuling | 72ffff5 | 2008-06-25 14:07:18 +1000 | [diff] [blame] | 46 | #endif |
Michael Neuling | 0b7673c | 2012-06-25 13:33:23 +0000 | [diff] [blame] | 47 | #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) |
| 48 | #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) |
Michael Neuling | 72ffff5 | 2008-06-25 14:07:18 +1000 | [diff] [blame] | 49 | |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 50 | /* |
Paul Mackerras | 1846196 | 2013-09-10 20:21:10 +1000 | [diff] [blame] | 51 | * Load state from memory into FP registers including FPSCR. |
| 52 | * Assumes the caller has enabled FP in the MSR. |
| 53 | */ |
| 54 | _GLOBAL(load_fp_state) |
| 55 | lfd fr0,FPSTATE_FPSCR(r3) |
| 56 | MTFSF_L(fr0) |
| 57 | REST_32FPVSRS(0, R4, R3) |
| 58 | blr |
Al Viro | 9445aa1 | 2016-01-13 23:33:46 -0500 | [diff] [blame] | 59 | EXPORT_SYMBOL(load_fp_state) |
Nicholas Piggin | e2b36d5 | 2019-05-02 15:21:07 +1000 | [diff] [blame] | 60 | _ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */ |
Paul Mackerras | 1846196 | 2013-09-10 20:21:10 +1000 | [diff] [blame] | 61 | |
| 62 | /* |
| 63 | * Store FP state into memory, including FPSCR |
| 64 | * Assumes the caller has enabled FP in the MSR. |
| 65 | */ |
| 66 | _GLOBAL(store_fp_state) |
| 67 | SAVE_32FPVSRS(0, R4, R3) |
| 68 | mffs fr0 |
| 69 | stfd fr0,FPSTATE_FPSCR(r3) |
| 70 | blr |
Al Viro | 9445aa1 | 2016-01-13 23:33:46 -0500 | [diff] [blame] | 71 | EXPORT_SYMBOL(store_fp_state) |
Paul Mackerras | 1846196 | 2013-09-10 20:21:10 +1000 | [diff] [blame] | 72 | |
| 73 | /* |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 74 | * This task wants to use the FPU now. |
| 75 | * On UP, disable FP for the task which had the FPU previously, |
| 76 | * and save its floating-point registers in its thread_struct. |
| 77 | * Load up this task's FP registers from its thread_struct, |
| 78 | * enable the FPU for the current task and return to the task. |
Paul Mackerras | 955c1ca | 2013-10-23 09:40:02 +0100 | [diff] [blame] | 79 | * Note that on 32-bit this can only use registers that will be |
| 80 | * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 81 | */ |
Paul Mackerras | b85a046 | 2005-10-06 10:59:19 +1000 | [diff] [blame] | 82 | _GLOBAL(load_up_fpu) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 83 | mfmsr r5 |
| 84 | ori r5,r5,MSR_FP |
Michael Neuling | ce48b21 | 2008-06-25 14:07:18 +1000 | [diff] [blame] | 85 | #ifdef CONFIG_VSX |
| 86 | BEGIN_FTR_SECTION |
| 87 | oris r5,r5,MSR_VSX@h |
| 88 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) |
| 89 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 90 | SYNC |
| 91 | MTMSRD(r5) /* enable use of fpu now */ |
| 92 | isync |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 93 | /* enable use of FP after return */ |
Paul Mackerras | b85a046 | 2005-10-06 10:59:19 +1000 | [diff] [blame] | 94 | #ifdef CONFIG_PPC32 |
Paul Mackerras | de79f7b | 2013-09-10 20:20:42 +1000 | [diff] [blame] | 95 | mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ |
Christophe Leroy | cd08f10 | 2019-12-21 08:32:38 +0000 | [diff] [blame] | 96 | #ifdef CONFIG_VMAP_STACK |
| 97 | tovirt(r5, r5) |
| 98 | #endif |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 99 | lwz r4,THREAD_FPEXC_MODE(r5) |
| 100 | ori r9,r9,MSR_FP /* enable FP for current */ |
| 101 | or r9,r9,r4 |
Paul Mackerras | b85a046 | 2005-10-06 10:59:19 +1000 | [diff] [blame] | 102 | #else |
| 103 | ld r4,PACACURRENT(r13) |
| 104 | addi r5,r4,THREAD /* Get THREAD */ |
Paul Mackerras | e2f5a3c | 2006-02-07 13:55:30 +1100 | [diff] [blame] | 105 | lwz r4,THREAD_FPEXC_MODE(r5) |
Paul Mackerras | b85a046 | 2005-10-06 10:59:19 +1000 | [diff] [blame] | 106 | ori r12,r12,MSR_FP |
| 107 | or r12,r12,r4 |
| 108 | std r12,_MSR(r1) |
| 109 | #endif |
Nicholas Piggin | b2b4630 | 2020-06-24 09:41:39 +1000 | [diff] [blame] | 110 | li r4,1 |
Cyril Bur | 70fe3d9 | 2016-02-29 17:53:47 +1100 | [diff] [blame] | 111 | stb r4,THREAD_LOAD_FP(r5) |
Paul Mackerras | 955c1ca | 2013-10-23 09:40:02 +0100 | [diff] [blame] | 112 | addi r10,r5,THREAD_FPSTATE |
| 113 | lfd fr0,FPSTATE_FPSCR(r10) |
Anton Blanchard | 3a2c48c | 2006-06-10 20:18:39 +1000 | [diff] [blame] | 114 | MTFSF_L(fr0) |
Paul Mackerras | 955c1ca | 2013-10-23 09:40:02 +0100 | [diff] [blame] | 115 | REST_32FPVSRS(0, R4, R10) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 116 | /* restore registers and return */ |
| 117 | /* we haven't used ctr or xer or lr */ |
Michael Neuling | 6f3d8e6 | 2008-06-25 14:07:18 +1000 | [diff] [blame] | 118 | blr |
Christophe Leroy | 5f32e83 | 2020-03-31 16:03:44 +0000 | [diff] [blame] | 119 | _ASM_NOKPROBE_SYMBOL(load_up_fpu) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 120 | |
| 121 | /* |
Cyril Bur | 8792468 | 2016-02-29 17:53:49 +1100 | [diff] [blame] | 122 | * save_fpu(tsk) |
| 123 | * Save the floating-point registers in its thread_struct. |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 124 | * Enables the FPU for use in the kernel on return. |
| 125 | */ |
Cyril Bur | 8792468 | 2016-02-29 17:53:49 +1100 | [diff] [blame] | 126 | _GLOBAL(save_fpu) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 127 | addi r3,r3,THREAD /* want THREAD of task */ |
Paul Mackerras | 1846196 | 2013-09-10 20:21:10 +1000 | [diff] [blame] | 128 | PPC_LL r6,THREAD_FPSAVEAREA(r3) |
David Gibson | 3ddfbcf | 2005-11-10 12:56:55 +1100 | [diff] [blame] | 129 | PPC_LL r5,PT_REGS(r3) |
Paul Mackerras | 1846196 | 2013-09-10 20:21:10 +1000 | [diff] [blame] | 130 | PPC_LCMPI 0,r6,0 |
| 131 | bne 2f |
Paul Mackerras | de79f7b | 2013-09-10 20:20:42 +1000 | [diff] [blame] | 132 | addi r6,r3,THREAD_FPSTATE |
Cyril Bur | 8792468 | 2016-02-29 17:53:49 +1100 | [diff] [blame] | 133 | 2: SAVE_32FPVSRS(0, R4, R6) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 134 | mffs fr0 |
Paul Mackerras | de79f7b | 2013-09-10 20:20:42 +1000 | [diff] [blame] | 135 | stfd fr0,FPSTATE_FPSCR(r6) |
Paul Mackerras | 14cf11a | 2005-09-26 16:04:21 +1000 | [diff] [blame] | 136 | blr |
David Gibson | 25c8a78 | 2005-10-27 16:27:25 +1000 | [diff] [blame] | 137 | |
| 138 | /* |
| 139 | * These are used in the alignment trap handler when emulating |
| 140 | * single-precision loads and stores. |
David Gibson | 25c8a78 | 2005-10-27 16:27:25 +1000 | [diff] [blame] | 141 | */ |
| 142 | |
| 143 | _GLOBAL(cvt_fd) |
David Gibson | 25c8a78 | 2005-10-27 16:27:25 +1000 | [diff] [blame] | 144 | lfs 0,0(r3) |
| 145 | stfd 0,0(r4) |
David Gibson | 25c8a78 | 2005-10-27 16:27:25 +1000 | [diff] [blame] | 146 | blr |
| 147 | |
| 148 | _GLOBAL(cvt_df) |
David Gibson | 25c8a78 | 2005-10-27 16:27:25 +1000 | [diff] [blame] | 149 | lfd 0,0(r3) |
| 150 | stfs 0,0(r4) |
David Gibson | 25c8a78 | 2005-10-27 16:27:25 +1000 | [diff] [blame] | 151 | blr |