Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
Lina Iyer | b2bb01ed | 2019-11-15 15:11:45 -0700 | [diff] [blame] | 3 | * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <linux/err.h> |
| 7 | #include <linux/init.h> |
Maulik Shah | e71374c | 2019-11-15 15:11:50 -0700 | [diff] [blame] | 8 | #include <linux/interrupt.h> |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 9 | #include <linux/irq.h> |
| 10 | #include <linux/irqchip.h> |
| 11 | #include <linux/irqdomain.h> |
| 12 | #include <linux/io.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/of.h> |
| 15 | #include <linux/of_address.h> |
| 16 | #include <linux/of_device.h> |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 17 | #include <linux/soc/qcom/irq.h> |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 18 | #include <linux/spinlock.h> |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 19 | #include <linux/slab.h> |
| 20 | #include <linux/types.h> |
| 21 | |
Lina Iyer | b2bb01ed | 2019-11-15 15:11:45 -0700 | [diff] [blame] | 22 | #define PDC_MAX_IRQS 168 |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 23 | #define PDC_MAX_GPIO_IRQS 256 |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 24 | |
| 25 | #define CLEAR_INTR(reg, intr) (reg & ~(1 << intr)) |
| 26 | #define ENABLE_INTR(reg, intr) (reg | (1 << intr)) |
| 27 | |
| 28 | #define IRQ_ENABLE_BANK 0x10 |
| 29 | #define IRQ_i_CFG 0x110 |
| 30 | |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 31 | #define PDC_NO_PARENT_IRQ ~0UL |
| 32 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 33 | struct pdc_pin_region { |
| 34 | u32 pin_base; |
| 35 | u32 parent_base; |
| 36 | u32 cnt; |
| 37 | }; |
| 38 | |
| 39 | static DEFINE_RAW_SPINLOCK(pdc_lock); |
| 40 | static void __iomem *pdc_base; |
| 41 | static struct pdc_pin_region *pdc_region; |
| 42 | static int pdc_region_cnt; |
| 43 | |
| 44 | static void pdc_reg_write(int reg, u32 i, u32 val) |
| 45 | { |
| 46 | writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); |
| 47 | } |
| 48 | |
| 49 | static u32 pdc_reg_read(int reg, u32 i) |
| 50 | { |
| 51 | return readl_relaxed(pdc_base + reg + i * sizeof(u32)); |
| 52 | } |
| 53 | |
Maulik Shah | e71374c | 2019-11-15 15:11:50 -0700 | [diff] [blame] | 54 | static int qcom_pdc_gic_get_irqchip_state(struct irq_data *d, |
| 55 | enum irqchip_irq_state which, |
| 56 | bool *state) |
| 57 | { |
| 58 | if (d->hwirq == GPIO_NO_WAKE_IRQ) |
| 59 | return 0; |
| 60 | |
| 61 | return irq_chip_get_parent_state(d, which, state); |
| 62 | } |
| 63 | |
| 64 | static int qcom_pdc_gic_set_irqchip_state(struct irq_data *d, |
| 65 | enum irqchip_irq_state which, |
| 66 | bool value) |
| 67 | { |
| 68 | if (d->hwirq == GPIO_NO_WAKE_IRQ) |
| 69 | return 0; |
| 70 | |
| 71 | return irq_chip_set_parent_state(d, which, value); |
| 72 | } |
| 73 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 74 | static void pdc_enable_intr(struct irq_data *d, bool on) |
| 75 | { |
| 76 | int pin_out = d->hwirq; |
| 77 | u32 index, mask; |
| 78 | u32 enable; |
| 79 | |
| 80 | index = pin_out / 32; |
| 81 | mask = pin_out % 32; |
| 82 | |
| 83 | raw_spin_lock(&pdc_lock); |
| 84 | enable = pdc_reg_read(IRQ_ENABLE_BANK, index); |
| 85 | enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask); |
| 86 | pdc_reg_write(IRQ_ENABLE_BANK, index, enable); |
| 87 | raw_spin_unlock(&pdc_lock); |
| 88 | } |
| 89 | |
Lina Iyer | da3f875 | 2019-11-15 15:11:46 -0700 | [diff] [blame] | 90 | static void qcom_pdc_gic_disable(struct irq_data *d) |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 91 | { |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 92 | if (d->hwirq == GPIO_NO_WAKE_IRQ) |
| 93 | return; |
| 94 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 95 | pdc_enable_intr(d, false); |
Lina Iyer | da3f875 | 2019-11-15 15:11:46 -0700 | [diff] [blame] | 96 | irq_chip_disable_parent(d); |
| 97 | } |
| 98 | |
| 99 | static void qcom_pdc_gic_enable(struct irq_data *d) |
| 100 | { |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 101 | if (d->hwirq == GPIO_NO_WAKE_IRQ) |
| 102 | return; |
| 103 | |
Lina Iyer | da3f875 | 2019-11-15 15:11:46 -0700 | [diff] [blame] | 104 | pdc_enable_intr(d, true); |
| 105 | irq_chip_enable_parent(d); |
| 106 | } |
| 107 | |
| 108 | static void qcom_pdc_gic_mask(struct irq_data *d) |
| 109 | { |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 110 | if (d->hwirq == GPIO_NO_WAKE_IRQ) |
| 111 | return; |
| 112 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 113 | irq_chip_mask_parent(d); |
| 114 | } |
| 115 | |
| 116 | static void qcom_pdc_gic_unmask(struct irq_data *d) |
| 117 | { |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 118 | if (d->hwirq == GPIO_NO_WAKE_IRQ) |
| 119 | return; |
| 120 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 121 | irq_chip_unmask_parent(d); |
| 122 | } |
| 123 | |
| 124 | /* |
| 125 | * GIC does not handle falling edge or active low. To allow falling edge and |
| 126 | * active low interrupts to be handled at GIC, PDC has an inverter that inverts |
| 127 | * falling edge into a rising edge and active low into an active high. |
| 128 | * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to |
| 129 | * set as per the table below. |
| 130 | * Level sensitive active low LOW |
| 131 | * Rising edge sensitive NOT USED |
| 132 | * Falling edge sensitive LOW |
| 133 | * Dual Edge sensitive NOT USED |
| 134 | * Level sensitive active High HIGH |
| 135 | * Falling Edge sensitive NOT USED |
| 136 | * Rising edge sensitive HIGH |
| 137 | * Dual Edge sensitive HIGH |
| 138 | */ |
| 139 | enum pdc_irq_config_bits { |
| 140 | PDC_LEVEL_LOW = 0b000, |
| 141 | PDC_EDGE_FALLING = 0b010, |
| 142 | PDC_LEVEL_HIGH = 0b100, |
| 143 | PDC_EDGE_RISING = 0b110, |
| 144 | PDC_EDGE_DUAL = 0b111, |
| 145 | }; |
| 146 | |
| 147 | /** |
| 148 | * qcom_pdc_gic_set_type: Configure PDC for the interrupt |
| 149 | * |
| 150 | * @d: the interrupt data |
| 151 | * @type: the interrupt type |
| 152 | * |
| 153 | * If @type is edge triggered, forward that as Rising edge as PDC |
| 154 | * takes care of converting falling edge to rising edge signal |
| 155 | * If @type is level, then forward that as level high as PDC |
| 156 | * takes care of converting falling edge to rising edge signal |
| 157 | */ |
| 158 | static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) |
| 159 | { |
| 160 | int pin_out = d->hwirq; |
| 161 | enum pdc_irq_config_bits pdc_type; |
| 162 | |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 163 | if (pin_out == GPIO_NO_WAKE_IRQ) |
| 164 | return 0; |
| 165 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 166 | switch (type) { |
| 167 | case IRQ_TYPE_EDGE_RISING: |
| 168 | pdc_type = PDC_EDGE_RISING; |
| 169 | break; |
| 170 | case IRQ_TYPE_EDGE_FALLING: |
| 171 | pdc_type = PDC_EDGE_FALLING; |
| 172 | type = IRQ_TYPE_EDGE_RISING; |
| 173 | break; |
| 174 | case IRQ_TYPE_EDGE_BOTH: |
| 175 | pdc_type = PDC_EDGE_DUAL; |
Lina Iyer | 7bae48b | 2018-09-27 11:18:10 -0600 | [diff] [blame] | 176 | type = IRQ_TYPE_EDGE_RISING; |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 177 | break; |
| 178 | case IRQ_TYPE_LEVEL_HIGH: |
| 179 | pdc_type = PDC_LEVEL_HIGH; |
| 180 | break; |
| 181 | case IRQ_TYPE_LEVEL_LOW: |
| 182 | pdc_type = PDC_LEVEL_LOW; |
| 183 | type = IRQ_TYPE_LEVEL_HIGH; |
| 184 | break; |
| 185 | default: |
| 186 | WARN_ON(1); |
| 187 | return -EINVAL; |
| 188 | } |
| 189 | |
| 190 | pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type); |
| 191 | |
| 192 | return irq_chip_set_type_parent(d, type); |
| 193 | } |
| 194 | |
| 195 | static struct irq_chip qcom_pdc_gic_chip = { |
| 196 | .name = "PDC", |
| 197 | .irq_eoi = irq_chip_eoi_parent, |
| 198 | .irq_mask = qcom_pdc_gic_mask, |
| 199 | .irq_unmask = qcom_pdc_gic_unmask, |
Lina Iyer | da3f875 | 2019-11-15 15:11:46 -0700 | [diff] [blame] | 200 | .irq_disable = qcom_pdc_gic_disable, |
| 201 | .irq_enable = qcom_pdc_gic_enable, |
Maulik Shah | e71374c | 2019-11-15 15:11:50 -0700 | [diff] [blame] | 202 | .irq_get_irqchip_state = qcom_pdc_gic_get_irqchip_state, |
| 203 | .irq_set_irqchip_state = qcom_pdc_gic_set_irqchip_state, |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 204 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
| 205 | .irq_set_type = qcom_pdc_gic_set_type, |
| 206 | .flags = IRQCHIP_MASK_ON_SUSPEND | |
| 207 | IRQCHIP_SET_TYPE_MASKED | |
| 208 | IRQCHIP_SKIP_SET_WAKE, |
| 209 | .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, |
| 210 | .irq_set_affinity = irq_chip_set_affinity_parent, |
| 211 | }; |
| 212 | |
| 213 | static irq_hw_number_t get_parent_hwirq(int pin) |
| 214 | { |
| 215 | int i; |
| 216 | struct pdc_pin_region *region; |
| 217 | |
| 218 | for (i = 0; i < pdc_region_cnt; i++) { |
| 219 | region = &pdc_region[i]; |
| 220 | if (pin >= region->pin_base && |
| 221 | pin < region->pin_base + region->cnt) |
| 222 | return (region->parent_base + pin - region->pin_base); |
| 223 | } |
| 224 | |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 225 | return PDC_NO_PARENT_IRQ; |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fwspec, |
| 229 | unsigned long *hwirq, unsigned int *type) |
| 230 | { |
| 231 | if (is_of_node(fwspec->fwnode)) { |
| 232 | if (fwspec->param_count != 2) |
| 233 | return -EINVAL; |
| 234 | |
| 235 | *hwirq = fwspec->param[0]; |
| 236 | *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; |
| 237 | return 0; |
| 238 | } |
| 239 | |
| 240 | return -EINVAL; |
| 241 | } |
| 242 | |
| 243 | static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, |
| 244 | unsigned int nr_irqs, void *data) |
| 245 | { |
| 246 | struct irq_fwspec *fwspec = data; |
| 247 | struct irq_fwspec parent_fwspec; |
| 248 | irq_hw_number_t hwirq, parent_hwirq; |
| 249 | unsigned int type; |
| 250 | int ret; |
| 251 | |
| 252 | ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); |
| 253 | if (ret) |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 254 | return ret; |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 255 | |
| 256 | ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, |
| 257 | &qcom_pdc_gic_chip, NULL); |
| 258 | if (ret) |
| 259 | return ret; |
| 260 | |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 261 | parent_hwirq = get_parent_hwirq(hwirq); |
| 262 | if (parent_hwirq == PDC_NO_PARENT_IRQ) |
| 263 | return 0; |
| 264 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 265 | if (type & IRQ_TYPE_EDGE_BOTH) |
| 266 | type = IRQ_TYPE_EDGE_RISING; |
| 267 | |
| 268 | if (type & IRQ_TYPE_LEVEL_MASK) |
| 269 | type = IRQ_TYPE_LEVEL_HIGH; |
| 270 | |
| 271 | parent_fwspec.fwnode = domain->parent->fwnode; |
| 272 | parent_fwspec.param_count = 3; |
| 273 | parent_fwspec.param[0] = 0; |
| 274 | parent_fwspec.param[1] = parent_hwirq; |
| 275 | parent_fwspec.param[2] = type; |
| 276 | |
| 277 | return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, |
| 278 | &parent_fwspec); |
| 279 | } |
| 280 | |
| 281 | static const struct irq_domain_ops qcom_pdc_ops = { |
| 282 | .translate = qcom_pdc_translate, |
| 283 | .alloc = qcom_pdc_alloc, |
| 284 | .free = irq_domain_free_irqs_common, |
| 285 | }; |
| 286 | |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 287 | static int qcom_pdc_gpio_alloc(struct irq_domain *domain, unsigned int virq, |
| 288 | unsigned int nr_irqs, void *data) |
| 289 | { |
| 290 | struct irq_fwspec *fwspec = data; |
| 291 | struct irq_fwspec parent_fwspec; |
| 292 | irq_hw_number_t hwirq, parent_hwirq; |
| 293 | unsigned int type; |
| 294 | int ret; |
| 295 | |
| 296 | ret = qcom_pdc_translate(domain, fwspec, &hwirq, &type); |
| 297 | if (ret) |
| 298 | return ret; |
| 299 | |
| 300 | ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, |
| 301 | &qcom_pdc_gic_chip, NULL); |
| 302 | if (ret) |
| 303 | return ret; |
| 304 | |
| 305 | if (hwirq == GPIO_NO_WAKE_IRQ) |
| 306 | return 0; |
| 307 | |
| 308 | parent_hwirq = get_parent_hwirq(hwirq); |
| 309 | if (parent_hwirq == PDC_NO_PARENT_IRQ) |
| 310 | return 0; |
| 311 | |
| 312 | if (type & IRQ_TYPE_EDGE_BOTH) |
| 313 | type = IRQ_TYPE_EDGE_RISING; |
| 314 | |
| 315 | if (type & IRQ_TYPE_LEVEL_MASK) |
| 316 | type = IRQ_TYPE_LEVEL_HIGH; |
| 317 | |
| 318 | parent_fwspec.fwnode = domain->parent->fwnode; |
| 319 | parent_fwspec.param_count = 3; |
| 320 | parent_fwspec.param[0] = 0; |
| 321 | parent_fwspec.param[1] = parent_hwirq; |
| 322 | parent_fwspec.param[2] = type; |
| 323 | |
| 324 | return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, |
| 325 | &parent_fwspec); |
| 326 | } |
| 327 | |
| 328 | static int qcom_pdc_gpio_domain_select(struct irq_domain *d, |
| 329 | struct irq_fwspec *fwspec, |
| 330 | enum irq_domain_bus_token bus_token) |
| 331 | { |
| 332 | return bus_token == DOMAIN_BUS_WAKEUP; |
| 333 | } |
| 334 | |
| 335 | static const struct irq_domain_ops qcom_pdc_gpio_ops = { |
| 336 | .select = qcom_pdc_gpio_domain_select, |
| 337 | .alloc = qcom_pdc_gpio_alloc, |
| 338 | .free = irq_domain_free_irqs_common, |
| 339 | }; |
| 340 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 341 | static int pdc_setup_pin_mapping(struct device_node *np) |
| 342 | { |
| 343 | int ret, n; |
| 344 | |
| 345 | n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); |
| 346 | if (n <= 0 || n % 3) |
| 347 | return -EINVAL; |
| 348 | |
| 349 | pdc_region_cnt = n / 3; |
| 350 | pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL); |
| 351 | if (!pdc_region) { |
| 352 | pdc_region_cnt = 0; |
| 353 | return -ENOMEM; |
| 354 | } |
| 355 | |
| 356 | for (n = 0; n < pdc_region_cnt; n++) { |
| 357 | ret = of_property_read_u32_index(np, "qcom,pdc-ranges", |
| 358 | n * 3 + 0, |
| 359 | &pdc_region[n].pin_base); |
| 360 | if (ret) |
| 361 | return ret; |
| 362 | ret = of_property_read_u32_index(np, "qcom,pdc-ranges", |
| 363 | n * 3 + 1, |
| 364 | &pdc_region[n].parent_base); |
| 365 | if (ret) |
| 366 | return ret; |
| 367 | ret = of_property_read_u32_index(np, "qcom,pdc-ranges", |
| 368 | n * 3 + 2, |
| 369 | &pdc_region[n].cnt); |
| 370 | if (ret) |
| 371 | return ret; |
| 372 | } |
| 373 | |
| 374 | return 0; |
| 375 | } |
| 376 | |
| 377 | static int qcom_pdc_init(struct device_node *node, struct device_node *parent) |
| 378 | { |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 379 | struct irq_domain *parent_domain, *pdc_domain, *pdc_gpio_domain; |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 380 | int ret; |
| 381 | |
| 382 | pdc_base = of_iomap(node, 0); |
| 383 | if (!pdc_base) { |
| 384 | pr_err("%pOF: unable to map PDC registers\n", node); |
| 385 | return -ENXIO; |
| 386 | } |
| 387 | |
| 388 | parent_domain = irq_find_host(parent); |
| 389 | if (!parent_domain) { |
| 390 | pr_err("%pOF: unable to find PDC's parent domain\n", node); |
| 391 | ret = -ENXIO; |
| 392 | goto fail; |
| 393 | } |
| 394 | |
| 395 | ret = pdc_setup_pin_mapping(node); |
| 396 | if (ret) { |
| 397 | pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); |
| 398 | goto fail; |
| 399 | } |
| 400 | |
| 401 | pdc_domain = irq_domain_create_hierarchy(parent_domain, 0, PDC_MAX_IRQS, |
| 402 | of_fwnode_handle(node), |
| 403 | &qcom_pdc_ops, NULL); |
| 404 | if (!pdc_domain) { |
| 405 | pr_err("%pOF: GIC domain add failed\n", node); |
| 406 | ret = -ENOMEM; |
| 407 | goto fail; |
| 408 | } |
| 409 | |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 410 | pdc_gpio_domain = irq_domain_create_hierarchy(parent_domain, |
| 411 | IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, |
| 412 | PDC_MAX_GPIO_IRQS, |
| 413 | of_fwnode_handle(node), |
| 414 | &qcom_pdc_gpio_ops, NULL); |
| 415 | if (!pdc_gpio_domain) { |
| 416 | pr_err("%pOF: PDC domain add failed for GPIO domain\n", node); |
| 417 | ret = -ENOMEM; |
| 418 | goto remove; |
| 419 | } |
| 420 | |
| 421 | irq_domain_update_bus_token(pdc_gpio_domain, DOMAIN_BUS_WAKEUP); |
| 422 | |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 423 | return 0; |
| 424 | |
Lina Iyer | 81ef8bf | 2019-11-15 15:11:47 -0700 | [diff] [blame] | 425 | remove: |
| 426 | irq_domain_remove(pdc_domain); |
Archana Sathyakumar | f55c73a | 2018-02-28 10:27:29 -0700 | [diff] [blame] | 427 | fail: |
| 428 | kfree(pdc_region); |
| 429 | iounmap(pdc_base); |
| 430 | return ret; |
| 431 | } |
| 432 | |
Rajendra Nayak | 8e4d5a5 | 2019-11-08 14:58:17 +0530 | [diff] [blame] | 433 | IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init); |