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Andrew Victorb2c65612007-02-08 09:42:40 +01001/*
2 * arch/arm/mach-at91/at91sam9263.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
Boris BREZILLON2edb90a2013-10-11 09:37:45 +020014#include <linux/clk/at91_pmc.h>
Andrew Victorb2c65612007-02-08 09:42:40 +010015
Nicolas Pitrec9dfafb2011-08-02 10:21:36 -040016#include <asm/proc-fns.h>
Russell King80b02c12009-01-08 10:01:47 +000017#include <asm/irq.h>
Andrew Victorb2c65612007-02-08 09:42:40 +010018#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
David Howells9f97da72012-03-28 18:30:01 +010020#include <asm/system_misc.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010021#include <mach/at91sam9263.h>
Uwe Kleine-Königac11a1d2013-11-14 10:49:19 +010022#include <mach/hardware.h>
Andrew Victorb2c65612007-02-08 09:42:40 +010023
Jean-Christophe PLAGNIOL-VILLARDa510b9b2012-10-30 06:41:28 +080024#include "at91_aic.h"
Jean-Christophe PLAGNIOL-VILLARDf0995d02012-10-30 08:11:24 +080025#include "at91_rstc.h"
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +080026#include "soc.h"
Andrew Victorb2c65612007-02-08 09:42:40 +010027#include "generic.h"
Jean-Christophe PLAGNIOL-VILLARDfaee0cc2011-10-14 01:37:09 +080028#include "sam9_smc.h"
Daniel Lezcano5ad945e2013-09-22 22:29:57 +020029#include "pm.h"
Andrew Victorb2c65612007-02-08 09:42:40 +010030
Alexandre Bellonib81ccb32014-04-10 20:19:05 +020031#if defined(CONFIG_OLD_CLK_AT91)
32#include "clock.h"
Andrew Victorb2c65612007-02-08 09:42:40 +010033/* --------------------------------------------------------------------
34 * Clocks
35 * -------------------------------------------------------------------- */
36
37/*
38 * The peripheral clocks.
39 */
40static struct clk pioA_clk = {
41 .name = "pioA_clk",
42 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
43 .type = CLK_TYPE_PERIPHERAL,
44};
45static struct clk pioB_clk = {
46 .name = "pioB_clk",
47 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
48 .type = CLK_TYPE_PERIPHERAL,
49};
50static struct clk pioCDE_clk = {
51 .name = "pioCDE_clk",
52 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
53 .type = CLK_TYPE_PERIPHERAL,
54};
55static struct clk usart0_clk = {
56 .name = "usart0_clk",
57 .pmc_mask = 1 << AT91SAM9263_ID_US0,
58 .type = CLK_TYPE_PERIPHERAL,
59};
60static struct clk usart1_clk = {
61 .name = "usart1_clk",
62 .pmc_mask = 1 << AT91SAM9263_ID_US1,
63 .type = CLK_TYPE_PERIPHERAL,
64};
65static struct clk usart2_clk = {
66 .name = "usart2_clk",
67 .pmc_mask = 1 << AT91SAM9263_ID_US2,
68 .type = CLK_TYPE_PERIPHERAL,
69};
70static struct clk mmc0_clk = {
71 .name = "mci0_clk",
72 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
73 .type = CLK_TYPE_PERIPHERAL,
74};
75static struct clk mmc1_clk = {
76 .name = "mci1_clk",
77 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
78 .type = CLK_TYPE_PERIPHERAL,
79};
Andrew Victore8788ba2007-05-02 17:14:57 +010080static struct clk can_clk = {
81 .name = "can_clk",
82 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
83 .type = CLK_TYPE_PERIPHERAL,
84};
Andrew Victorb2c65612007-02-08 09:42:40 +010085static struct clk twi_clk = {
86 .name = "twi_clk",
87 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
88 .type = CLK_TYPE_PERIPHERAL,
89};
90static struct clk spi0_clk = {
91 .name = "spi0_clk",
92 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
93 .type = CLK_TYPE_PERIPHERAL,
94};
95static struct clk spi1_clk = {
96 .name = "spi1_clk",
97 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
98 .type = CLK_TYPE_PERIPHERAL,
99};
Andrew Victore8788ba2007-05-02 17:14:57 +0100100static struct clk ssc0_clk = {
101 .name = "ssc0_clk",
102 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
103 .type = CLK_TYPE_PERIPHERAL,
104};
105static struct clk ssc1_clk = {
106 .name = "ssc1_clk",
107 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
108 .type = CLK_TYPE_PERIPHERAL,
109};
110static struct clk ac97_clk = {
111 .name = "ac97_clk",
112 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
113 .type = CLK_TYPE_PERIPHERAL,
114};
Andrew Victorb2c65612007-02-08 09:42:40 +0100115static struct clk tcb_clk = {
116 .name = "tcb_clk",
117 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
118 .type = CLK_TYPE_PERIPHERAL,
119};
Andrew Victorbb1ad682008-09-18 19:42:37 +0100120static struct clk pwm_clk = {
121 .name = "pwm_clk",
Andrew Victore8788ba2007-05-02 17:14:57 +0100122 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
123 .type = CLK_TYPE_PERIPHERAL,
124};
Andrew Victor69b2e99c2007-02-14 08:44:43 +0100125static struct clk macb_clk = {
Jamie Iles865d6052011-08-09 16:51:11 +0200126 .name = "pclk",
Andrew Victorb2c65612007-02-08 09:42:40 +0100127 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
128 .type = CLK_TYPE_PERIPHERAL,
129};
Andrew Victore8788ba2007-05-02 17:14:57 +0100130static struct clk dma_clk = {
131 .name = "dma_clk",
132 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
133 .type = CLK_TYPE_PERIPHERAL,
134};
135static struct clk twodge_clk = {
136 .name = "2dge_clk",
137 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
138 .type = CLK_TYPE_PERIPHERAL,
139};
Andrew Victorb2c65612007-02-08 09:42:40 +0100140static struct clk udc_clk = {
141 .name = "udc_clk",
142 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
143 .type = CLK_TYPE_PERIPHERAL,
144};
145static struct clk isi_clk = {
146 .name = "isi_clk",
147 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
148 .type = CLK_TYPE_PERIPHERAL,
149};
150static struct clk lcdc_clk = {
151 .name = "lcdc_clk",
Andrew Victor7f6e2d92007-02-22 07:34:56 +0100152 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
Andrew Victorb2c65612007-02-08 09:42:40 +0100153 .type = CLK_TYPE_PERIPHERAL,
154};
155static struct clk ohci_clk = {
156 .name = "ohci_clk",
157 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
158 .type = CLK_TYPE_PERIPHERAL,
159};
160
161static struct clk *periph_clocks[] __initdata = {
162 &pioA_clk,
163 &pioB_clk,
164 &pioCDE_clk,
165 &usart0_clk,
166 &usart1_clk,
167 &usart2_clk,
168 &mmc0_clk,
169 &mmc1_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100170 &can_clk,
Andrew Victorb2c65612007-02-08 09:42:40 +0100171 &twi_clk,
172 &spi0_clk,
173 &spi1_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100174 &ssc0_clk,
175 &ssc1_clk,
176 &ac97_clk,
Andrew Victorb2c65612007-02-08 09:42:40 +0100177 &tcb_clk,
Andrew Victorbb1ad682008-09-18 19:42:37 +0100178 &pwm_clk,
Andrew Victor69b2e99c2007-02-14 08:44:43 +0100179 &macb_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100180 &twodge_clk,
Andrew Victorb2c65612007-02-08 09:42:40 +0100181 &udc_clk,
182 &isi_clk,
183 &lcdc_clk,
Andrew Victore8788ba2007-05-02 17:14:57 +0100184 &dma_clk,
Andrew Victorb2c65612007-02-08 09:42:40 +0100185 &ohci_clk,
186 // irq0 .. irq1
187};
188
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100189static struct clk_lookup periph_clocks_lookups[] = {
Jamie Iles865d6052011-08-09 16:51:11 +0200190 /* One additional fake clock for macb_hclk */
191 CLKDEV_CON_ID("hclk", &macb_clk),
Bo Shen636036d22012-11-06 13:57:51 +0800192 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
193 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
Bo Shen099343c2012-11-07 11:41:41 +0800194 CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
195 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
Johan Hovoldbbd44f6b2013-02-07 16:31:58 +0100196 CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
Ludovic Desroches4cf33262012-05-21 12:23:27 +0200197 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
198 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100199 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
200 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
201 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
Bo Shen302090a2012-10-15 17:30:28 +0800202 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
Alexandre Belloni3791f782014-05-29 01:20:06 +0200203 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
Jean-Christophe PLAGNIOL-VILLARD0af43162011-08-30 03:29:28 +0200204 /* fake hclk clock */
205 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
Jean-Christophe PLAGNIOL-VILLARD619d4a42011-11-13 13:00:58 +0800206 CLKDEV_CON_ID("pioA", &pioA_clk),
207 CLKDEV_CON_ID("pioB", &pioB_clk),
208 CLKDEV_CON_ID("pioC", &pioCDE_clk),
209 CLKDEV_CON_ID("pioD", &pioCDE_clk),
210 CLKDEV_CON_ID("pioE", &pioCDE_clk),
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800211 /* more usart lookup table for DT entries */
212 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
213 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
214 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
215 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
216 /* more tc lookup table for DT entries */
217 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
218 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
219 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
220 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
Ludovic Desroches23e3b242012-11-19 12:19:53 +0100221 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
222 CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
Ludovic Desrochesf7d19b92012-09-12 08:42:15 +0200223 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800224 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
226 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
227 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
228 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
Bo Shen050208d2013-12-19 11:59:16 +0800229 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100230};
231
232static struct clk_lookup usart_clocks_lookups[] = {
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
235 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
236 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
237};
238
Andrew Victorb2c65612007-02-08 09:42:40 +0100239/*
240 * The four programmable clocks.
241 * You must configure pin multiplexing to bring these signals out.
242 */
243static struct clk pck0 = {
244 .name = "pck0",
245 .pmc_mask = AT91_PMC_PCK0,
246 .type = CLK_TYPE_PROGRAMMABLE,
247 .id = 0,
248};
249static struct clk pck1 = {
250 .name = "pck1",
251 .pmc_mask = AT91_PMC_PCK1,
252 .type = CLK_TYPE_PROGRAMMABLE,
253 .id = 1,
254};
255static struct clk pck2 = {
256 .name = "pck2",
257 .pmc_mask = AT91_PMC_PCK2,
258 .type = CLK_TYPE_PROGRAMMABLE,
259 .id = 2,
260};
261static struct clk pck3 = {
262 .name = "pck3",
263 .pmc_mask = AT91_PMC_PCK3,
264 .type = CLK_TYPE_PROGRAMMABLE,
265 .id = 3,
266};
267
268static void __init at91sam9263_register_clocks(void)
269{
270 int i;
271
272 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
273 clk_register(periph_clocks[i]);
274
Jean-Christophe PLAGNIOL-VILLARDbd602992011-02-02 07:27:07 +0100275 clkdev_add_table(periph_clocks_lookups,
276 ARRAY_SIZE(periph_clocks_lookups));
277 clkdev_add_table(usart_clocks_lookups,
278 ARRAY_SIZE(usart_clocks_lookups));
279
Andrew Victorb2c65612007-02-08 09:42:40 +0100280 clk_register(&pck0);
281 clk_register(&pck1);
282 clk_register(&pck2);
283 clk_register(&pck3);
284}
Alexandre Bellonib81ccb32014-04-10 20:19:05 +0200285#else
286#define at91sam9263_register_clocks NULL
287#endif
Andrew Victorb2c65612007-02-08 09:42:40 +0100288
289/* --------------------------------------------------------------------
290 * GPIO
291 * -------------------------------------------------------------------- */
292
Jean-Christophe PLAGNIOL-VILLARD1a2d9152011-10-17 14:28:38 +0800293static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
Andrew Victorb2c65612007-02-08 09:42:40 +0100294 {
295 .id = AT91SAM9263_ID_PIOA,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800296 .regbase = AT91SAM9263_BASE_PIOA,
Andrew Victorb2c65612007-02-08 09:42:40 +0100297 }, {
298 .id = AT91SAM9263_ID_PIOB,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800299 .regbase = AT91SAM9263_BASE_PIOB,
Andrew Victorb2c65612007-02-08 09:42:40 +0100300 }, {
301 .id = AT91SAM9263_ID_PIOCDE,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800302 .regbase = AT91SAM9263_BASE_PIOC,
Andrew Victorb2c65612007-02-08 09:42:40 +0100303 }, {
304 .id = AT91SAM9263_ID_PIOCDE,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800305 .regbase = AT91SAM9263_BASE_PIOD,
Andrew Victorb2c65612007-02-08 09:42:40 +0100306 }, {
307 .id = AT91SAM9263_ID_PIOCDE,
Jean-Christophe PLAGNIOL-VILLARD80e91cb2011-09-16 23:37:50 +0800308 .regbase = AT91SAM9263_BASE_PIOE,
Andrew Victorb2c65612007-02-08 09:42:40 +0100309 }
310};
311
Andrew Victorb2c65612007-02-08 09:42:40 +0100312/* --------------------------------------------------------------------
313 * AT91SAM9263 processor initialization
314 * -------------------------------------------------------------------- */
315
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800316static void __init at91sam9263_map_io(void)
Andrew Victorb2c65612007-02-08 09:42:40 +0100317{
Jean-Christophe PLAGNIOL-VILLARDf0051d82011-05-10 03:20:09 +0800318 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
319 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800320}
Andrew Victorb2c65612007-02-08 09:42:40 +0100321
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800322static void __init at91sam9263_ioremap_registers(void)
323{
Jean-Christophe PLAGNIOL-VILLARDf22deee2011-11-01 01:23:20 +0800324 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
Jean-Christophe PLAGNIOL-VILLARDe9f68b52011-11-18 01:25:52 +0800325 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
Jean-Christophe PLAGNIOL-VILLARDf363c402012-02-13 12:58:53 +0800326 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
327 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
Jean-Christophe PLAGNIOL-VILLARD4ab0c5992011-09-18 22:29:50 +0800328 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
Jean-Christophe PLAGNIOL-VILLARDfaee0cc2011-10-14 01:37:09 +0800329 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
330 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
Jean-Christophe PLAGNIOL-VILLARD4342d642011-11-27 23:15:50 +0800331 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
Jean-Christophe PLAGNIOL-VILLARD6b6258912013-10-16 16:24:57 +0200332 at91_pm_set_standby(at91sam9_sdram_standby);
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800333}
334
Jean-Christophe PLAGNIOL-VILLARD46539372011-04-24 18:20:28 +0800335static void __init at91sam9263_initialize(void)
Jean-Christophe PLAGNIOL-VILLARD1b021a32011-04-28 20:19:32 +0800336{
Jean-Christophe PLAGNIOL-VILLARD0d781712012-02-05 20:25:32 +0800337 arm_pm_idle = at91sam9_idle;
Russell King1b2073e2011-11-03 09:53:29 +0000338 arm_pm_restart = at91sam9_alt_restart;
Andrew Victorb2c65612007-02-08 09:42:40 +0100339
Johan Hovold94c4c792013-10-16 11:56:15 +0200340 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
341 at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
342
Andrew Victorb2c65612007-02-08 09:42:40 +0100343 /* Register GPIO subsystem */
344 at91_gpio_init(at91sam9263_gpio, 5);
345}
346
347/* --------------------------------------------------------------------
348 * Interrupt initialization
349 * -------------------------------------------------------------------- */
350
351/*
352 * The default interrupt priority levels (0 = lowest, 7 = highest).
353 */
354static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
355 7, /* Advanced Interrupt Controller (FIQ) */
356 7, /* System Peripherals */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100357 1, /* Parallel IO Controller A */
358 1, /* Parallel IO Controller B */
359 1, /* Parallel IO Controller C, D and E */
Andrew Victorb2c65612007-02-08 09:42:40 +0100360 0,
361 0,
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100362 5, /* USART 0 */
363 5, /* USART 1 */
364 5, /* USART 2 */
Andrew Victorb2c65612007-02-08 09:42:40 +0100365 0, /* Multimedia Card Interface 0 */
366 0, /* Multimedia Card Interface 1 */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100367 3, /* CAN */
368 6, /* Two-Wire Interface */
369 5, /* Serial Peripheral Interface 0 */
370 5, /* Serial Peripheral Interface 1 */
371 4, /* Serial Synchronous Controller 0 */
372 4, /* Serial Synchronous Controller 1 */
373 5, /* AC97 Controller */
Andrew Victorb2c65612007-02-08 09:42:40 +0100374 0, /* Timer Counter 0, 1 and 2 */
375 0, /* Pulse Width Modulation Controller */
376 3, /* Ethernet */
377 0,
378 0, /* 2D Graphic Engine */
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100379 2, /* USB Device Port */
Andrew Victorb2c65612007-02-08 09:42:40 +0100380 0, /* Image Sensor Interface */
381 3, /* LDC Controller */
382 0, /* DMA Controller */
383 0,
Andrew Victor7cbed2b2007-11-20 08:46:53 +0100384 2, /* USB Host port */
Andrew Victorb2c65612007-02-08 09:42:40 +0100385 0, /* Advanced Interrupt Controller (IRQ0) */
386 0, /* Advanced Interrupt Controller (IRQ1) */
387};
388
Ludovic Desroches84ddb082013-03-22 13:24:09 +0000389AT91_SOC_START(at91sam9263)
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800390 .map_io = at91sam9263_map_io,
Jean-Christophe PLAGNIOL-VILLARD92100c122011-04-23 15:28:34 +0800391 .default_irq_priority = at91sam9263_default_irq_priority,
Jean-Christophe PLAGNIOL-VILLARD546c8302013-06-01 16:40:11 +0200392 .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
Jean-Christophe PLAGNIOL-VILLARDcfa5a1f2011-10-14 01:17:18 +0800393 .ioremap_registers = at91sam9263_ioremap_registers,
Jean-Christophe PLAGNIOL-VILLARD51ddec72011-04-24 18:15:34 +0800394 .register_clocks = at91sam9263_register_clocks,
Jean-Christophe PLAGNIOL-VILLARD21d08b92011-04-23 15:28:34 +0800395 .init = at91sam9263_initialize,
Jean-Christophe PLAGNIOL-VILLARD8d39e0fd02012-08-16 17:36:55 +0800396AT91_SOC_END