Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Format of an instruction in memory. |
| 3 | * |
| 4 | * This file is subject to the terms and conditions of the GNU General Public |
| 5 | * License. See the file "COPYING" in the main directory of this archive |
| 6 | * for more details. |
| 7 | * |
| 8 | * Copyright (C) 1996, 2000 by Ralf Baechle |
Thiemo Seufer | ca30225 | 2006-05-15 18:27:03 +0100 | [diff] [blame] | 9 | * Copyright (C) 2006 by Thiemo Seufer |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | */ |
| 11 | #ifndef _ASM_INST_H |
| 12 | #define _ASM_INST_H |
| 13 | |
Ralf Baechle | 90e8cac | 2013-01-17 15:11:16 +0100 | [diff] [blame] | 14 | #include <uapi/asm/inst.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | |
| 16 | /* HACHACHAHCAHC ... */ |
| 17 | |
| 18 | /* In case some other massaging is needed, keep MIPSInst as wrapper */ |
| 19 | |
| 20 | #define MIPSInst(x) x |
| 21 | |
| 22 | #define I_OPCODE_SFT 26 |
| 23 | #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT) |
| 24 | |
| 25 | #define I_JTARGET_SFT 0 |
| 26 | #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff) |
| 27 | |
| 28 | #define I_RS_SFT 21 |
| 29 | #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT) |
| 30 | |
| 31 | #define I_RT_SFT 16 |
| 32 | #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT) |
| 33 | |
| 34 | #define I_IMM_SFT 0 |
| 35 | #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff))) |
| 36 | #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff) |
| 37 | |
| 38 | #define I_CACHEOP_SFT 18 |
| 39 | #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT) |
| 40 | |
| 41 | #define I_CACHESEL_SFT 16 |
| 42 | #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT) |
| 43 | |
| 44 | #define I_RD_SFT 11 |
| 45 | #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT) |
| 46 | |
| 47 | #define I_RE_SFT 6 |
| 48 | #define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT) |
| 49 | |
| 50 | #define I_FUNC_SFT 0 |
| 51 | #define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f) |
| 52 | |
| 53 | #define I_FFMT_SFT 21 |
| 54 | #define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT) |
| 55 | |
| 56 | #define I_FT_SFT 16 |
| 57 | #define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT) |
| 58 | |
| 59 | #define I_FS_SFT 11 |
| 60 | #define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT) |
| 61 | |
| 62 | #define I_FD_SFT 6 |
| 63 | #define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT) |
| 64 | |
| 65 | #define I_FR_SFT 21 |
| 66 | #define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT) |
| 67 | |
Tiezhu Yang | 919af8b | 2021-01-22 15:53:18 +0800 | [diff] [blame] | 68 | #define I_FMA_FUNC_SFT 3 |
| 69 | #define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x00000038) >> I_FMA_FUNC_SFT) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | |
| 71 | #define I_FMA_FFMT_SFT 0 |
Tiezhu Yang | 919af8b | 2021-01-22 15:53:18 +0800 | [diff] [blame] | 72 | #define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000007) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | |
| 74 | typedef unsigned int mips_instruction; |
| 75 | |
Leonid Yegoshin | 102cedc | 2013-03-25 12:09:02 -0500 | [diff] [blame] | 76 | /* microMIPS instruction decode structure. Do NOT export!!! */ |
| 77 | struct mm_decoded_insn { |
| 78 | mips_instruction insn; |
| 79 | mips_instruction next_insn; |
| 80 | int pc_inc; |
| 81 | int next_pc_inc; |
| 82 | int micro_mips_mode; |
| 83 | }; |
| 84 | |
Steven J. Hill | 8508488 | 2013-03-25 13:45:19 -0500 | [diff] [blame] | 85 | /* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */ |
| 86 | extern const int reg16to32[]; |
| 87 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 88 | #endif /* _ASM_INST_H */ |