Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1 | /* |
| 2 | * lpc_ich.c - LPC interface for Intel ICH |
| 3 | * |
| 4 | * LPC bridge function of the Intel ICH contains many other |
| 5 | * functional units, such as Interrupt controllers, Timers, |
| 6 | * Power Management, System Management, GPIO, RTC, and LPC |
| 7 | * Configuration Registers. |
| 8 | * |
| 9 | * This driver is derived from lpc_sch. |
| 10 | |
| 11 | * Copyright (c) 2011 Extreme Engineering Solution, Inc. |
| 12 | * Author: Aaron Sierra <asierra@xes-inc.com> |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License 2 as published |
| 16 | * by the Free Software Foundation. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 23 | * This driver supports the following I/O Controller hubs: |
| 24 | * (See the intel documentation on http://developer.intel.com.) |
| 25 | * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) |
| 26 | * document number 290687-002, 298242-027: 82801BA (ICH2) |
| 27 | * document number 290733-003, 290739-013: 82801CA (ICH3-S) |
| 28 | * document number 290716-001, 290718-007: 82801CAM (ICH3-M) |
| 29 | * document number 290744-001, 290745-025: 82801DB (ICH4) |
| 30 | * document number 252337-001, 252663-008: 82801DBM (ICH4-M) |
| 31 | * document number 273599-001, 273645-002: 82801E (C-ICH) |
| 32 | * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) |
| 33 | * document number 300641-004, 300884-013: 6300ESB |
| 34 | * document number 301473-002, 301474-026: 82801F (ICH6) |
| 35 | * document number 313082-001, 313075-006: 631xESB, 632xESB |
| 36 | * document number 307013-003, 307014-024: 82801G (ICH7) |
| 37 | * document number 322896-001, 322897-001: NM10 |
| 38 | * document number 313056-003, 313057-017: 82801H (ICH8) |
| 39 | * document number 316972-004, 316973-012: 82801I (ICH9) |
| 40 | * document number 319973-002, 319974-002: 82801J (ICH10) |
| 41 | * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) |
| 42 | * document number 320066-003, 320257-008: EP80597 (IICH) |
| 43 | * document number 324645-001, 324646-001: Cougar Point (CPT) |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 44 | */ |
| 45 | |
| 46 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 47 | |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 48 | #include <linux/kernel.h> |
| 49 | #include <linux/module.h> |
| 50 | #include <linux/errno.h> |
| 51 | #include <linux/acpi.h> |
| 52 | #include <linux/pci.h> |
| 53 | #include <linux/mfd/core.h> |
| 54 | #include <linux/mfd/lpc_ich.h> |
Matt Fleming | 420b54d | 2015-08-06 13:46:24 +0100 | [diff] [blame] | 55 | #include <linux/platform_data/itco_wdt.h> |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 56 | |
| 57 | #define ACPIBASE 0x40 |
| 58 | #define ACPIBASE_GPE_OFF 0x28 |
| 59 | #define ACPIBASE_GPE_END 0x2f |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 60 | #define ACPIBASE_SMI_OFF 0x30 |
| 61 | #define ACPIBASE_SMI_END 0x33 |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 62 | #define ACPIBASE_PMC_OFF 0x08 |
| 63 | #define ACPIBASE_PMC_END 0x0c |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 64 | #define ACPIBASE_TCO_OFF 0x60 |
| 65 | #define ACPIBASE_TCO_END 0x7f |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 66 | #define ACPICTRL_PMCBASE 0x44 |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 67 | |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 68 | #define ACPIBASE_GCS_OFF 0x3410 |
| 69 | #define ACPIBASE_GCS_END 0x3414 |
| 70 | |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 71 | #define SPIBASE_BYT 0x54 |
| 72 | #define SPIBASE_BYT_SZ 512 |
| 73 | #define SPIBASE_BYT_EN BIT(1) |
| 74 | |
| 75 | #define SPIBASE_LPT 0x3800 |
| 76 | #define SPIBASE_LPT_SZ 512 |
| 77 | #define BCR 0xdc |
| 78 | #define BCR_WPD BIT(0) |
| 79 | |
Mika Westerberg | 87eb832 | 2016-11-28 15:06:26 +0300 | [diff] [blame] | 80 | #define SPIBASE_APL_SZ 4096 |
| 81 | |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 82 | #define GPIOBASE_ICH0 0x58 |
| 83 | #define GPIOCTRL_ICH0 0x5C |
| 84 | #define GPIOBASE_ICH6 0x48 |
| 85 | #define GPIOCTRL_ICH6 0x4C |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 86 | |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 87 | #define RCBABASE 0xf0 |
| 88 | |
| 89 | #define wdt_io_res(i) wdt_res(0, i) |
| 90 | #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) |
| 91 | #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) |
| 92 | |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 93 | struct lpc_ich_priv { |
| 94 | int chipset; |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 95 | |
| 96 | int abase; /* ACPI base */ |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 97 | int actrl_pbase; /* ACPI control or PMC base */ |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 98 | int gbase; /* GPIO base */ |
| 99 | int gctrl; /* GPIO control */ |
| 100 | |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 101 | int abase_save; /* Cached ACPI base value */ |
| 102 | int actrl_pbase_save; /* Cached ACPI control or PMC base value */ |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 103 | int gctrl_save; /* Cached GPIO control value */ |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 104 | }; |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 105 | |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 106 | static struct resource wdt_ich_res[] = { |
| 107 | /* ACPI - TCO */ |
| 108 | { |
| 109 | .flags = IORESOURCE_IO, |
| 110 | }, |
| 111 | /* ACPI - SMI */ |
| 112 | { |
| 113 | .flags = IORESOURCE_IO, |
| 114 | }, |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 115 | /* GCS or PMC */ |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 116 | { |
| 117 | .flags = IORESOURCE_MEM, |
| 118 | }, |
| 119 | }; |
| 120 | |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 121 | static struct resource gpio_ich_res[] = { |
| 122 | /* GPIO */ |
| 123 | { |
| 124 | .flags = IORESOURCE_IO, |
| 125 | }, |
| 126 | /* ACPI - GPE0 */ |
| 127 | { |
| 128 | .flags = IORESOURCE_IO, |
| 129 | }, |
| 130 | }; |
| 131 | |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 132 | static struct resource intel_spi_res[] = { |
| 133 | { |
| 134 | .flags = IORESOURCE_MEM, |
| 135 | } |
| 136 | }; |
| 137 | |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 138 | static struct mfd_cell lpc_ich_wdt_cell = { |
| 139 | .name = "iTCO_wdt", |
| 140 | .num_resources = ARRAY_SIZE(wdt_ich_res), |
| 141 | .resources = wdt_ich_res, |
| 142 | .ignore_resource_conflicts = true, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 143 | }; |
| 144 | |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 145 | static struct mfd_cell lpc_ich_gpio_cell = { |
| 146 | .name = "gpio_ich", |
| 147 | .num_resources = ARRAY_SIZE(gpio_ich_res), |
| 148 | .resources = gpio_ich_res, |
| 149 | .ignore_resource_conflicts = true, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 150 | }; |
| 151 | |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 152 | |
| 153 | static struct mfd_cell lpc_ich_spi_cell = { |
| 154 | .name = "intel-spi", |
| 155 | .num_resources = ARRAY_SIZE(intel_spi_res), |
| 156 | .resources = intel_spi_res, |
| 157 | .ignore_resource_conflicts = true, |
| 158 | }; |
| 159 | |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 160 | /* chipset related info */ |
| 161 | enum lpc_chipsets { |
| 162 | LPC_ICH = 0, /* ICH */ |
| 163 | LPC_ICH0, /* ICH0 */ |
| 164 | LPC_ICH2, /* ICH2 */ |
| 165 | LPC_ICH2M, /* ICH2-M */ |
| 166 | LPC_ICH3, /* ICH3-S */ |
| 167 | LPC_ICH3M, /* ICH3-M */ |
| 168 | LPC_ICH4, /* ICH4 */ |
| 169 | LPC_ICH4M, /* ICH4-M */ |
| 170 | LPC_CICH, /* C-ICH */ |
| 171 | LPC_ICH5, /* ICH5 & ICH5R */ |
| 172 | LPC_6300ESB, /* 6300ESB */ |
| 173 | LPC_ICH6, /* ICH6 & ICH6R */ |
| 174 | LPC_ICH6M, /* ICH6-M */ |
| 175 | LPC_ICH6W, /* ICH6W & ICH6RW */ |
| 176 | LPC_631XESB, /* 631xESB/632xESB */ |
| 177 | LPC_ICH7, /* ICH7 & ICH7R */ |
| 178 | LPC_ICH7DH, /* ICH7DH */ |
| 179 | LPC_ICH7M, /* ICH7-M & ICH7-U */ |
| 180 | LPC_ICH7MDH, /* ICH7-M DH */ |
| 181 | LPC_NM10, /* NM10 */ |
| 182 | LPC_ICH8, /* ICH8 & ICH8R */ |
| 183 | LPC_ICH8DH, /* ICH8DH */ |
| 184 | LPC_ICH8DO, /* ICH8DO */ |
| 185 | LPC_ICH8M, /* ICH8M */ |
| 186 | LPC_ICH8ME, /* ICH8M-E */ |
| 187 | LPC_ICH9, /* ICH9 */ |
| 188 | LPC_ICH9R, /* ICH9R */ |
| 189 | LPC_ICH9DH, /* ICH9DH */ |
| 190 | LPC_ICH9DO, /* ICH9DO */ |
| 191 | LPC_ICH9M, /* ICH9M */ |
| 192 | LPC_ICH9ME, /* ICH9M-E */ |
| 193 | LPC_ICH10, /* ICH10 */ |
| 194 | LPC_ICH10R, /* ICH10R */ |
| 195 | LPC_ICH10D, /* ICH10D */ |
| 196 | LPC_ICH10DO, /* ICH10DO */ |
| 197 | LPC_PCH, /* PCH Desktop Full Featured */ |
| 198 | LPC_PCHM, /* PCH Mobile Full Featured */ |
| 199 | LPC_P55, /* P55 */ |
| 200 | LPC_PM55, /* PM55 */ |
| 201 | LPC_H55, /* H55 */ |
| 202 | LPC_QM57, /* QM57 */ |
| 203 | LPC_H57, /* H57 */ |
| 204 | LPC_HM55, /* HM55 */ |
| 205 | LPC_Q57, /* Q57 */ |
| 206 | LPC_HM57, /* HM57 */ |
| 207 | LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ |
| 208 | LPC_QS57, /* QS57 */ |
| 209 | LPC_3400, /* 3400 */ |
| 210 | LPC_3420, /* 3420 */ |
| 211 | LPC_3450, /* 3450 */ |
| 212 | LPC_EP80579, /* EP80579 */ |
| 213 | LPC_CPT, /* Cougar Point */ |
| 214 | LPC_CPTD, /* Cougar Point Desktop */ |
| 215 | LPC_CPTM, /* Cougar Point Mobile */ |
| 216 | LPC_PBG, /* Patsburg */ |
| 217 | LPC_DH89XXCC, /* DH89xxCC */ |
| 218 | LPC_PPT, /* Panther Point */ |
| 219 | LPC_LPT, /* Lynx Point */ |
James Ralston | 7fb9c1a | 2012-08-09 09:46:13 -0700 | [diff] [blame] | 220 | LPC_LPT_LP, /* Lynx Point-LP */ |
James Ralston | 6e6680e | 2013-02-08 17:33:38 -0800 | [diff] [blame] | 221 | LPC_WBG, /* Wellsburg */ |
James Ralston | 8477128 | 2013-05-09 12:38:53 -0700 | [diff] [blame] | 222 | LPC_AVN, /* Avoton SoC */ |
Peter Tyser | 6111ec7 | 2014-03-10 16:34:58 -0500 | [diff] [blame] | 223 | LPC_BAYTRAIL, /* Bay Trail SoC */ |
Seth Heasley | 283aae8 | 2013-06-19 17:04:25 -0700 | [diff] [blame] | 224 | LPC_COLETO, /* Coleto Creek */ |
James Ralston | 5e90169 | 2013-11-04 09:31:20 -0800 | [diff] [blame] | 225 | LPC_WPT_LP, /* Wildcat Point-LP */ |
Alan Cox | ff0c9da | 2014-08-21 12:46:25 +0300 | [diff] [blame] | 226 | LPC_BRASWELL, /* Braswell SoC */ |
Alexandra Yates | 6223a30 | 2015-11-06 15:19:48 -0800 | [diff] [blame] | 227 | LPC_LEWISBURG, /* Lewisburg */ |
James Ralston | fea3104 | 2014-08-27 14:34:25 -0700 | [diff] [blame] | 228 | LPC_9S, /* 9 Series */ |
Mika Westerberg | 87eb832 | 2016-11-28 15:06:26 +0300 | [diff] [blame] | 229 | LPC_APL, /* Apollo Lake SoC */ |
Mika Westerberg | a6450cb | 2017-04-10 13:28:45 +0300 | [diff] [blame] | 230 | LPC_GLK, /* Gemini Lake SoC */ |
Priyalee Kushwaha | f36c1f6 | 2017-02-03 18:05:43 +0000 | [diff] [blame] | 231 | LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/ |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 232 | }; |
| 233 | |
Jingoo Han | a1ca138 | 2013-08-01 10:59:11 +0900 | [diff] [blame] | 234 | static struct lpc_ich_info lpc_chipset_info[] = { |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 235 | [LPC_ICH] = { |
| 236 | .name = "ICH", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 237 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 238 | }, |
| 239 | [LPC_ICH0] = { |
| 240 | .name = "ICH0", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 241 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 242 | }, |
| 243 | [LPC_ICH2] = { |
| 244 | .name = "ICH2", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 245 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 246 | }, |
| 247 | [LPC_ICH2M] = { |
| 248 | .name = "ICH2-M", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 249 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 250 | }, |
| 251 | [LPC_ICH3] = { |
| 252 | .name = "ICH3-S", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 253 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 254 | }, |
| 255 | [LPC_ICH3M] = { |
| 256 | .name = "ICH3-M", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 257 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 258 | }, |
| 259 | [LPC_ICH4] = { |
| 260 | .name = "ICH4", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 261 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 262 | }, |
| 263 | [LPC_ICH4M] = { |
| 264 | .name = "ICH4-M", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 265 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 266 | }, |
| 267 | [LPC_CICH] = { |
| 268 | .name = "C-ICH", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 269 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 270 | }, |
| 271 | [LPC_ICH5] = { |
| 272 | .name = "ICH5 or ICH5R", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 273 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 274 | }, |
| 275 | [LPC_6300ESB] = { |
| 276 | .name = "6300ESB", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 277 | .iTCO_version = 1, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 278 | }, |
| 279 | [LPC_ICH6] = { |
| 280 | .name = "ICH6 or ICH6R", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 281 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 282 | .gpio_version = ICH_V6_GPIO, |
| 283 | }, |
| 284 | [LPC_ICH6M] = { |
| 285 | .name = "ICH6-M", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 286 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 287 | .gpio_version = ICH_V6_GPIO, |
| 288 | }, |
| 289 | [LPC_ICH6W] = { |
| 290 | .name = "ICH6W or ICH6RW", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 291 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 292 | .gpio_version = ICH_V6_GPIO, |
| 293 | }, |
| 294 | [LPC_631XESB] = { |
| 295 | .name = "631xESB/632xESB", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 296 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 297 | .gpio_version = ICH_V6_GPIO, |
| 298 | }, |
| 299 | [LPC_ICH7] = { |
| 300 | .name = "ICH7 or ICH7R", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 301 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 302 | .gpio_version = ICH_V7_GPIO, |
| 303 | }, |
| 304 | [LPC_ICH7DH] = { |
| 305 | .name = "ICH7DH", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 306 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 307 | .gpio_version = ICH_V7_GPIO, |
| 308 | }, |
| 309 | [LPC_ICH7M] = { |
| 310 | .name = "ICH7-M or ICH7-U", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 311 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 312 | .gpio_version = ICH_V7_GPIO, |
| 313 | }, |
| 314 | [LPC_ICH7MDH] = { |
| 315 | .name = "ICH7-M DH", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 316 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 317 | .gpio_version = ICH_V7_GPIO, |
| 318 | }, |
| 319 | [LPC_NM10] = { |
| 320 | .name = "NM10", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 321 | .iTCO_version = 2, |
Peter Tyser | 117bbfe | 2014-03-10 16:34:57 -0500 | [diff] [blame] | 322 | .gpio_version = ICH_V7_GPIO, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 323 | }, |
| 324 | [LPC_ICH8] = { |
| 325 | .name = "ICH8 or ICH8R", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 326 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 327 | .gpio_version = ICH_V7_GPIO, |
| 328 | }, |
| 329 | [LPC_ICH8DH] = { |
| 330 | .name = "ICH8DH", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 331 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 332 | .gpio_version = ICH_V7_GPIO, |
| 333 | }, |
| 334 | [LPC_ICH8DO] = { |
| 335 | .name = "ICH8DO", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 336 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 337 | .gpio_version = ICH_V7_GPIO, |
| 338 | }, |
| 339 | [LPC_ICH8M] = { |
| 340 | .name = "ICH8M", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 341 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 342 | .gpio_version = ICH_V7_GPIO, |
| 343 | }, |
| 344 | [LPC_ICH8ME] = { |
| 345 | .name = "ICH8M-E", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 346 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 347 | .gpio_version = ICH_V7_GPIO, |
| 348 | }, |
| 349 | [LPC_ICH9] = { |
| 350 | .name = "ICH9", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 351 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 352 | .gpio_version = ICH_V9_GPIO, |
| 353 | }, |
| 354 | [LPC_ICH9R] = { |
| 355 | .name = "ICH9R", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 356 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 357 | .gpio_version = ICH_V9_GPIO, |
| 358 | }, |
| 359 | [LPC_ICH9DH] = { |
| 360 | .name = "ICH9DH", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 361 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 362 | .gpio_version = ICH_V9_GPIO, |
| 363 | }, |
| 364 | [LPC_ICH9DO] = { |
| 365 | .name = "ICH9DO", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 366 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 367 | .gpio_version = ICH_V9_GPIO, |
| 368 | }, |
| 369 | [LPC_ICH9M] = { |
| 370 | .name = "ICH9M", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 371 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 372 | .gpio_version = ICH_V9_GPIO, |
| 373 | }, |
| 374 | [LPC_ICH9ME] = { |
| 375 | .name = "ICH9M-E", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 376 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 377 | .gpio_version = ICH_V9_GPIO, |
| 378 | }, |
| 379 | [LPC_ICH10] = { |
| 380 | .name = "ICH10", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 381 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 382 | .gpio_version = ICH_V10CONS_GPIO, |
| 383 | }, |
| 384 | [LPC_ICH10R] = { |
| 385 | .name = "ICH10R", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 386 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 387 | .gpio_version = ICH_V10CONS_GPIO, |
| 388 | }, |
| 389 | [LPC_ICH10D] = { |
| 390 | .name = "ICH10D", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 391 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 392 | .gpio_version = ICH_V10CORP_GPIO, |
| 393 | }, |
| 394 | [LPC_ICH10DO] = { |
| 395 | .name = "ICH10DO", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 396 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 397 | .gpio_version = ICH_V10CORP_GPIO, |
| 398 | }, |
| 399 | [LPC_PCH] = { |
| 400 | .name = "PCH Desktop Full Featured", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 401 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 402 | .gpio_version = ICH_V5_GPIO, |
| 403 | }, |
| 404 | [LPC_PCHM] = { |
| 405 | .name = "PCH Mobile Full Featured", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 406 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 407 | .gpio_version = ICH_V5_GPIO, |
| 408 | }, |
| 409 | [LPC_P55] = { |
| 410 | .name = "P55", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 411 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 412 | .gpio_version = ICH_V5_GPIO, |
| 413 | }, |
| 414 | [LPC_PM55] = { |
| 415 | .name = "PM55", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 416 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 417 | .gpio_version = ICH_V5_GPIO, |
| 418 | }, |
| 419 | [LPC_H55] = { |
| 420 | .name = "H55", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 421 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 422 | .gpio_version = ICH_V5_GPIO, |
| 423 | }, |
| 424 | [LPC_QM57] = { |
| 425 | .name = "QM57", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 426 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 427 | .gpio_version = ICH_V5_GPIO, |
| 428 | }, |
| 429 | [LPC_H57] = { |
| 430 | .name = "H57", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 431 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 432 | .gpio_version = ICH_V5_GPIO, |
| 433 | }, |
| 434 | [LPC_HM55] = { |
| 435 | .name = "HM55", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 436 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 437 | .gpio_version = ICH_V5_GPIO, |
| 438 | }, |
| 439 | [LPC_Q57] = { |
| 440 | .name = "Q57", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 441 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 442 | .gpio_version = ICH_V5_GPIO, |
| 443 | }, |
| 444 | [LPC_HM57] = { |
| 445 | .name = "HM57", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 446 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 447 | .gpio_version = ICH_V5_GPIO, |
| 448 | }, |
| 449 | [LPC_PCHMSFF] = { |
| 450 | .name = "PCH Mobile SFF Full Featured", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 451 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 452 | .gpio_version = ICH_V5_GPIO, |
| 453 | }, |
| 454 | [LPC_QS57] = { |
| 455 | .name = "QS57", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 456 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 457 | .gpio_version = ICH_V5_GPIO, |
| 458 | }, |
| 459 | [LPC_3400] = { |
| 460 | .name = "3400", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 461 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 462 | .gpio_version = ICH_V5_GPIO, |
| 463 | }, |
| 464 | [LPC_3420] = { |
| 465 | .name = "3420", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 466 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 467 | .gpio_version = ICH_V5_GPIO, |
| 468 | }, |
| 469 | [LPC_3450] = { |
| 470 | .name = "3450", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 471 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 472 | .gpio_version = ICH_V5_GPIO, |
| 473 | }, |
| 474 | [LPC_EP80579] = { |
| 475 | .name = "EP80579", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 476 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 477 | }, |
| 478 | [LPC_CPT] = { |
| 479 | .name = "Cougar Point", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 480 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 481 | .gpio_version = ICH_V5_GPIO, |
| 482 | }, |
| 483 | [LPC_CPTD] = { |
| 484 | .name = "Cougar Point Desktop", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 485 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 486 | .gpio_version = ICH_V5_GPIO, |
| 487 | }, |
| 488 | [LPC_CPTM] = { |
| 489 | .name = "Cougar Point Mobile", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 490 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 491 | .gpio_version = ICH_V5_GPIO, |
| 492 | }, |
| 493 | [LPC_PBG] = { |
| 494 | .name = "Patsburg", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 495 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 496 | }, |
| 497 | [LPC_DH89XXCC] = { |
| 498 | .name = "DH89xxCC", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 499 | .iTCO_version = 2, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 500 | }, |
| 501 | [LPC_PPT] = { |
| 502 | .name = "Panther Point", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 503 | .iTCO_version = 2, |
Guenter Roeck | 62cf2cd | 2014-04-05 08:49:34 -0700 | [diff] [blame] | 504 | .gpio_version = ICH_V5_GPIO, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 505 | }, |
| 506 | [LPC_LPT] = { |
| 507 | .name = "Lynx Point", |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 508 | .iTCO_version = 2, |
Dan Gora | e420d6a | 2016-07-06 22:35:02 -0300 | [diff] [blame] | 509 | .gpio_version = ICH_V5_GPIO, |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 510 | .spi_type = INTEL_SPI_LPT, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 511 | }, |
James Ralston | 7fb9c1a | 2012-08-09 09:46:13 -0700 | [diff] [blame] | 512 | [LPC_LPT_LP] = { |
| 513 | .name = "Lynx Point_LP", |
| 514 | .iTCO_version = 2, |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 515 | .spi_type = INTEL_SPI_LPT, |
James Ralston | 7fb9c1a | 2012-08-09 09:46:13 -0700 | [diff] [blame] | 516 | }, |
James Ralston | 6e6680e | 2013-02-08 17:33:38 -0800 | [diff] [blame] | 517 | [LPC_WBG] = { |
| 518 | .name = "Wellsburg", |
| 519 | .iTCO_version = 2, |
| 520 | }, |
James Ralston | 8477128 | 2013-05-09 12:38:53 -0700 | [diff] [blame] | 521 | [LPC_AVN] = { |
| 522 | .name = "Avoton SoC", |
Peter Tyser | c48cf59 | 2014-03-10 16:34:56 -0500 | [diff] [blame] | 523 | .iTCO_version = 3, |
Vincent Donnefort | facd993 | 2014-02-14 15:01:54 +0100 | [diff] [blame] | 524 | .gpio_version = AVOTON_GPIO, |
Joakim Tjernlund | 07d7091 | 2017-10-11 12:40:55 +0200 | [diff] [blame] | 525 | .spi_type = INTEL_SPI_BYT, |
James Ralston | 8477128 | 2013-05-09 12:38:53 -0700 | [diff] [blame] | 526 | }, |
Peter Tyser | 6111ec7 | 2014-03-10 16:34:58 -0500 | [diff] [blame] | 527 | [LPC_BAYTRAIL] = { |
| 528 | .name = "Bay Trail SoC", |
| 529 | .iTCO_version = 3, |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 530 | .spi_type = INTEL_SPI_BYT, |
Peter Tyser | 6111ec7 | 2014-03-10 16:34:58 -0500 | [diff] [blame] | 531 | }, |
Seth Heasley | 283aae8 | 2013-06-19 17:04:25 -0700 | [diff] [blame] | 532 | [LPC_COLETO] = { |
| 533 | .name = "Coleto Creek", |
| 534 | .iTCO_version = 2, |
| 535 | }, |
James Ralston | 5e90169 | 2013-11-04 09:31:20 -0800 | [diff] [blame] | 536 | [LPC_WPT_LP] = { |
James Ralston | a8822df | 2013-11-27 09:38:04 +0100 | [diff] [blame] | 537 | .name = "Wildcat Point_LP", |
James Ralston | 5e90169 | 2013-11-04 09:31:20 -0800 | [diff] [blame] | 538 | .iTCO_version = 2, |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 539 | .spi_type = INTEL_SPI_LPT, |
James Ralston | 5e90169 | 2013-11-04 09:31:20 -0800 | [diff] [blame] | 540 | }, |
Alan Cox | ff0c9da | 2014-08-21 12:46:25 +0300 | [diff] [blame] | 541 | [LPC_BRASWELL] = { |
| 542 | .name = "Braswell SoC", |
| 543 | .iTCO_version = 3, |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 544 | .spi_type = INTEL_SPI_BYT, |
Alan Cox | ff0c9da | 2014-08-21 12:46:25 +0300 | [diff] [blame] | 545 | }, |
Alexandra Yates | 6223a30 | 2015-11-06 15:19:48 -0800 | [diff] [blame] | 546 | [LPC_LEWISBURG] = { |
| 547 | .name = "Lewisburg", |
| 548 | .iTCO_version = 2, |
| 549 | }, |
James Ralston | fea3104 | 2014-08-27 14:34:25 -0700 | [diff] [blame] | 550 | [LPC_9S] = { |
| 551 | .name = "9 Series", |
| 552 | .iTCO_version = 2, |
Dan Gora | e420d6a | 2016-07-06 22:35:02 -0300 | [diff] [blame] | 553 | .gpio_version = ICH_V5_GPIO, |
James Ralston | fea3104 | 2014-08-27 14:34:25 -0700 | [diff] [blame] | 554 | }, |
Mika Westerberg | 87eb832 | 2016-11-28 15:06:26 +0300 | [diff] [blame] | 555 | [LPC_APL] = { |
| 556 | .name = "Apollo Lake SoC", |
Tan Jui Nee | e93c102 | 2017-01-28 16:27:33 +0200 | [diff] [blame] | 557 | .iTCO_version = 5, |
Mika Westerberg | 87eb832 | 2016-11-28 15:06:26 +0300 | [diff] [blame] | 558 | .spi_type = INTEL_SPI_BXT, |
| 559 | }, |
Mika Westerberg | a6450cb | 2017-04-10 13:28:45 +0300 | [diff] [blame] | 560 | [LPC_GLK] = { |
| 561 | .name = "Gemini Lake SoC", |
| 562 | .spi_type = INTEL_SPI_BXT, |
| 563 | }, |
Priyalee Kushwaha | f36c1f6 | 2017-02-03 18:05:43 +0000 | [diff] [blame] | 564 | [LPC_COUGARMOUNTAIN] = { |
| 565 | .name = "Cougar Mountain SoC", |
| 566 | .iTCO_version = 3, |
| 567 | }, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 568 | }; |
| 569 | |
| 570 | /* |
| 571 | * This data only exists for exporting the supported PCI ids |
| 572 | * via MODULE_DEVICE_TABLE. We do not actually register a |
| 573 | * pci_driver, because the I/O Controller Hub has also other |
| 574 | * functions that probably will be registered by other drivers. |
| 575 | */ |
Jingoo Han | 36fcd06 | 2013-12-03 08:15:39 +0900 | [diff] [blame] | 576 | static const struct pci_device_id lpc_ich_ids[] = { |
Andy Shevchenko | aec9038 | 2015-03-27 20:06:01 +0200 | [diff] [blame] | 577 | { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL}, |
| 578 | { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, |
| 579 | { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, |
| 580 | { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, |
| 581 | { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, |
| 582 | { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, |
| 583 | { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, |
| 584 | { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, |
| 585 | { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, |
| 586 | { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, |
| 587 | { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, |
| 588 | { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, |
| 589 | { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, |
| 590 | { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, |
| 591 | { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, |
| 592 | { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, |
| 593 | { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, |
| 594 | { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, |
| 595 | { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, |
| 596 | { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, |
| 597 | { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, |
| 598 | { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, |
| 599 | { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, |
| 600 | { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, |
| 601 | { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, |
| 602 | { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, |
| 603 | { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, |
| 604 | { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, |
| 605 | { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, |
| 606 | { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, |
| 607 | { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, |
| 608 | { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, |
| 609 | { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, |
| 610 | { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, |
| 611 | { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, |
| 612 | { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, |
| 613 | { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, |
| 614 | { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, |
| 615 | { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, |
| 616 | { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, |
| 617 | { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, |
| 618 | { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, |
| 619 | { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, |
| 620 | { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, |
| 621 | { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, |
| 622 | { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, |
| 623 | { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, |
| 624 | { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, |
| 625 | { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, |
| 626 | { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, |
| 627 | { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, |
| 628 | { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, |
| 629 | { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, |
| 630 | { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, |
| 631 | { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, |
| 632 | { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, |
| 633 | { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, |
| 634 | { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, |
| 635 | { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, |
| 636 | { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, |
| 637 | { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, |
| 638 | { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, |
| 639 | { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, |
| 640 | { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, |
| 641 | { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, |
| 642 | { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, |
| 643 | { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN}, |
| 644 | { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, |
| 645 | { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, |
| 646 | { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, |
| 647 | { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL}, |
| 648 | { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, |
| 649 | { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 650 | { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, |
| 651 | { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, |
| 652 | { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, |
| 653 | { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, |
Andy Shevchenko | 7271575 | 2015-03-31 14:47:29 +0300 | [diff] [blame] | 654 | { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 655 | { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, |
| 656 | { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, |
| 657 | { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, |
| 658 | { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 659 | { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, |
| 660 | { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, |
| 661 | { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, |
| 662 | { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, |
| 663 | { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, |
| 664 | { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, |
| 665 | { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, |
| 666 | { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, |
| 667 | { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, |
| 668 | { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, |
| 669 | { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, |
| 670 | { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, |
| 671 | { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, |
| 672 | { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, |
| 673 | { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, |
| 674 | { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, |
| 675 | { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, |
| 676 | { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, |
| 677 | { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, |
| 678 | { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, |
| 679 | { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 680 | { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, |
Andy Shevchenko | 7271575 | 2015-03-31 14:47:29 +0300 | [diff] [blame] | 681 | { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 682 | { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 683 | { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, |
Andy Shevchenko | 7271575 | 2015-03-31 14:47:29 +0300 | [diff] [blame] | 684 | { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 685 | { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, |
Andy Shevchenko | 7271575 | 2015-03-31 14:47:29 +0300 | [diff] [blame] | 686 | { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 687 | { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, |
| 688 | { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, |
| 689 | { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 690 | { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, |
| 691 | { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, |
Andy Shevchenko | 7271575 | 2015-03-31 14:47:29 +0300 | [diff] [blame] | 692 | { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 693 | { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, |
Andy Shevchenko | 7271575 | 2015-03-31 14:47:29 +0300 | [diff] [blame] | 694 | { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, |
| 695 | { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, |
Mika Westerberg | a6450cb | 2017-04-10 13:28:45 +0300 | [diff] [blame] | 696 | { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK}, |
Priyalee Kushwaha | f36c1f6 | 2017-02-03 18:05:43 +0000 | [diff] [blame] | 697 | { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 698 | { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, |
Andy Shevchenko | 7271575 | 2015-03-31 14:47:29 +0300 | [diff] [blame] | 699 | { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, |
| 700 | { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, |
| 701 | { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 702 | { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, |
| 703 | { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, |
| 704 | { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, |
| 705 | { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, |
| 706 | { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, |
| 707 | { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, |
| 708 | { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, |
| 709 | { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, |
| 710 | { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, |
| 711 | { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, |
| 712 | { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, |
| 713 | { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, |
| 714 | { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, |
| 715 | { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, |
| 716 | { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, |
| 717 | { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, |
Mika Westerberg | 87eb832 | 2016-11-28 15:06:26 +0300 | [diff] [blame] | 718 | { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 719 | { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, |
| 720 | { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, |
| 721 | { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, |
| 722 | { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, |
| 723 | { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, |
| 724 | { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, |
| 725 | { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, |
| 726 | { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, |
| 727 | { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, |
| 728 | { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, |
| 729 | { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, |
| 730 | { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, |
| 731 | { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, |
| 732 | { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, |
| 733 | { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, |
| 734 | { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, |
| 735 | { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, |
| 736 | { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, |
| 737 | { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, |
| 738 | { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, |
| 739 | { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, |
| 740 | { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, |
| 741 | { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, |
| 742 | { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, |
| 743 | { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, |
| 744 | { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, |
| 745 | { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, |
| 746 | { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, |
| 747 | { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, |
| 748 | { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, |
| 749 | { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, |
| 750 | { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, |
Andy Shevchenko | aec9038 | 2015-03-27 20:06:01 +0200 | [diff] [blame] | 751 | { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S}, |
| 752 | { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S}, |
| 753 | { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S}, |
| 754 | { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S}, |
| 755 | { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S}, |
James Ralston | 6e6680e | 2013-02-08 17:33:38 -0800 | [diff] [blame] | 756 | { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, |
| 757 | { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, |
| 758 | { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, |
| 759 | { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, |
| 760 | { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, |
| 761 | { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, |
| 762 | { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, |
| 763 | { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, |
| 764 | { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, |
| 765 | { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, |
| 766 | { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, |
| 767 | { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, |
| 768 | { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, |
| 769 | { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, |
| 770 | { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, |
| 771 | { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, |
| 772 | { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, |
| 773 | { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, |
| 774 | { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, |
| 775 | { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, |
| 776 | { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, |
| 777 | { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, |
| 778 | { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, |
| 779 | { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, |
| 780 | { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, |
| 781 | { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, |
| 782 | { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, |
| 783 | { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, |
| 784 | { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, |
| 785 | { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, |
| 786 | { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, |
| 787 | { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, |
Andy Shevchenko | aec9038 | 2015-03-27 20:06:01 +0200 | [diff] [blame] | 788 | { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, |
| 789 | { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, |
| 790 | { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, |
| 791 | { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, |
| 792 | { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, |
| 793 | { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, |
| 794 | { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, |
| 795 | { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, |
James Ralston | 5e90169 | 2013-11-04 09:31:20 -0800 | [diff] [blame] | 796 | { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, |
| 797 | { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, |
| 798 | { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP}, |
| 799 | { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP}, |
| 800 | { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP}, |
| 801 | { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP}, |
| 802 | { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP}, |
Alexandra Yates | 6223a30 | 2015-11-06 15:19:48 -0800 | [diff] [blame] | 803 | { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG}, |
| 804 | { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG}, |
| 805 | { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG}, |
| 806 | { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG}, |
| 807 | { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG}, |
| 808 | { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG}, |
| 809 | { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG}, |
| 810 | { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG}, |
| 811 | { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG}, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 812 | { 0, }, /* End of list */ |
| 813 | }; |
| 814 | MODULE_DEVICE_TABLE(pci, lpc_ich_ids); |
| 815 | |
| 816 | static void lpc_ich_restore_config_space(struct pci_dev *dev) |
| 817 | { |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 818 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
| 819 | |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 820 | if (priv->abase_save >= 0) { |
| 821 | pci_write_config_byte(dev, priv->abase, priv->abase_save); |
| 822 | priv->abase_save = -1; |
| 823 | } |
| 824 | |
| 825 | if (priv->actrl_pbase_save >= 0) { |
| 826 | pci_write_config_byte(dev, priv->actrl_pbase, |
| 827 | priv->actrl_pbase_save); |
| 828 | priv->actrl_pbase_save = -1; |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 829 | } |
| 830 | |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 831 | if (priv->gctrl_save >= 0) { |
| 832 | pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); |
| 833 | priv->gctrl_save = -1; |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 834 | } |
| 835 | } |
| 836 | |
Bill Pemberton | f791be4 | 2012-11-19 13:23:04 -0500 | [diff] [blame] | 837 | static void lpc_ich_enable_acpi_space(struct pci_dev *dev) |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 838 | { |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 839 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 840 | u8 reg_save; |
| 841 | |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 842 | switch (lpc_chipset_info[priv->chipset].iTCO_version) { |
| 843 | case 3: |
| 844 | /* |
| 845 | * Some chipsets (eg Avoton) enable the ACPI space in the |
| 846 | * ACPI BASE register. |
| 847 | */ |
| 848 | pci_read_config_byte(dev, priv->abase, ®_save); |
| 849 | pci_write_config_byte(dev, priv->abase, reg_save | 0x2); |
| 850 | priv->abase_save = reg_save; |
| 851 | break; |
| 852 | default: |
| 853 | /* |
| 854 | * Most chipsets enable the ACPI space in the ACPI control |
| 855 | * register. |
| 856 | */ |
| 857 | pci_read_config_byte(dev, priv->actrl_pbase, ®_save); |
| 858 | pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); |
| 859 | priv->actrl_pbase_save = reg_save; |
| 860 | break; |
| 861 | } |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 862 | } |
| 863 | |
Bill Pemberton | f791be4 | 2012-11-19 13:23:04 -0500 | [diff] [blame] | 864 | static void lpc_ich_enable_gpio_space(struct pci_dev *dev) |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 865 | { |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 866 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 867 | u8 reg_save; |
| 868 | |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 869 | pci_read_config_byte(dev, priv->gctrl, ®_save); |
| 870 | pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); |
| 871 | priv->gctrl_save = reg_save; |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 872 | } |
| 873 | |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 874 | static void lpc_ich_enable_pmc_space(struct pci_dev *dev) |
| 875 | { |
| 876 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
| 877 | u8 reg_save; |
| 878 | |
| 879 | pci_read_config_byte(dev, priv->actrl_pbase, ®_save); |
| 880 | pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); |
| 881 | |
| 882 | priv->actrl_pbase_save = reg_save; |
| 883 | } |
| 884 | |
Matt Fleming | 420b54d | 2015-08-06 13:46:24 +0100 | [diff] [blame] | 885 | static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev) |
| 886 | { |
| 887 | struct itco_wdt_platform_data *pdata; |
| 888 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
| 889 | struct lpc_ich_info *info; |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 890 | struct mfd_cell *cell = &lpc_ich_wdt_cell; |
Matt Fleming | 420b54d | 2015-08-06 13:46:24 +0100 | [diff] [blame] | 891 | |
| 892 | pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); |
| 893 | if (!pdata) |
| 894 | return -ENOMEM; |
| 895 | |
| 896 | info = &lpc_chipset_info[priv->chipset]; |
| 897 | |
| 898 | pdata->version = info->iTCO_version; |
| 899 | strlcpy(pdata->name, info->name, sizeof(pdata->name)); |
| 900 | |
| 901 | cell->platform_data = pdata; |
| 902 | cell->pdata_size = sizeof(*pdata); |
| 903 | return 0; |
| 904 | } |
| 905 | |
| 906 | static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev) |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 907 | { |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 908 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 909 | struct mfd_cell *cell = &lpc_ich_gpio_cell; |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 910 | |
| 911 | cell->platform_data = &lpc_chipset_info[priv->chipset]; |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 912 | cell->pdata_size = sizeof(struct lpc_ich_info); |
| 913 | } |
| 914 | |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 915 | /* |
| 916 | * We don't check for resource conflict globally. There are 2 or 3 independent |
| 917 | * GPIO groups and it's enough to have access to one of these to instantiate |
| 918 | * the device. |
| 919 | */ |
Bill Pemberton | f791be4 | 2012-11-19 13:23:04 -0500 | [diff] [blame] | 920 | static int lpc_ich_check_conflict_gpio(struct resource *res) |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 921 | { |
| 922 | int ret; |
| 923 | u8 use_gpio = 0; |
| 924 | |
| 925 | if (resource_size(res) >= 0x50 && |
| 926 | !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) |
| 927 | use_gpio |= 1 << 2; |
| 928 | |
| 929 | if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) |
| 930 | use_gpio |= 1 << 1; |
| 931 | |
| 932 | ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); |
| 933 | if (!ret) |
| 934 | use_gpio |= 1 << 0; |
| 935 | |
| 936 | return use_gpio ? use_gpio : ret; |
| 937 | } |
| 938 | |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 939 | static int lpc_ich_init_gpio(struct pci_dev *dev) |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 940 | { |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 941 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 942 | u32 base_addr_cfg; |
| 943 | u32 base_addr; |
| 944 | int ret; |
| 945 | bool acpi_conflict = false; |
| 946 | struct resource *res; |
| 947 | |
| 948 | /* Setup power management base register */ |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 949 | pci_read_config_dword(dev, priv->abase, &base_addr_cfg); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 950 | base_addr = base_addr_cfg & 0x0000ff80; |
| 951 | if (!base_addr) { |
Paul Bolle | 0c41884 | 2012-11-19 21:04:11 +0100 | [diff] [blame] | 952 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 953 | lpc_ich_gpio_cell.num_resources--; |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 954 | goto gpe0_done; |
| 955 | } |
| 956 | |
| 957 | res = &gpio_ich_res[ICH_RES_GPE0]; |
| 958 | res->start = base_addr + ACPIBASE_GPE_OFF; |
| 959 | res->end = base_addr + ACPIBASE_GPE_END; |
| 960 | ret = acpi_check_resource_conflict(res); |
| 961 | if (ret) { |
| 962 | /* |
| 963 | * This isn't fatal for the GPIO, but we have to make sure that |
| 964 | * the platform_device subsystem doesn't see this resource |
| 965 | * or it will register an invalid region. |
| 966 | */ |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 967 | lpc_ich_gpio_cell.num_resources--; |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 968 | acpi_conflict = true; |
| 969 | } else { |
| 970 | lpc_ich_enable_acpi_space(dev); |
| 971 | } |
| 972 | |
| 973 | gpe0_done: |
| 974 | /* Setup GPIO base register */ |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 975 | pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 976 | base_addr = base_addr_cfg & 0x0000ff80; |
| 977 | if (!base_addr) { |
Paul Bolle | 0c41884 | 2012-11-19 21:04:11 +0100 | [diff] [blame] | 978 | dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 979 | ret = -ENODEV; |
| 980 | goto gpio_done; |
| 981 | } |
| 982 | |
| 983 | /* Older devices provide fewer GPIO and have a smaller resource size. */ |
| 984 | res = &gpio_ich_res[ICH_RES_GPIO]; |
| 985 | res->start = base_addr; |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 986 | switch (lpc_chipset_info[priv->chipset].gpio_version) { |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 987 | case ICH_V5_GPIO: |
| 988 | case ICH_V10CORP_GPIO: |
| 989 | res->end = res->start + 128 - 1; |
| 990 | break; |
| 991 | default: |
| 992 | res->end = res->start + 64 - 1; |
| 993 | break; |
| 994 | } |
| 995 | |
Jean Delvare | 4f600ad | 2012-07-23 17:34:15 +0200 | [diff] [blame] | 996 | ret = lpc_ich_check_conflict_gpio(res); |
| 997 | if (ret < 0) { |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 998 | /* this isn't necessarily fatal for the GPIO */ |
| 999 | acpi_conflict = true; |
| 1000 | goto gpio_done; |
| 1001 | } |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1002 | lpc_chipset_info[priv->chipset].use_gpio = ret; |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1003 | lpc_ich_enable_gpio_space(dev); |
| 1004 | |
Matt Fleming | 420b54d | 2015-08-06 13:46:24 +0100 | [diff] [blame] | 1005 | lpc_ich_finalize_gpio_cell(dev); |
Mika Westerberg | 1abf25a | 2015-06-09 12:17:07 +0300 | [diff] [blame] | 1006 | ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 1007 | &lpc_ich_gpio_cell, 1, NULL, 0, NULL); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1008 | |
| 1009 | gpio_done: |
| 1010 | if (acpi_conflict) |
| 1011 | pr_warn("Resource conflict(s) found affecting %s\n", |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 1012 | lpc_ich_gpio_cell.name); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1013 | return ret; |
| 1014 | } |
| 1015 | |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1016 | static int lpc_ich_init_wdt(struct pci_dev *dev) |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1017 | { |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1018 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1019 | u32 base_addr_cfg; |
| 1020 | u32 base_addr; |
| 1021 | int ret; |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1022 | struct resource *res; |
| 1023 | |
Mika Westerberg | 3413f70 | 2016-09-20 15:30:52 +0300 | [diff] [blame] | 1024 | /* If we have ACPI based watchdog use that instead */ |
| 1025 | if (acpi_has_watchdog()) |
| 1026 | return -ENODEV; |
| 1027 | |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1028 | /* Setup power management base register */ |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 1029 | pci_read_config_dword(dev, priv->abase, &base_addr_cfg); |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1030 | base_addr = base_addr_cfg & 0x0000ff80; |
| 1031 | if (!base_addr) { |
Paul Bolle | 0c41884 | 2012-11-19 21:04:11 +0100 | [diff] [blame] | 1032 | dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1033 | ret = -ENODEV; |
| 1034 | goto wdt_done; |
| 1035 | } |
| 1036 | |
| 1037 | res = wdt_io_res(ICH_RES_IO_TCO); |
| 1038 | res->start = base_addr + ACPIBASE_TCO_OFF; |
| 1039 | res->end = base_addr + ACPIBASE_TCO_END; |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1040 | |
| 1041 | res = wdt_io_res(ICH_RES_IO_SMI); |
| 1042 | res->start = base_addr + ACPIBASE_SMI_OFF; |
| 1043 | res->end = base_addr + ACPIBASE_SMI_END; |
Feng Tang | 092369e | 2012-08-16 15:50:10 +0800 | [diff] [blame] | 1044 | |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1045 | lpc_ich_enable_acpi_space(dev); |
| 1046 | |
| 1047 | /* |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 1048 | * iTCO v2: |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1049 | * Get the Memory-Mapped GCS register. To get access to it |
| 1050 | * we have to read RCBA from PCI Config space 0xf0 and use |
| 1051 | * it as base. GCS = RCBA + ICH6_GCS(0x3410). |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 1052 | * |
| 1053 | * iTCO v3: |
| 1054 | * Get the Power Management Configuration register. To get access |
| 1055 | * to it we have to read the PMC BASE from config space and address |
| 1056 | * the register at offset 0x8. |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1057 | */ |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1058 | if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { |
Peter Hurley | e294bc9 | 2012-11-21 17:30:50 +0100 | [diff] [blame] | 1059 | /* Don't register iomem for TCO ver 1 */ |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 1060 | lpc_ich_wdt_cell.num_resources--; |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 1061 | } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1062 | pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); |
| 1063 | base_addr = base_addr_cfg & 0xffffc000; |
| 1064 | if (!(base_addr_cfg & 1)) { |
Paul Bolle | 0c41884 | 2012-11-19 21:04:11 +0100 | [diff] [blame] | 1065 | dev_notice(&dev->dev, "RCBA is disabled by " |
| 1066 | "hardware/BIOS, device disabled\n"); |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1067 | ret = -ENODEV; |
| 1068 | goto wdt_done; |
| 1069 | } |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 1070 | res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1071 | res->start = base_addr + ACPIBASE_GCS_OFF; |
| 1072 | res->end = base_addr + ACPIBASE_GCS_END; |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 1073 | } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { |
| 1074 | lpc_ich_enable_pmc_space(dev); |
| 1075 | pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg); |
| 1076 | base_addr = base_addr_cfg & 0xfffffe00; |
| 1077 | |
| 1078 | res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); |
| 1079 | res->start = base_addr + ACPIBASE_PMC_OFF; |
| 1080 | res->end = base_addr + ACPIBASE_PMC_END; |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1081 | } |
| 1082 | |
Matt Fleming | 420b54d | 2015-08-06 13:46:24 +0100 | [diff] [blame] | 1083 | ret = lpc_ich_finalize_wdt_cell(dev); |
| 1084 | if (ret) |
| 1085 | goto wdt_done; |
| 1086 | |
Mika Westerberg | 1abf25a | 2015-06-09 12:17:07 +0300 | [diff] [blame] | 1087 | ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, |
Aaron Sierra | 3dab794 | 2015-09-22 19:04:24 -0500 | [diff] [blame] | 1088 | &lpc_ich_wdt_cell, 1, NULL, 0, NULL); |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1089 | |
| 1090 | wdt_done: |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1091 | return ret; |
| 1092 | } |
| 1093 | |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 1094 | static int lpc_ich_init_spi(struct pci_dev *dev) |
| 1095 | { |
| 1096 | struct lpc_ich_priv *priv = pci_get_drvdata(dev); |
| 1097 | struct resource *res = &intel_spi_res[0]; |
| 1098 | struct intel_spi_boardinfo *info; |
| 1099 | u32 spi_base, rcba, bcr; |
| 1100 | |
| 1101 | info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); |
| 1102 | if (!info) |
| 1103 | return -ENOMEM; |
| 1104 | |
| 1105 | info->type = lpc_chipset_info[priv->chipset].spi_type; |
| 1106 | |
| 1107 | switch (info->type) { |
| 1108 | case INTEL_SPI_BYT: |
| 1109 | pci_read_config_dword(dev, SPIBASE_BYT, &spi_base); |
| 1110 | if (spi_base & SPIBASE_BYT_EN) { |
| 1111 | res->start = spi_base & ~(SPIBASE_BYT_SZ - 1); |
| 1112 | res->end = res->start + SPIBASE_BYT_SZ - 1; |
| 1113 | } |
| 1114 | break; |
| 1115 | |
| 1116 | case INTEL_SPI_LPT: |
| 1117 | pci_read_config_dword(dev, RCBABASE, &rcba); |
| 1118 | if (rcba & 1) { |
| 1119 | spi_base = round_down(rcba, SPIBASE_LPT_SZ); |
| 1120 | res->start = spi_base + SPIBASE_LPT; |
| 1121 | res->end = res->start + SPIBASE_LPT_SZ - 1; |
| 1122 | |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 1123 | pci_read_config_dword(dev, BCR, &bcr); |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 1124 | info->writeable = !!(bcr & BCR_WPD); |
| 1125 | } |
| 1126 | break; |
| 1127 | |
Mika Westerberg | 87eb832 | 2016-11-28 15:06:26 +0300 | [diff] [blame] | 1128 | case INTEL_SPI_BXT: { |
| 1129 | unsigned int p2sb = PCI_DEVFN(13, 0); |
| 1130 | unsigned int spi = PCI_DEVFN(13, 2); |
| 1131 | struct pci_bus *bus = dev->bus; |
| 1132 | |
| 1133 | /* |
| 1134 | * The P2SB is hidden by BIOS and we need to unhide it in |
| 1135 | * order to read BAR of the SPI flash device. Once that is |
| 1136 | * done we hide it again. |
| 1137 | */ |
| 1138 | pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0); |
| 1139 | pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0, |
| 1140 | &spi_base); |
| 1141 | if (spi_base != ~0) { |
| 1142 | res->start = spi_base & 0xfffffff0; |
| 1143 | res->end = res->start + SPIBASE_APL_SZ - 1; |
| 1144 | |
| 1145 | pci_bus_read_config_dword(bus, spi, BCR, &bcr); |
| 1146 | if (!(bcr & BCR_WPD)) { |
| 1147 | bcr |= BCR_WPD; |
| 1148 | pci_bus_write_config_dword(bus, spi, BCR, bcr); |
| 1149 | pci_bus_read_config_dword(bus, spi, BCR, &bcr); |
| 1150 | } |
| 1151 | info->writeable = !!(bcr & BCR_WPD); |
| 1152 | } |
| 1153 | |
| 1154 | pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1); |
| 1155 | break; |
| 1156 | } |
| 1157 | |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 1158 | default: |
| 1159 | return -EINVAL; |
| 1160 | } |
| 1161 | |
| 1162 | if (!res->start) |
| 1163 | return -ENODEV; |
| 1164 | |
| 1165 | lpc_ich_spi_cell.platform_data = info; |
| 1166 | lpc_ich_spi_cell.pdata_size = sizeof(*info); |
| 1167 | |
| 1168 | return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE, |
| 1169 | &lpc_ich_spi_cell, 1, NULL, 0, NULL); |
| 1170 | } |
| 1171 | |
Bill Pemberton | f791be4 | 2012-11-19 13:23:04 -0500 | [diff] [blame] | 1172 | static int lpc_ich_probe(struct pci_dev *dev, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1173 | const struct pci_device_id *id) |
| 1174 | { |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1175 | struct lpc_ich_priv *priv; |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1176 | int ret; |
| 1177 | bool cell_added = false; |
| 1178 | |
Aaron Sierra | ff7109f | 2013-02-14 11:35:04 -0600 | [diff] [blame] | 1179 | priv = devm_kzalloc(&dev->dev, |
| 1180 | sizeof(struct lpc_ich_priv), GFP_KERNEL); |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1181 | if (!priv) |
| 1182 | return -ENOMEM; |
| 1183 | |
| 1184 | priv->chipset = id->driver_data; |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1185 | |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 1186 | priv->actrl_pbase_save = -1; |
| 1187 | priv->abase_save = -1; |
| 1188 | |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 1189 | priv->abase = ACPIBASE; |
Peter Tyser | eb71d4d | 2014-03-10 16:34:54 -0500 | [diff] [blame] | 1190 | priv->actrl_pbase = ACPICTRL_PMCBASE; |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 1191 | |
| 1192 | priv->gctrl_save = -1; |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1193 | if (priv->chipset <= LPC_ICH5) { |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 1194 | priv->gbase = GPIOBASE_ICH0; |
| 1195 | priv->gctrl = GPIOCTRL_ICH0; |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1196 | } else { |
Peter Tyser | 429b941 | 2014-03-10 16:34:53 -0500 | [diff] [blame] | 1197 | priv->gbase = GPIOBASE_ICH6; |
| 1198 | priv->gctrl = GPIOCTRL_ICH6; |
Aaron Sierra | 01560f6 | 2013-01-24 14:52:39 -0600 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | pci_set_drvdata(dev, priv); |
| 1202 | |
Peter Tyser | f0776b8 | 2014-03-10 16:34:52 -0500 | [diff] [blame] | 1203 | if (lpc_chipset_info[priv->chipset].iTCO_version) { |
| 1204 | ret = lpc_ich_init_wdt(dev); |
| 1205 | if (!ret) |
| 1206 | cell_added = true; |
| 1207 | } |
Aaron Sierra | 887c8ec | 2012-04-20 14:14:11 -0500 | [diff] [blame] | 1208 | |
Peter Tyser | f0776b8 | 2014-03-10 16:34:52 -0500 | [diff] [blame] | 1209 | if (lpc_chipset_info[priv->chipset].gpio_version) { |
| 1210 | ret = lpc_ich_init_gpio(dev); |
| 1211 | if (!ret) |
| 1212 | cell_added = true; |
| 1213 | } |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1214 | |
Mika Westerberg | ff00d7a | 2016-11-28 15:06:25 +0300 | [diff] [blame] | 1215 | if (lpc_chipset_info[priv->chipset].spi_type) { |
| 1216 | ret = lpc_ich_init_spi(dev); |
| 1217 | if (!ret) |
| 1218 | cell_added = true; |
| 1219 | } |
| 1220 | |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1221 | /* |
| 1222 | * We only care if at least one or none of the cells registered |
| 1223 | * successfully. |
| 1224 | */ |
| 1225 | if (!cell_added) { |
Paul Bolle | 0c41884 | 2012-11-19 21:04:11 +0100 | [diff] [blame] | 1226 | dev_warn(&dev->dev, "No MFD cells added\n"); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1227 | lpc_ich_restore_config_space(dev); |
| 1228 | return -ENODEV; |
| 1229 | } |
| 1230 | |
| 1231 | return 0; |
| 1232 | } |
| 1233 | |
Bill Pemberton | 4740f73 | 2012-11-19 13:26:01 -0500 | [diff] [blame] | 1234 | static void lpc_ich_remove(struct pci_dev *dev) |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1235 | { |
| 1236 | mfd_remove_devices(&dev->dev); |
| 1237 | lpc_ich_restore_config_space(dev); |
| 1238 | } |
| 1239 | |
| 1240 | static struct pci_driver lpc_ich_driver = { |
| 1241 | .name = "lpc_ich", |
| 1242 | .id_table = lpc_ich_ids, |
| 1243 | .probe = lpc_ich_probe, |
Bill Pemberton | 8444921 | 2012-11-19 13:20:24 -0500 | [diff] [blame] | 1244 | .remove = lpc_ich_remove, |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1245 | }; |
| 1246 | |
Libo Chen | b4d0fe9 | 2013-05-27 10:28:56 +0800 | [diff] [blame] | 1247 | module_pci_driver(lpc_ich_driver); |
Aaron Sierra | 4630b13 | 2012-03-28 09:43:10 -0500 | [diff] [blame] | 1248 | |
| 1249 | MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>"); |
| 1250 | MODULE_DESCRIPTION("LPC interface for Intel ICH"); |
| 1251 | MODULE_LICENSE("GPL"); |