blob: a22180803bd7dd2b03f13f54e3843e2ad820b337 [file] [log] [blame]
Fabio Estevam19ad2b72018-07-09 14:55:58 -03001// SPDX-License-Identifier: GPL-2.0+
Shawn Guo4dce82c2012-04-04 10:50:52 +08002/*
3 * Copyright 2012 Freescale Semiconductor, Inc.
Shawn Guo4dce82c2012-04-04 10:50:52 +08004 */
5
6#include <linux/clk.h>
7#include <linux/err.h>
8#include <linux/io.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
Shawn Guo4dce82c2012-04-04 10:50:52 +080012#include <linux/platform_device.h>
13#include <linux/pwm.h>
14#include <linux/slab.h>
Shawn Guo01bf32e2012-06-26 16:58:09 +080015#include <linux/stmp_device.h>
Shawn Guo4dce82c2012-04-04 10:50:52 +080016
17#define SET 0x4
18#define CLR 0x8
19#define TOG 0xc
20
21#define PWM_CTRL 0x0
22#define PWM_ACTIVE0 0x10
23#define PWM_PERIOD0 0x20
24#define PERIOD_PERIOD(p) ((p) & 0xffff)
25#define PERIOD_PERIOD_MAX 0x10000
26#define PERIOD_ACTIVE_HIGH (3 << 16)
Rasmus Villemoes2cf0f6f2019-10-04 15:32:04 +020027#define PERIOD_ACTIVE_LOW (2 << 16)
28#define PERIOD_INACTIVE_HIGH (3 << 18)
Shawn Guo4dce82c2012-04-04 10:50:52 +080029#define PERIOD_INACTIVE_LOW (2 << 18)
Rasmus Villemoesbf29c2f2019-10-04 15:32:02 +020030#define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW)
Rasmus Villemoes2cf0f6f2019-10-04 15:32:04 +020031#define PERIOD_POLARITY_INVERSE (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH)
Shawn Guo4dce82c2012-04-04 10:50:52 +080032#define PERIOD_CDIV(div) (((div) & 0x7) << 20)
33#define PERIOD_CDIV_MAX 8
34
Rasmus Villemoes3c64ed72019-10-04 15:32:06 +020035static const u8 cdiv_shift[PERIOD_CDIV_MAX] = {
36 0, 1, 2, 3, 4, 6, 8, 10
Gaetan Hug24ccea12015-03-11 13:08:12 +010037};
38
Shawn Guo4dce82c2012-04-04 10:50:52 +080039struct mxs_pwm_chip {
40 struct pwm_chip chip;
Shawn Guo4dce82c2012-04-04 10:50:52 +080041 struct clk *clk;
42 void __iomem *base;
43};
44
45#define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip)
46
Rasmus Villemoesbf29c2f2019-10-04 15:32:02 +020047static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
48 const struct pwm_state *state)
49{
50 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip);
51 int ret, div = 0;
52 unsigned int period_cycles, duty_cycles;
53 unsigned long rate;
54 unsigned long long c;
Rasmus Villemoes2cf0f6f2019-10-04 15:32:04 +020055 unsigned int pol_bits;
Rasmus Villemoesbf29c2f2019-10-04 15:32:02 +020056
57 /*
58 * If the PWM channel is disabled, make sure to turn on the
59 * clock before calling clk_get_rate() and writing to the
60 * registers. Otherwise, just keep it enabled.
61 */
62 if (!pwm_is_enabled(pwm)) {
63 ret = clk_prepare_enable(mxs->clk);
64 if (ret)
65 return ret;
66 }
67
68 if (!state->enabled && pwm_is_enabled(pwm))
69 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR);
70
71 rate = clk_get_rate(mxs->clk);
72 while (1) {
Rasmus Villemoes3c64ed72019-10-04 15:32:06 +020073 c = rate >> cdiv_shift[div];
Rasmus Villemoesbf29c2f2019-10-04 15:32:02 +020074 c = c * state->period;
75 do_div(c, 1000000000);
76 if (c < PERIOD_PERIOD_MAX)
77 break;
78 div++;
79 if (div >= PERIOD_CDIV_MAX)
80 return -EINVAL;
81 }
82
83 period_cycles = c;
84 c *= state->duty_cycle;
85 do_div(c, state->period);
86 duty_cycles = c;
87
88 /*
89 * The data sheet the says registers must be written to in
90 * this order (ACTIVEn, then PERIODn). Also, the new settings
91 * only take effect at the beginning of a new period, avoiding
92 * glitches.
93 */
Rasmus Villemoes2cf0f6f2019-10-04 15:32:04 +020094
95 pol_bits = state->polarity == PWM_POLARITY_NORMAL ?
96 PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE;
Rasmus Villemoesbf29c2f2019-10-04 15:32:02 +020097 writel(duty_cycles << 16,
98 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20);
Rasmus Villemoes2cf0f6f2019-10-04 15:32:04 +020099 writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div),
Rasmus Villemoesbf29c2f2019-10-04 15:32:02 +0200100 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20);
101
102 if (state->enabled) {
103 if (!pwm_is_enabled(pwm)) {
104 /*
105 * The clock was enabled above. Just enable
106 * the channel in the control register.
107 */
108 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET);
109 }
110 } else {
111 clk_disable_unprepare(mxs->clk);
112 }
113 return 0;
114}
115
Shawn Guo4dce82c2012-04-04 10:50:52 +0800116static const struct pwm_ops mxs_pwm_ops = {
Rasmus Villemoesbf29c2f2019-10-04 15:32:02 +0200117 .apply = mxs_pwm_apply,
Shawn Guo4dce82c2012-04-04 10:50:52 +0800118 .owner = THIS_MODULE,
119};
120
121static int mxs_pwm_probe(struct platform_device *pdev)
122{
123 struct device_node *np = pdev->dev.of_node;
124 struct mxs_pwm_chip *mxs;
125 int ret;
126
127 mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL);
128 if (!mxs)
129 return -ENOMEM;
130
Anson Huanga3156142019-07-18 09:32:05 +0800131 mxs->base = devm_platform_ioremap_resource(pdev, 0);
Thierry Reding6d4294d2013-01-21 11:09:16 +0100132 if (IS_ERR(mxs->base))
133 return PTR_ERR(mxs->base);
Shawn Guo4dce82c2012-04-04 10:50:52 +0800134
Shawn Guo22d260b2012-06-26 16:58:10 +0800135 mxs->clk = devm_clk_get(&pdev->dev, NULL);
136 if (IS_ERR(mxs->clk))
137 return PTR_ERR(mxs->clk);
Shawn Guo4dce82c2012-04-04 10:50:52 +0800138
139 mxs->chip.dev = &pdev->dev;
140 mxs->chip.ops = &mxs_pwm_ops;
Thierry Reding8c0216f2017-01-04 09:40:54 +0100141
Shawn Guo4dce82c2012-04-04 10:50:52 +0800142 ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
143 if (ret < 0) {
144 dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
Shawn Guo22d260b2012-06-26 16:58:10 +0800145 return ret;
Shawn Guo4dce82c2012-04-04 10:50:52 +0800146 }
147
148 ret = pwmchip_add(&mxs->chip);
149 if (ret < 0) {
150 dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret);
Shawn Guo22d260b2012-06-26 16:58:10 +0800151 return ret;
Shawn Guo4dce82c2012-04-04 10:50:52 +0800152 }
153
Shawn Guo4dce82c2012-04-04 10:50:52 +0800154 platform_set_drvdata(pdev, mxs);
155
Fabio Estevamcfb9e4c2013-07-09 23:25:37 -0300156 ret = stmp_reset_block(mxs->base);
157 if (ret)
158 goto pwm_remove;
Shawn Guo4dce82c2012-04-04 10:50:52 +0800159
160 return 0;
Fabio Estevamcfb9e4c2013-07-09 23:25:37 -0300161
162pwm_remove:
163 pwmchip_remove(&mxs->chip);
164 return ret;
Shawn Guo4dce82c2012-04-04 10:50:52 +0800165}
166
Bill Pemberton77f37912012-11-19 13:26:09 -0500167static int mxs_pwm_remove(struct platform_device *pdev)
Shawn Guo4dce82c2012-04-04 10:50:52 +0800168{
169 struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev);
170
Axel Lin457fd762012-07-01 12:58:00 +0800171 return pwmchip_remove(&mxs->chip);
Shawn Guo4dce82c2012-04-04 10:50:52 +0800172}
173
Thierry Redingf1a88702013-04-18 10:04:14 +0200174static const struct of_device_id mxs_pwm_dt_ids[] = {
Shawn Guo071407e2012-06-26 16:58:08 +0800175 { .compatible = "fsl,imx23-pwm", },
Shawn Guo4dce82c2012-04-04 10:50:52 +0800176 { /* sentinel */ }
177};
178MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids);
179
180static struct platform_driver mxs_pwm_driver = {
181 .driver = {
182 .name = "mxs-pwm",
Sachin Kamatde02cb82013-09-30 08:56:39 +0530183 .of_match_table = mxs_pwm_dt_ids,
Shawn Guo4dce82c2012-04-04 10:50:52 +0800184 },
185 .probe = mxs_pwm_probe,
Bill Pembertonfd109112012-11-19 13:21:28 -0500186 .remove = mxs_pwm_remove,
Shawn Guo4dce82c2012-04-04 10:50:52 +0800187};
188module_platform_driver(mxs_pwm_driver);
189
190MODULE_ALIAS("platform:mxs-pwm");
191MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
192MODULE_DESCRIPTION("Freescale MXS PWM Driver");
193MODULE_LICENSE("GPL v2");