Nobuhiro Iwamatsu | a68a784 | 2020-09-10 05:43:30 +0900 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2020 TOSHIBA CORPORATION |
| 4 | * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation |
| 5 | * Copyright (c) 2020 Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> |
| 6 | */ |
| 7 | |
| 8 | #include <linux/init.h> |
| 9 | #include <linux/io.h> |
| 10 | #include <linux/of.h> |
| 11 | #include <linux/platform_device.h> |
| 12 | #include <linux/pinctrl/pinctrl.h> |
| 13 | #include "pinctrl-common.h" |
| 14 | |
| 15 | #define tmpv7700_MAGIC_NUM 0x4932f70e |
| 16 | |
| 17 | /* register offset */ |
| 18 | #define REG_KEY_CTRL 0x0000 |
| 19 | #define REG_KEY_CMD 0x0004 |
| 20 | #define REG_PINMUX1 0x3000 |
| 21 | #define REG_PINMUX2 0x3004 |
| 22 | #define REG_PINMUX3 0x3008 |
| 23 | #define REG_PINMUX4 0x300c |
| 24 | #define REG_PINMUX5 0x3010 |
| 25 | #define REG_IOSET 0x3014 |
| 26 | #define REG_IO_VSEL 0x3018 |
| 27 | #define REG_IO_DSEL1 0x301c |
| 28 | #define REG_IO_DSEL2 0x3020 |
| 29 | #define REG_IO_DSEL3 0x3024 |
| 30 | #define REG_IO_DSEL4 0x3028 |
| 31 | #define REG_IO_DSEL5 0x302c |
| 32 | #define REG_IO_DSEL6 0x3030 |
| 33 | #define REG_IO_DSEL7 0x3034 |
| 34 | #define REG_IO_DSEL8 0x3038 |
| 35 | #define REG_IO_PUDE1 0x303c |
| 36 | #define REG_IO_PUDE2 0x3040 |
| 37 | #define REG_IO_PUDSEL1 0x3044 |
| 38 | #define REG_IO_PUDSEL2 0x3048 |
| 39 | |
| 40 | /* PIN */ |
| 41 | static const struct visconti_desc_pin pins_tmpv7700[] = { |
| 42 | VISCONTI_PIN(PINCTRL_PIN(0, "gpio0"), REG_IO_DSEL4, 24, |
| 43 | REG_IO_PUDE1, REG_IO_PUDSEL1, 30), |
| 44 | VISCONTI_PIN(PINCTRL_PIN(1, "gpio1"), REG_IO_DSEL4, 28, |
| 45 | REG_IO_PUDE1, REG_IO_PUDSEL1, 31), |
| 46 | VISCONTI_PIN(PINCTRL_PIN(2, "gpio2"), REG_IO_DSEL5, 0, |
| 47 | REG_IO_PUDE2, REG_IO_PUDSEL2, 0), |
| 48 | VISCONTI_PIN(PINCTRL_PIN(3, "gpio3"), REG_IO_DSEL5, 4, |
| 49 | REG_IO_PUDE2, REG_IO_PUDSEL2, 1), |
| 50 | VISCONTI_PIN(PINCTRL_PIN(4, "gpio4"), REG_IO_DSEL5, 8, |
| 51 | REG_IO_PUDE2, REG_IO_PUDSEL2, 2), |
| 52 | VISCONTI_PIN(PINCTRL_PIN(5, "gpio5"), REG_IO_DSEL5, 12, |
| 53 | REG_IO_PUDE2, REG_IO_PUDSEL2, 3), |
| 54 | VISCONTI_PIN(PINCTRL_PIN(6, "gpio6"), REG_IO_DSEL5, 16, |
| 55 | REG_IO_PUDE2, REG_IO_PUDSEL2, 4), |
| 56 | VISCONTI_PIN(PINCTRL_PIN(7, "gpio7"), REG_IO_DSEL5, 20, |
| 57 | REG_IO_PUDE2, REG_IO_PUDSEL2, 5), |
| 58 | VISCONTI_PIN(PINCTRL_PIN(8, "gpio8"), REG_IO_DSEL5, 24, |
| 59 | REG_IO_PUDE2, REG_IO_PUDSEL2, 6), |
| 60 | VISCONTI_PIN(PINCTRL_PIN(9, "gpio9"), REG_IO_DSEL5, 28, |
| 61 | REG_IO_PUDE2, REG_IO_PUDSEL2, 7), |
| 62 | VISCONTI_PIN(PINCTRL_PIN(10, "gpio10"), REG_IO_DSEL6, 0, |
| 63 | REG_IO_PUDE2, REG_IO_PUDSEL2, 8), |
| 64 | VISCONTI_PIN(PINCTRL_PIN(11, "gpio11"), REG_IO_DSEL6, 4, |
| 65 | REG_IO_PUDE2, REG_IO_PUDSEL2, 9), |
| 66 | VISCONTI_PIN(PINCTRL_PIN(12, "gpio12"), REG_IO_DSEL6, 8, |
| 67 | REG_IO_PUDE2, REG_IO_PUDSEL2, 10), |
| 68 | VISCONTI_PIN(PINCTRL_PIN(13, "gpio13"), REG_IO_DSEL6, 12, |
| 69 | REG_IO_PUDE2, REG_IO_PUDSEL2, 11), |
| 70 | VISCONTI_PIN(PINCTRL_PIN(14, "gpio14"), REG_IO_DSEL6, 16, |
| 71 | REG_IO_PUDE2, REG_IO_PUDSEL2, 12), |
| 72 | VISCONTI_PIN(PINCTRL_PIN(15, "gpio15"), REG_IO_DSEL6, 20, |
| 73 | REG_IO_PUDE2, REG_IO_PUDSEL2, 13), |
| 74 | VISCONTI_PIN(PINCTRL_PIN(16, "gpio16"), REG_IO_DSEL6, 24, |
| 75 | REG_IO_PUDE2, REG_IO_PUDSEL2, 14), |
| 76 | VISCONTI_PIN(PINCTRL_PIN(17, "gpio17"), REG_IO_DSEL6, 28, |
| 77 | REG_IO_PUDE2, REG_IO_PUDSEL2, 15), |
| 78 | VISCONTI_PIN(PINCTRL_PIN(18, "gpio18"), REG_IO_DSEL7, 0, |
| 79 | REG_IO_PUDE2, REG_IO_PUDSEL2, 16), |
| 80 | VISCONTI_PIN(PINCTRL_PIN(19, "gpio19"), REG_IO_DSEL7, 4, |
| 81 | REG_IO_PUDE2, REG_IO_PUDSEL2, 17), |
| 82 | VISCONTI_PIN(PINCTRL_PIN(20, "gpio20"), REG_IO_DSEL7, 8, |
| 83 | REG_IO_PUDE2, REG_IO_PUDSEL2, 18), |
| 84 | VISCONTI_PIN(PINCTRL_PIN(21, "gpio21"), REG_IO_DSEL7, 12, |
| 85 | REG_IO_PUDE2, REG_IO_PUDSEL2, 19), |
| 86 | VISCONTI_PIN(PINCTRL_PIN(22, "gpio22"), REG_IO_DSEL7, 16, |
| 87 | REG_IO_PUDE2, REG_IO_PUDSEL2, 20), |
| 88 | VISCONTI_PIN(PINCTRL_PIN(23, "gpio23"), REG_IO_DSEL7, 20, |
| 89 | REG_IO_PUDE2, REG_IO_PUDSEL2, 21), |
| 90 | VISCONTI_PIN(PINCTRL_PIN(24, "gpio24"), REG_IO_DSEL7, 24, |
| 91 | REG_IO_PUDE2, REG_IO_PUDSEL2, 22), |
| 92 | VISCONTI_PIN(PINCTRL_PIN(25, "gpio25"), REG_IO_DSEL7, 28, |
| 93 | REG_IO_PUDE2, REG_IO_PUDSEL2, 23), |
| 94 | VISCONTI_PIN(PINCTRL_PIN(26, "gpio26"), REG_IO_DSEL8, 0, |
| 95 | REG_IO_PUDE2, REG_IO_PUDSEL2, 24), |
| 96 | VISCONTI_PIN(PINCTRL_PIN(27, "gpio27"), REG_IO_DSEL8, 4, |
| 97 | REG_IO_PUDE2, REG_IO_PUDSEL2, 25), |
| 98 | VISCONTI_PIN(PINCTRL_PIN(28, "gpio28"), REG_IO_DSEL8, 8, |
| 99 | REG_IO_PUDE2, REG_IO_PUDSEL2, 26), |
| 100 | VISCONTI_PIN(PINCTRL_PIN(29, "gpio29"), REG_IO_DSEL4, 8, |
| 101 | REG_IO_PUDE1, REG_IO_PUDSEL1, 26), |
| 102 | VISCONTI_PIN(PINCTRL_PIN(30, "gpio30"), REG_IO_DSEL4, 4, |
| 103 | REG_IO_PUDE1, REG_IO_PUDSEL1, 25), |
| 104 | VISCONTI_PIN(PINCTRL_PIN(31, "gpio31"), REG_IO_DSEL4, 0, |
| 105 | REG_IO_PUDE1, REG_IO_PUDSEL1, 24), |
| 106 | VISCONTI_PIN(PINCTRL_PIN(32, "spi_sck"), REG_IO_DSEL4, 12, |
| 107 | REG_IO_PUDE1, REG_IO_PUDSEL1, 27), |
| 108 | VISCONTI_PIN(PINCTRL_PIN(33, "spi_sdo"), REG_IO_DSEL4, 16, |
| 109 | REG_IO_PUDE1, REG_IO_PUDSEL1, 28), |
| 110 | VISCONTI_PIN(PINCTRL_PIN(34, "spi_sdi"), REG_IO_DSEL4, 20, |
| 111 | REG_IO_PUDE1, REG_IO_PUDSEL1, 29), |
| 112 | }; |
| 113 | |
| 114 | /* Group */ |
| 115 | VISCONTI_PINS(i2c0, 0, 1); |
| 116 | VISCONTI_PINS(i2c1, 2, 3); |
| 117 | VISCONTI_PINS(i2c2, 12, 13); |
| 118 | VISCONTI_PINS(i2c3, 14, 15); |
| 119 | VISCONTI_PINS(i2c4, 16, 17); |
| 120 | VISCONTI_PINS(i2c5, 18, 19); |
| 121 | VISCONTI_PINS(i2c6, 33, 34); |
| 122 | VISCONTI_PINS(i2c7, 29, 32); |
| 123 | VISCONTI_PINS(i2c8, 30, 31); |
| 124 | VISCONTI_PINS(spi0_cs0, 29); |
| 125 | VISCONTI_PINS(spi0_cs1, 30); |
| 126 | VISCONTI_PINS(spi0_cs2, 31); |
| 127 | VISCONTI_PINS(spi1_cs, 3); |
| 128 | VISCONTI_PINS(spi2_cs, 7); |
| 129 | VISCONTI_PINS(spi3_cs, 11); |
| 130 | VISCONTI_PINS(spi4_cs, 15); |
| 131 | VISCONTI_PINS(spi5_cs, 19); |
| 132 | VISCONTI_PINS(spi6_cs, 27); |
| 133 | VISCONTI_PINS(spi0, 32, 33, 34); |
| 134 | VISCONTI_PINS(spi1, 0, 1, 2); |
| 135 | VISCONTI_PINS(spi2, 4, 5, 6); |
| 136 | VISCONTI_PINS(spi3, 8, 9, 10); |
| 137 | VISCONTI_PINS(spi4, 12, 13, 14); |
| 138 | VISCONTI_PINS(spi5, 16, 17, 18); |
| 139 | VISCONTI_PINS(spi6, 24, 25, 26); |
| 140 | VISCONTI_PINS(uart0, 4, 5, 6, 7); |
| 141 | VISCONTI_PINS(uart1, 8, 9, 10, 11); |
| 142 | VISCONTI_PINS(uart2, 12, 13, 14, 15); |
| 143 | VISCONTI_PINS(uart3, 16, 17, 18, 19); |
| 144 | VISCONTI_PINS(pwm0_gpio4, 4); |
| 145 | VISCONTI_PINS(pwm1_gpio5, 5); |
| 146 | VISCONTI_PINS(pwm2_gpio6, 6); |
| 147 | VISCONTI_PINS(pwm3_gpio7, 7); |
| 148 | VISCONTI_PINS(pwm0_gpio8, 8); |
| 149 | VISCONTI_PINS(pwm1_gpio9, 9); |
| 150 | VISCONTI_PINS(pwm2_gpio10, 10); |
| 151 | VISCONTI_PINS(pwm3_gpio11, 11); |
| 152 | VISCONTI_PINS(pwm0_gpio12, 12); |
| 153 | VISCONTI_PINS(pwm1_gpio13, 13); |
| 154 | VISCONTI_PINS(pwm2_gpio14, 14); |
| 155 | VISCONTI_PINS(pwm3_gpio15, 15); |
| 156 | VISCONTI_PINS(pwm0_gpio16, 16); |
| 157 | VISCONTI_PINS(pwm1_gpio17, 17); |
| 158 | VISCONTI_PINS(pwm2_gpio18, 18); |
| 159 | VISCONTI_PINS(pwm3_gpio19, 19); |
| 160 | VISCONTI_PINS(pcmif_out, 20, 21, 22); |
| 161 | VISCONTI_PINS(pcmif_in, 24, 25, 26); |
| 162 | |
| 163 | static const struct visconti_pin_group groups_tmpv7700[] = { |
| 164 | VISCONTI_PIN_GROUP(i2c0, REG_PINMUX2, GENMASK(7, 0), 0x00000022), |
| 165 | VISCONTI_PIN_GROUP(i2c1, REG_PINMUX2, GENMASK(15, 8), 0x00002200), |
| 166 | VISCONTI_PIN_GROUP(i2c2, REG_PINMUX3, GENMASK(23, 16), 0x00770000), |
| 167 | VISCONTI_PIN_GROUP(i2c3, REG_PINMUX3, GENMASK(31, 24), 0x77000000), |
| 168 | VISCONTI_PIN_GROUP(i2c4, REG_PINMUX4, GENMASK(7, 0), 0x00000077), |
| 169 | VISCONTI_PIN_GROUP(i2c5, REG_PINMUX4, GENMASK(15, 8), 0x00007700), |
| 170 | VISCONTI_PIN_GROUP(i2c6, REG_PINMUX1, GENMASK(3, 0), 0x0000002), |
| 171 | VISCONTI_PIN_GROUP(i2c7, REG_PINMUX5, GENMASK(23, 20), 0x00200000), |
| 172 | VISCONTI_PIN_GROUP(i2c8, REG_PINMUX5, GENMASK(31, 24), 0x22000000), |
| 173 | VISCONTI_PIN_GROUP(spi0_cs0, REG_PINMUX5, GENMASK(23, 20), 0x00100000), |
| 174 | VISCONTI_PIN_GROUP(spi0_cs1, REG_PINMUX5, GENMASK(27, 24), 0x01000000), |
| 175 | VISCONTI_PIN_GROUP(spi0_cs2, REG_PINMUX5, GENMASK(31, 28), 0x10000000), |
| 176 | VISCONTI_PIN_GROUP(spi1_cs, REG_PINMUX2, GENMASK(15, 12), 0x00001000), |
| 177 | VISCONTI_PIN_GROUP(spi2_cs, REG_PINMUX2, GENMASK(31, 28), 0x10000000), |
| 178 | VISCONTI_PIN_GROUP(spi3_cs, REG_PINMUX3, GENMASK(15, 12), 0x00001000), |
| 179 | VISCONTI_PIN_GROUP(spi4_cs, REG_PINMUX4, GENMASK(31, 28), 0x10000000), |
| 180 | VISCONTI_PIN_GROUP(spi5_cs, REG_PINMUX4, GENMASK(15, 12), 0x00001000), |
| 181 | VISCONTI_PIN_GROUP(spi6_cs, REG_PINMUX5, GENMASK(15, 12), 0x00001000), |
| 182 | VISCONTI_PIN_GROUP(spi0, REG_PINMUX1, GENMASK(3, 0), 0x00000001), |
| 183 | VISCONTI_PIN_GROUP(spi1, REG_PINMUX2, GENMASK(11, 0), 0x00000111), |
| 184 | VISCONTI_PIN_GROUP(spi2, REG_PINMUX2, GENMASK(27, 16), 0x01110000), |
| 185 | VISCONTI_PIN_GROUP(spi3, REG_PINMUX3, GENMASK(11, 0), 0x00000111), |
| 186 | VISCONTI_PIN_GROUP(spi4, REG_PINMUX3, GENMASK(27, 16), 0x01110000), |
| 187 | VISCONTI_PIN_GROUP(spi5, REG_PINMUX4, GENMASK(11, 0), 0x00000111), |
| 188 | VISCONTI_PIN_GROUP(spi6, REG_PINMUX5, GENMASK(11, 0), 0x00000111), |
| 189 | VISCONTI_PIN_GROUP(uart0, REG_PINMUX2, GENMASK(31, 16), 0x22220000), |
| 190 | VISCONTI_PIN_GROUP(uart1, REG_PINMUX3, GENMASK(15, 0), 0x00002222), |
| 191 | VISCONTI_PIN_GROUP(uart2, REG_PINMUX3, GENMASK(31, 16), 0x22220000), |
| 192 | VISCONTI_PIN_GROUP(uart3, REG_PINMUX4, GENMASK(15, 0), 0x00002222), |
| 193 | VISCONTI_PIN_GROUP(pwm0_gpio4, REG_PINMUX2, GENMASK(19, 16), 0x00050000), |
| 194 | VISCONTI_PIN_GROUP(pwm1_gpio5, REG_PINMUX2, GENMASK(23, 20), 0x00500000), |
| 195 | VISCONTI_PIN_GROUP(pwm2_gpio6, REG_PINMUX2, GENMASK(27, 24), 0x05000000), |
| 196 | VISCONTI_PIN_GROUP(pwm3_gpio7, REG_PINMUX2, GENMASK(31, 28), 0x50000000), |
| 197 | VISCONTI_PIN_GROUP(pwm0_gpio8, REG_PINMUX3, GENMASK(3, 0), 0x00000005), |
| 198 | VISCONTI_PIN_GROUP(pwm1_gpio9, REG_PINMUX3, GENMASK(7, 4), 0x00000050), |
| 199 | VISCONTI_PIN_GROUP(pwm2_gpio10, REG_PINMUX3, GENMASK(11, 8), 0x00000500), |
| 200 | VISCONTI_PIN_GROUP(pwm3_gpio11, REG_PINMUX3, GENMASK(15, 12), 0x00005000), |
| 201 | VISCONTI_PIN_GROUP(pwm0_gpio12, REG_PINMUX3, GENMASK(19, 16), 0x00050000), |
| 202 | VISCONTI_PIN_GROUP(pwm1_gpio13, REG_PINMUX3, GENMASK(23, 20), 0x00500000), |
| 203 | VISCONTI_PIN_GROUP(pwm2_gpio14, REG_PINMUX3, GENMASK(27, 24), 0x05000000), |
| 204 | VISCONTI_PIN_GROUP(pwm3_gpio15, REG_PINMUX3, GENMASK(31, 28), 0x50000000), |
| 205 | VISCONTI_PIN_GROUP(pwm0_gpio16, REG_PINMUX4, GENMASK(3, 0), 0x00000005), |
| 206 | VISCONTI_PIN_GROUP(pwm1_gpio17, REG_PINMUX4, GENMASK(7, 4), 0x00000050), |
| 207 | VISCONTI_PIN_GROUP(pwm2_gpio18, REG_PINMUX4, GENMASK(11, 8), 0x00000500), |
| 208 | VISCONTI_PIN_GROUP(pwm3_gpio19, REG_PINMUX4, GENMASK(15, 12), 0x00005000), |
| 209 | VISCONTI_PIN_GROUP(pcmif_out, REG_PINMUX4, GENMASK(27, 16), 0x01110000), |
| 210 | VISCONTI_PIN_GROUP(pcmif_in, REG_PINMUX5, GENMASK(11, 0), 0x00000222), |
| 211 | }; |
| 212 | |
| 213 | /* MUX */ |
| 214 | VISCONTI_GROUPS(i2c0, "i2c0_grp"); |
| 215 | VISCONTI_GROUPS(i2c1, "i2c1_grp"); |
| 216 | VISCONTI_GROUPS(i2c2, "i2c2_grp"); |
| 217 | VISCONTI_GROUPS(i2c3, "i2c3_grp"); |
| 218 | VISCONTI_GROUPS(i2c4, "i2c4_grp"); |
| 219 | VISCONTI_GROUPS(i2c5, "i2c5_grp"); |
| 220 | VISCONTI_GROUPS(i2c6, "i2c6_grp"); |
| 221 | VISCONTI_GROUPS(i2c7, "i2c7_grp"); |
| 222 | VISCONTI_GROUPS(i2c8, "i2c8_grp"); |
| 223 | VISCONTI_GROUPS(spi0, "spi0_grp", "spi0_cs0_grp", |
| 224 | "spi0_cs1_grp", "spi0_cs2_grp"); |
| 225 | VISCONTI_GROUPS(spi1, "spi1_grp", "spi1_cs_grp"); |
| 226 | VISCONTI_GROUPS(spi2, "spi2_grp", "spi2_cs_grp"); |
| 227 | VISCONTI_GROUPS(spi3, "spi3_grp", "spi3_cs_grp"); |
| 228 | VISCONTI_GROUPS(spi4, "spi4_grp", "spi4_cs_grp"); |
| 229 | VISCONTI_GROUPS(spi5, "spi5_grp", "spi5_cs_grp"); |
| 230 | VISCONTI_GROUPS(spi6, "spi6_grp", "spi6_cs_grp"); |
| 231 | VISCONTI_GROUPS(uart0, "uart0_grp"); |
| 232 | VISCONTI_GROUPS(uart1, "uart1_grp"); |
| 233 | VISCONTI_GROUPS(uart2, "uart2_grp"); |
| 234 | VISCONTI_GROUPS(uart3, "uart3_grp"); |
| 235 | VISCONTI_GROUPS(pwm, "pwm0_gpio4_grp", "pwm0_gpio8_grp", |
| 236 | "pwm0_gpio12_grp", "pwm0_gpio16_grp", |
| 237 | "pwm1_gpio5_grp", "pwm1_gpio9_grp", |
| 238 | "pwm1_gpio13_grp", "pwm1_gpio17_grp", |
| 239 | "pwm2_gpio6_grp", "pwm2_gpio10_grp", |
| 240 | "pwm2_gpio14_grp", "pwm2_gpio18_grp", |
| 241 | "pwm3_gpio7_grp", "pwm3_gpio11_grp", |
| 242 | "pwm3_gpio15_grp", "pwm3_gpio19_grp"); |
| 243 | VISCONTI_GROUPS(pcmif_out, "pcmif_out_grp"); |
| 244 | VISCONTI_GROUPS(pcmif_in, "pcmif_in_grp"); |
| 245 | |
| 246 | static const struct visconti_pin_function functions_tmpv7700[] = { |
| 247 | VISCONTI_PIN_FUNCTION(i2c0), |
| 248 | VISCONTI_PIN_FUNCTION(i2c1), |
| 249 | VISCONTI_PIN_FUNCTION(i2c2), |
| 250 | VISCONTI_PIN_FUNCTION(i2c3), |
| 251 | VISCONTI_PIN_FUNCTION(i2c4), |
| 252 | VISCONTI_PIN_FUNCTION(i2c5), |
| 253 | VISCONTI_PIN_FUNCTION(i2c6), |
| 254 | VISCONTI_PIN_FUNCTION(i2c7), |
| 255 | VISCONTI_PIN_FUNCTION(i2c8), |
| 256 | VISCONTI_PIN_FUNCTION(spi0), |
| 257 | VISCONTI_PIN_FUNCTION(spi1), |
| 258 | VISCONTI_PIN_FUNCTION(spi2), |
| 259 | VISCONTI_PIN_FUNCTION(spi3), |
| 260 | VISCONTI_PIN_FUNCTION(spi4), |
| 261 | VISCONTI_PIN_FUNCTION(spi5), |
| 262 | VISCONTI_PIN_FUNCTION(spi6), |
| 263 | VISCONTI_PIN_FUNCTION(uart0), |
| 264 | VISCONTI_PIN_FUNCTION(uart1), |
| 265 | VISCONTI_PIN_FUNCTION(uart2), |
| 266 | VISCONTI_PIN_FUNCTION(uart3), |
| 267 | VISCONTI_PIN_FUNCTION(pwm), |
| 268 | VISCONTI_PIN_FUNCTION(pcmif_in), |
| 269 | VISCONTI_PIN_FUNCTION(pcmif_out), |
| 270 | }; |
| 271 | |
| 272 | /* GPIO MUX */ |
| 273 | #define tmpv7700_GPIO_MUX(off, msk) \ |
| 274 | { \ |
| 275 | .offset = off, \ |
| 276 | .mask = msk, \ |
| 277 | .val = 0, \ |
| 278 | } |
| 279 | |
| 280 | static const struct visconti_mux gpio_mux_tmpv7700[] = { |
| 281 | tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)), |
| 282 | tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)), |
| 283 | tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)), |
| 284 | tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(15, 12)), |
| 285 | tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(19, 16)), |
| 286 | tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(23, 20)), |
| 287 | tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(27, 24)), |
| 288 | tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(31, 28)), |
| 289 | tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)), |
| 290 | tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)), |
| 291 | tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)), |
| 292 | tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(15, 12)), |
| 293 | tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(19, 16)), |
| 294 | tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(23, 20)), |
| 295 | tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(27, 24)), |
| 296 | tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(31, 28)), |
| 297 | tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)), |
| 298 | tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)), |
| 299 | tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)), |
| 300 | tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(15, 12)), |
| 301 | tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(19, 16)), |
| 302 | tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(23, 20)), |
| 303 | tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(27, 24)), |
| 304 | tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(31, 28)), |
| 305 | tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)), |
| 306 | tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(7, 4)), |
| 307 | tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(11, 8)), |
| 308 | tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(15, 12)), |
| 309 | tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(19, 16)), |
| 310 | tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(23, 20)), |
| 311 | tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(27, 24)), |
| 312 | tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(31, 28)), |
| 313 | }; |
| 314 | |
| 315 | static void tmpv7700_pinctrl_unlock(void __iomem *base) |
| 316 | { |
| 317 | writel(1, base + REG_KEY_CTRL); |
| 318 | writel(tmpv7700_MAGIC_NUM, base + REG_KEY_CMD); |
| 319 | } |
| 320 | |
| 321 | /* chip dependent data */ |
| 322 | static const struct visconti_pinctrl_devdata tmpv7700_pinctrl_data = { |
| 323 | .pins = pins_tmpv7700, |
| 324 | .nr_pins = ARRAY_SIZE(pins_tmpv7700), |
| 325 | .groups = groups_tmpv7700, |
| 326 | .nr_groups = ARRAY_SIZE(groups_tmpv7700), |
| 327 | .functions = functions_tmpv7700, |
| 328 | .nr_functions = ARRAY_SIZE(functions_tmpv7700), |
| 329 | .gpio_mux = gpio_mux_tmpv7700, |
| 330 | .unlock = tmpv7700_pinctrl_unlock, |
| 331 | }; |
| 332 | |
| 333 | static int tmpv7700_pinctrl_probe(struct platform_device *pdev) |
| 334 | { |
| 335 | return visconti_pinctrl_probe(pdev, &tmpv7700_pinctrl_data); |
| 336 | } |
| 337 | |
| 338 | static const struct of_device_id tmpv7700_pctrl_of_match[] = { |
| 339 | { .compatible = "toshiba,tmpv7708-pinctrl", }, |
| 340 | {}, |
| 341 | }; |
| 342 | |
| 343 | static struct platform_driver tmpv7700_pinctrl_driver = { |
| 344 | .probe = tmpv7700_pinctrl_probe, |
| 345 | .driver = { |
| 346 | .name = "tmpv7700-pinctrl", |
| 347 | .of_match_table = tmpv7700_pctrl_of_match, |
| 348 | }, |
| 349 | }; |
| 350 | |
| 351 | static int __init tmpv7700_pinctrl_init(void) |
| 352 | { |
| 353 | return platform_driver_register(&tmpv7700_pinctrl_driver); |
| 354 | } |
| 355 | arch_initcall(tmpv7700_pinctrl_init); |