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Tero Kristof60b1ea2013-06-18 18:55:59 +03001/*
2 * OMAP gate clock support
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/ti.h>
24
Tero Kristof1876162014-12-16 18:20:48 +020025#include "clock.h"
26
Tero Kristof60b1ea2013-06-18 18:55:59 +030027#undef pr_fmt
28#define pr_fmt(fmt) "%s: " fmt, __func__
29
30static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
31
32static const struct clk_ops omap_gate_clkdm_clk_ops = {
33 .init = &omap2_init_clk_clkdm,
34 .enable = &omap2_clkops_enable_clkdm,
35 .disable = &omap2_clkops_disable_clkdm,
Russ Dilld6e7bbc2018-09-04 12:19:37 +053036 .restore_context = clk_gate_restore_context,
Tero Kristof60b1ea2013-06-18 18:55:59 +030037};
38
Tero Kristo9a00fa62017-02-09 11:10:19 +020039const struct clk_ops omap_gate_clk_ops = {
Tero Kristof60b1ea2013-06-18 18:55:59 +030040 .init = &omap2_init_clk_clkdm,
41 .enable = &omap2_dflt_clk_enable,
42 .disable = &omap2_dflt_clk_disable,
43 .is_enabled = &omap2_dflt_clk_is_enabled,
Russ Dilld6e7bbc2018-09-04 12:19:37 +053044 .restore_context = clk_gate_restore_context,
Tero Kristof60b1ea2013-06-18 18:55:59 +030045};
46
47static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
48 .init = &omap2_init_clk_clkdm,
49 .enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
50 .disable = &omap2_dflt_clk_disable,
51 .is_enabled = &omap2_dflt_clk_is_enabled,
Russ Dilld6e7bbc2018-09-04 12:19:37 +053052 .restore_context = clk_gate_restore_context,
Tero Kristof60b1ea2013-06-18 18:55:59 +030053};
54
55/**
56 * omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
57 * from HSDivider PWRDN problem Implements Errata ID: i556.
Lee Jonesd52848c2021-01-20 09:30:36 +000058 * @hw: DPLL output struct clk_hw
Tero Kristof60b1ea2013-06-18 18:55:59 +030059 *
60 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
61 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
62 * valueafter their respective PWRDN bits are set. Any dummy write
63 * (Any other value different from the Read value) to the
64 * corresponding CM_CLKSEL register will refresh the dividers.
65 */
Stephen Boyda53ad8e2015-07-30 17:20:57 -070066static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
Tero Kristof60b1ea2013-06-18 18:55:59 +030067{
Tero Kristo6dbde942017-02-09 14:45:45 +020068 struct clk_omap_divider *parent;
Tero Kristof60b1ea2013-06-18 18:55:59 +030069 struct clk_hw *parent_hw;
70 u32 dummy_v, orig_v;
71 int ret;
72
73 /* Clear PWRDN bit of HSDIVIDER */
Stephen Boyda53ad8e2015-07-30 17:20:57 -070074 ret = omap2_dflt_clk_enable(hw);
Tero Kristof60b1ea2013-06-18 18:55:59 +030075
76 /* Parent is the x2 node, get parent of parent for the m2 div */
Stephen Boyda53ad8e2015-07-30 17:20:57 -070077 parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
Tero Kristo6dbde942017-02-09 14:45:45 +020078 parent = to_clk_omap_divider(parent_hw);
Tero Kristof60b1ea2013-06-18 18:55:59 +030079
80 /* Restore the dividers */
81 if (!ret) {
Tero Kristo6c0afb52017-02-09 11:24:37 +020082 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);
Tero Kristof60b1ea2013-06-18 18:55:59 +030083 dummy_v = orig_v;
84
85 /* Write any other value different from the Read value */
86 dummy_v ^= (1 << parent->shift);
Tero Kristo6c0afb52017-02-09 11:24:37 +020087 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);
Tero Kristof60b1ea2013-06-18 18:55:59 +030088
89 /* Write the original divider */
Tero Kristo6c0afb52017-02-09 11:24:37 +020090 ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);
Tero Kristof60b1ea2013-06-18 18:55:59 +030091 }
92
93 return ret;
94}
95
Tero Kristof1876162014-12-16 18:20:48 +020096static struct clk *_register_gate(struct device *dev, const char *name,
97 const char *parent_name, unsigned long flags,
Tero Kristo6c0afb52017-02-09 11:24:37 +020098 struct clk_omap_reg *reg, u8 bit_idx,
Tero Kristof1876162014-12-16 18:20:48 +020099 u8 clk_gate_flags, const struct clk_ops *ops,
100 const struct clk_hw_omap_ops *hw_ops)
101{
102 struct clk_init_data init = { NULL };
103 struct clk_hw_omap *clk_hw;
104 struct clk *clk;
105
106 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
107 if (!clk_hw)
108 return ERR_PTR(-ENOMEM);
109
110 clk_hw->hw.init = &init;
111
112 init.name = name;
113 init.ops = ops;
114
Tero Kristo6c0afb52017-02-09 11:24:37 +0200115 memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
Tero Kristof1876162014-12-16 18:20:48 +0200116 clk_hw->enable_bit = bit_idx;
117 clk_hw->ops = hw_ops;
118
Tero Kristoc91f0782017-01-30 16:01:36 +0200119 clk_hw->flags = clk_gate_flags;
Tero Kristof1876162014-12-16 18:20:48 +0200120
121 init.parent_names = &parent_name;
122 init.num_parents = 1;
123
124 init.flags = flags;
125
Tero Kristoead47822019-01-15 11:15:15 +0200126 clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name);
Tero Kristof1876162014-12-16 18:20:48 +0200127
128 if (IS_ERR(clk))
129 kfree(clk_hw);
130
131 return clk;
132}
133
Tero Kristof60b1ea2013-06-18 18:55:59 +0300134static void __init _of_ti_gate_clk_setup(struct device_node *node,
135 const struct clk_ops *ops,
136 const struct clk_hw_omap_ops *hw_ops)
137{
138 struct clk *clk;
Tero Kristof60b1ea2013-06-18 18:55:59 +0300139 const char *parent_name;
Tero Kristo6c0afb52017-02-09 11:24:37 +0200140 struct clk_omap_reg reg;
Tony Lindgrened060992022-02-04 09:14:49 +0200141 const char *name;
Tero Kristof1876162014-12-16 18:20:48 +0200142 u8 enable_bit = 0;
Tero Kristof60b1ea2013-06-18 18:55:59 +0300143 u32 val;
Tero Kristof1876162014-12-16 18:20:48 +0200144 u32 flags = 0;
145 u8 clk_gate_flags = 0;
Tero Kristof60b1ea2013-06-18 18:55:59 +0300146
147 if (ops != &omap_gate_clkdm_clk_ops) {
Tero Kristo6c0afb52017-02-09 11:24:37 +0200148 if (ti_clk_get_reg_addr(node, 0, &reg))
Tero Kristof1876162014-12-16 18:20:48 +0200149 return;
Tero Kristof60b1ea2013-06-18 18:55:59 +0300150
151 if (!of_property_read_u32(node, "ti,bit-shift", &val))
Tero Kristof1876162014-12-16 18:20:48 +0200152 enable_bit = val;
Tero Kristof60b1ea2013-06-18 18:55:59 +0300153 }
154
Tero Kristof60b1ea2013-06-18 18:55:59 +0300155 if (of_clk_get_parent_count(node) != 1) {
Rob Herringe665f022018-08-28 10:44:29 -0500156 pr_err("%pOFn must have 1 parent\n", node);
Tero Kristof1876162014-12-16 18:20:48 +0200157 return;
Tero Kristof60b1ea2013-06-18 18:55:59 +0300158 }
159
160 parent_name = of_clk_get_parent_name(node, 0);
Tero Kristof60b1ea2013-06-18 18:55:59 +0300161
162 if (of_property_read_bool(node, "ti,set-rate-parent"))
Tero Kristof1876162014-12-16 18:20:48 +0200163 flags |= CLK_SET_RATE_PARENT;
Tero Kristof60b1ea2013-06-18 18:55:59 +0300164
165 if (of_property_read_bool(node, "ti,set-bit-to-disable"))
Tero Kristof1876162014-12-16 18:20:48 +0200166 clk_gate_flags |= INVERT_ENABLE;
Tero Kristof60b1ea2013-06-18 18:55:59 +0300167
Tony Lindgrened060992022-02-04 09:14:49 +0200168 name = ti_dt_clk_name(node);
169 clk = _register_gate(NULL, name, parent_name, flags, &reg,
Tero Kristof1876162014-12-16 18:20:48 +0200170 enable_bit, clk_gate_flags, ops, hw_ops);
Tero Kristof60b1ea2013-06-18 18:55:59 +0300171
Tero Kristof1876162014-12-16 18:20:48 +0200172 if (!IS_ERR(clk))
Tero Kristof60b1ea2013-06-18 18:55:59 +0300173 of_clk_add_provider(node, of_clk_src_simple_get, clk);
Tero Kristof60b1ea2013-06-18 18:55:59 +0300174}
175
176static void __init
177_of_ti_composite_gate_clk_setup(struct device_node *node,
178 const struct clk_hw_omap_ops *hw_ops)
179{
180 struct clk_hw_omap *gate;
181 u32 val = 0;
182
183 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
184 if (!gate)
185 return;
186
Tero Kristo6c0afb52017-02-09 11:24:37 +0200187 if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
Tero Kristof60b1ea2013-06-18 18:55:59 +0300188 goto cleanup;
189
190 of_property_read_u32(node, "ti,bit-shift", &val);
191
192 gate->enable_bit = val;
193 gate->ops = hw_ops;
Tero Kristof60b1ea2013-06-18 18:55:59 +0300194
195 if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
196 return;
197
198cleanup:
199 kfree(gate);
200}
201
202static void __init
203of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
204{
205 _of_ti_composite_gate_clk_setup(node, NULL);
206}
207CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
208 of_ti_composite_no_wait_gate_clk_setup);
209
Tero Kristob3654d72014-03-05 10:03:38 +0200210#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
Tero Kristof60b1ea2013-06-18 18:55:59 +0300211static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
212{
213 _of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
214}
215CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
216 of_ti_composite_interface_clk_setup);
217#endif
218
219static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
220{
221 _of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
222}
223CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
224 of_ti_composite_gate_clk_setup);
225
226
227static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
228{
229 _of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
230}
231CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
232 of_ti_clkdm_gate_clk_setup);
233
234static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
235{
236 _of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
237 &clkhwops_wait);
238}
239CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
240 of_ti_hsdiv_gate_clk_setup);
241
242static void __init of_ti_gate_clk_setup(struct device_node *node)
243{
244 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
245}
Rob Herring826d8952014-05-12 11:41:19 -0500246CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
Tero Kristof60b1ea2013-06-18 18:55:59 +0300247
248static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
249{
250 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
251}
252CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
253 of_ti_wait_gate_clk_setup);
254
255#ifdef CONFIG_ARCH_OMAP3
256static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
257{
258 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
259 &clkhwops_am35xx_ipss_module_wait);
260}
261CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
262 of_ti_am35xx_gate_clk_setup);
263
264static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
265{
266 _of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
267 &clkhwops_omap3430es2_dss_usbhost_wait);
268}
269CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
270 of_ti_dss_gate_clk_setup);
271#endif