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Gregory CLEMENT43058342019-02-08 17:09:42 +01001// SPDX-License-Identifier: GPL-2.0+
Roland Stigge906ecf62012-02-14 19:44:56 +01002/*
3 * lpc32xx_adc.c - Support for ADC in LPC32XX
4 *
5 * 3-channel, 10-bit ADC
6 *
7 * Copyright (C) 2011, 2012 Roland Stigge <stigge@antcom.de>
Roland Stigge906ecf62012-02-14 19:44:56 +01008 */
9
Roland Stigge906ecf62012-02-14 19:44:56 +010010#include <linux/clk.h>
Roland Stigge906ecf62012-02-14 19:44:56 +010011#include <linux/completion.h>
Gregory CLEMENT16332102019-03-15 10:52:28 +010012#include <linux/err.h>
Jonathan Cameron06458e22012-04-25 15:54:58 +010013#include <linux/iio/iio.h>
Gregory CLEMENT16332102019-03-15 10:52:28 +010014#include <linux/interrupt.h>
15#include <linux/io.h>
Gregory CLEMENT16332102019-03-15 10:52:28 +010016#include <linux/module.h>
Gregory CLEMENT16332102019-03-15 10:52:28 +010017#include <linux/platform_device.h>
Gregory CLEMENTe32cff62019-03-15 10:52:30 +010018#include <linux/regulator/consumer.h>
Roland Stigge906ecf62012-02-14 19:44:56 +010019
20/*
21 * LPC32XX registers definitions
22 */
Jonathan Cameron50235742017-02-05 13:06:58 +000023#define LPC32XXAD_SELECT(x) ((x) + 0x04)
24#define LPC32XXAD_CTRL(x) ((x) + 0x08)
25#define LPC32XXAD_VALUE(x) ((x) + 0x48)
Roland Stigge906ecf62012-02-14 19:44:56 +010026
Jonathan Cameron50235742017-02-05 13:06:58 +000027/* Bit definitions for LPC32XXAD_SELECT: */
28/* constant, always write this value! */
29#define LPC32XXAD_REFm 0x00000200
30/* constant, always write this value! */
31#define LPC32XXAD_REFp 0x00000080
32 /* multiple of this is the channel number: 0, 1, 2 */
33#define LPC32XXAD_IN 0x00000010
34/* constant, always write this value! */
35#define LPC32XXAD_INTERNAL 0x00000004
Roland Stigge906ecf62012-02-14 19:44:56 +010036
Jonathan Cameron50235742017-02-05 13:06:58 +000037/* Bit definitions for LPC32XXAD_CTRL: */
38#define LPC32XXAD_STROBE 0x00000002
39#define LPC32XXAD_PDN_CTRL 0x00000004
Roland Stigge906ecf62012-02-14 19:44:56 +010040
Jonathan Cameron50235742017-02-05 13:06:58 +000041/* Bit definitions for LPC32XXAD_VALUE: */
42#define LPC32XXAD_VALUE_MASK 0x000003FF
Roland Stigge906ecf62012-02-14 19:44:56 +010043
Jonathan Cameron50235742017-02-05 13:06:58 +000044#define LPC32XXAD_NAME "lpc32xx-adc"
Roland Stigge906ecf62012-02-14 19:44:56 +010045
Jonathan Cameron7901b2a2017-02-05 13:06:59 +000046struct lpc32xx_adc_state {
Roland Stigge906ecf62012-02-14 19:44:56 +010047 void __iomem *adc_base;
48 struct clk *clk;
49 struct completion completion;
Gregory CLEMENTe32cff62019-03-15 10:52:30 +010050 struct regulator *vref;
Roland Stigge906ecf62012-02-14 19:44:56 +010051
52 u32 value;
53};
54
55static int lpc32xx_read_raw(struct iio_dev *indio_dev,
Ioana Ciorneie8ef49f2015-10-14 21:14:13 +030056 struct iio_chan_spec const *chan,
57 int *val,
58 int *val2,
59 long mask)
Roland Stigge906ecf62012-02-14 19:44:56 +010060{
Jonathan Cameron7901b2a2017-02-05 13:06:59 +000061 struct lpc32xx_adc_state *st = iio_priv(indio_dev);
Arvind Yadav42d97ac2017-05-30 16:35:27 +053062 int ret;
Gregory CLEMENTe32cff62019-03-15 10:52:30 +010063
64 switch (mask) {
65 case IIO_CHAN_INFO_RAW:
Roland Stigge906ecf62012-02-14 19:44:56 +010066 mutex_lock(&indio_dev->mlock);
Arvind Yadav42d97ac2017-05-30 16:35:27 +053067 ret = clk_prepare_enable(st->clk);
68 if (ret) {
69 mutex_unlock(&indio_dev->mlock);
70 return ret;
71 }
Roland Stigge906ecf62012-02-14 19:44:56 +010072 /* Measurement setup */
Jonathan Cameron50235742017-02-05 13:06:58 +000073 __raw_writel(LPC32XXAD_INTERNAL | (chan->address) |
74 LPC32XXAD_REFp | LPC32XXAD_REFm,
Jonathan Cameron7901b2a2017-02-05 13:06:59 +000075 LPC32XXAD_SELECT(st->adc_base));
Roland Stigge906ecf62012-02-14 19:44:56 +010076 /* Trigger conversion */
Jonathan Cameron50235742017-02-05 13:06:58 +000077 __raw_writel(LPC32XXAD_PDN_CTRL | LPC32XXAD_STROBE,
Jonathan Cameron7901b2a2017-02-05 13:06:59 +000078 LPC32XXAD_CTRL(st->adc_base));
79 wait_for_completion(&st->completion); /* set by ISR */
80 clk_disable_unprepare(st->clk);
81 *val = st->value;
Roland Stigge906ecf62012-02-14 19:44:56 +010082 mutex_unlock(&indio_dev->mlock);
83
84 return IIO_VAL_INT;
Roland Stigge906ecf62012-02-14 19:44:56 +010085
Gregory CLEMENTe32cff62019-03-15 10:52:30 +010086 case IIO_CHAN_INFO_SCALE:
87 *val = regulator_get_voltage(st->vref) / 1000;
88 *val2 = 10;
89
90 return IIO_VAL_FRACTIONAL_LOG2;
91 default:
92 return -EINVAL;
93 }
Roland Stigge906ecf62012-02-14 19:44:56 +010094}
95
96static const struct iio_info lpc32xx_adc_iio_info = {
97 .read_raw = &lpc32xx_read_raw,
Roland Stigge906ecf62012-02-14 19:44:56 +010098};
99
Gregory CLEMENTe32cff62019-03-15 10:52:30 +0100100#define LPC32XX_ADC_CHANNEL_BASE(_index) \
Jonathan Cameronb11f98f2012-04-15 17:41:18 +0100101 .type = IIO_VOLTAGE, \
102 .indexed = 1, \
103 .channel = _index, \
Jonathan Cameron066f9052013-03-04 21:10:17 +0000104 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
Jonathan Cameron50235742017-02-05 13:06:58 +0000105 .address = LPC32XXAD_IN * _index, \
Gregory CLEMENTe32cff62019-03-15 10:52:30 +0100106 .scan_index = _index,
107
108#define LPC32XX_ADC_CHANNEL(_index) { \
109 LPC32XX_ADC_CHANNEL_BASE(_index) \
110}
111
112#define LPC32XX_ADC_SCALE_CHANNEL(_index) { \
113 LPC32XX_ADC_CHANNEL_BASE(_index) \
114 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
Roland Stigge906ecf62012-02-14 19:44:56 +0100115}
116
Lars-Peter Clausenf4e4b952012-08-09 08:51:00 +0100117static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = {
Roland Stigge906ecf62012-02-14 19:44:56 +0100118 LPC32XX_ADC_CHANNEL(0),
119 LPC32XX_ADC_CHANNEL(1),
120 LPC32XX_ADC_CHANNEL(2),
121};
122
Gregory CLEMENTe32cff62019-03-15 10:52:30 +0100123static const struct iio_chan_spec lpc32xx_adc_iio_scale_channels[] = {
124 LPC32XX_ADC_SCALE_CHANNEL(0),
125 LPC32XX_ADC_SCALE_CHANNEL(1),
126 LPC32XX_ADC_SCALE_CHANNEL(2),
127};
128
Roland Stigge906ecf62012-02-14 19:44:56 +0100129static irqreturn_t lpc32xx_adc_isr(int irq, void *dev_id)
130{
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000131 struct lpc32xx_adc_state *st = dev_id;
Roland Stigge906ecf62012-02-14 19:44:56 +0100132
133 /* Read value and clear irq */
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000134 st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) &
135 LPC32XXAD_VALUE_MASK;
136 complete(&st->completion);
Roland Stigge906ecf62012-02-14 19:44:56 +0100137
138 return IRQ_HANDLED;
139}
140
Bill Pemberton4ae1c612012-11-19 13:21:57 -0500141static int lpc32xx_adc_probe(struct platform_device *pdev)
Roland Stigge906ecf62012-02-14 19:44:56 +0100142{
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000143 struct lpc32xx_adc_state *st = NULL;
Roland Stigge906ecf62012-02-14 19:44:56 +0100144 struct resource *res;
145 int retval = -ENODEV;
146 struct iio_dev *iodev = NULL;
147 int irq;
148
149 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
150 if (!res) {
151 dev_err(&pdev->dev, "failed to get platform I/O memory\n");
Peng Fanf6707ef2015-08-30 16:12:57 +0800152 return -ENXIO;
Roland Stigge906ecf62012-02-14 19:44:56 +0100153 }
154
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000155 iodev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
Sachin Kamat7d456e42013-08-31 18:12:00 +0100156 if (!iodev)
157 return -ENOMEM;
Roland Stigge906ecf62012-02-14 19:44:56 +0100158
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000159 st = iio_priv(iodev);
Roland Stigge906ecf62012-02-14 19:44:56 +0100160
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000161 st->adc_base = devm_ioremap(&pdev->dev, res->start,
162 resource_size(res));
163 if (!st->adc_base) {
Roland Stigge906ecf62012-02-14 19:44:56 +0100164 dev_err(&pdev->dev, "failed mapping memory\n");
Sachin Kamat7d456e42013-08-31 18:12:00 +0100165 return -EBUSY;
Roland Stigge906ecf62012-02-14 19:44:56 +0100166 }
167
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000168 st->clk = devm_clk_get(&pdev->dev, NULL);
169 if (IS_ERR(st->clk)) {
Roland Stigge906ecf62012-02-14 19:44:56 +0100170 dev_err(&pdev->dev, "failed getting clock\n");
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000171 return PTR_ERR(st->clk);
Roland Stigge906ecf62012-02-14 19:44:56 +0100172 }
173
174 irq = platform_get_irq(pdev, 0);
Lars-Peter Clausen2918ad12013-10-16 21:45:00 +0100175 if (irq <= 0) {
Roland Stigge906ecf62012-02-14 19:44:56 +0100176 dev_err(&pdev->dev, "failed getting interrupt resource\n");
Peng Fanf6707ef2015-08-30 16:12:57 +0800177 return -ENXIO;
Roland Stigge906ecf62012-02-14 19:44:56 +0100178 }
179
Sachin Kamat7d456e42013-08-31 18:12:00 +0100180 retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0,
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000181 LPC32XXAD_NAME, st);
Roland Stigge906ecf62012-02-14 19:44:56 +0100182 if (retval < 0) {
183 dev_err(&pdev->dev, "failed requesting interrupt\n");
Sachin Kamat7d456e42013-08-31 18:12:00 +0100184 return retval;
Roland Stigge906ecf62012-02-14 19:44:56 +0100185 }
186
Gregory CLEMENTe32cff62019-03-15 10:52:30 +0100187 st->vref = devm_regulator_get(&pdev->dev, "vref");
188 if (IS_ERR(st->vref)) {
189 iodev->channels = lpc32xx_adc_iio_channels;
190 dev_info(&pdev->dev,
191 "Missing vref regulator: No scaling available\n");
192 } else {
193 iodev->channels = lpc32xx_adc_iio_scale_channels;
194 }
195
Roland Stigge906ecf62012-02-14 19:44:56 +0100196 platform_set_drvdata(pdev, iodev);
197
Jonathan Cameron7901b2a2017-02-05 13:06:59 +0000198 init_completion(&st->completion);
Roland Stigge906ecf62012-02-14 19:44:56 +0100199
Jonathan Cameron50235742017-02-05 13:06:58 +0000200 iodev->name = LPC32XXAD_NAME;
Roland Stigge906ecf62012-02-14 19:44:56 +0100201 iodev->dev.parent = &pdev->dev;
202 iodev->info = &lpc32xx_adc_iio_info;
203 iodev->modes = INDIO_DIRECT_MODE;
Roland Stigge906ecf62012-02-14 19:44:56 +0100204 iodev->num_channels = ARRAY_SIZE(lpc32xx_adc_iio_channels);
205
Sachin Kamatafb6fd52013-10-29 11:39:00 +0000206 retval = devm_iio_device_register(&pdev->dev, iodev);
Roland Stigge906ecf62012-02-14 19:44:56 +0100207 if (retval)
Sachin Kamat7d456e42013-08-31 18:12:00 +0100208 return retval;
Roland Stigge906ecf62012-02-14 19:44:56 +0100209
210 dev_info(&pdev->dev, "LPC32XX ADC driver loaded, IRQ %d\n", irq);
211
212 return 0;
Roland Stigge906ecf62012-02-14 19:44:56 +0100213}
214
Roland Stigge1f9e3492012-04-21 10:10:16 +0200215#ifdef CONFIG_OF
216static const struct of_device_id lpc32xx_adc_match[] = {
217 { .compatible = "nxp,lpc3220-adc" },
218 {},
219};
220MODULE_DEVICE_TABLE(of, lpc32xx_adc_match);
221#endif
222
Roland Stigge906ecf62012-02-14 19:44:56 +0100223static struct platform_driver lpc32xx_adc_driver = {
224 .probe = lpc32xx_adc_probe,
Roland Stigge906ecf62012-02-14 19:44:56 +0100225 .driver = {
Jonathan Cameron50235742017-02-05 13:06:58 +0000226 .name = LPC32XXAD_NAME,
Roland Stigge1f9e3492012-04-21 10:10:16 +0200227 .of_match_table = of_match_ptr(lpc32xx_adc_match),
Roland Stigge906ecf62012-02-14 19:44:56 +0100228 },
229};
230
231module_platform_driver(lpc32xx_adc_driver);
232
233MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
234MODULE_DESCRIPTION("LPC32XX ADC driver");
235MODULE_LICENSE("GPL");