Thomas Gleixner | 1802d0b | 2019-05-27 08:55:21 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2014 MediaTek Inc. |
| 4 | * Author: Jie Qiu <jie.qiu@mediatek.com> |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 5 | */ |
Sam Ravnborg | 9aef586 | 2019-07-16 08:42:20 +0200 | [diff] [blame] | 6 | |
Jie Qiu | 56ba355 | 2016-01-04 18:36:39 +0100 | [diff] [blame] | 7 | #include <linux/arm-smccc.h> |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 8 | #include <linux/clk.h> |
| 9 | #include <linux/delay.h> |
| 10 | #include <linux/hdmi.h> |
| 11 | #include <linux/i2c.h> |
| 12 | #include <linux/io.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/mfd/syscon.h> |
Tzung-Bi Shih | f07980d | 2020-02-17 11:16:53 +0800 | [diff] [blame] | 15 | #include <linux/mutex.h> |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 16 | #include <linux/of_platform.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/of_gpio.h> |
| 19 | #include <linux/of_graph.h> |
| 20 | #include <linux/phy/phy.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/regmap.h> |
Sam Ravnborg | 9aef586 | 2019-07-16 08:42:20 +0200 | [diff] [blame] | 23 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 24 | #include <sound/hdmi-codec.h> |
Sam Ravnborg | 9aef586 | 2019-07-16 08:42:20 +0200 | [diff] [blame] | 25 | |
| 26 | #include <drm/drm_atomic_helper.h> |
Boris Brezillon | ee68c74 | 2019-08-26 17:26:29 +0200 | [diff] [blame] | 27 | #include <drm/drm_bridge.h> |
Sam Ravnborg | 9aef586 | 2019-07-16 08:42:20 +0200 | [diff] [blame] | 28 | #include <drm/drm_crtc.h> |
| 29 | #include <drm/drm_edid.h> |
| 30 | #include <drm/drm_print.h> |
| 31 | #include <drm/drm_probe_helper.h> |
| 32 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 33 | #include "mtk_cec.h" |
| 34 | #include "mtk_hdmi.h" |
| 35 | #include "mtk_hdmi_regs.h" |
| 36 | |
| 37 | #define NCTS_BYTES 7 |
| 38 | |
| 39 | enum mtk_hdmi_clk_id { |
| 40 | MTK_HDMI_CLK_HDMI_PIXEL, |
| 41 | MTK_HDMI_CLK_HDMI_PLL, |
| 42 | MTK_HDMI_CLK_AUD_BCLK, |
| 43 | MTK_HDMI_CLK_AUD_SPDIF, |
| 44 | MTK_HDMI_CLK_COUNT |
| 45 | }; |
| 46 | |
| 47 | enum hdmi_aud_input_type { |
| 48 | HDMI_AUD_INPUT_I2S = 0, |
| 49 | HDMI_AUD_INPUT_SPDIF, |
| 50 | }; |
| 51 | |
| 52 | enum hdmi_aud_i2s_fmt { |
| 53 | HDMI_I2S_MODE_RJT_24BIT = 0, |
| 54 | HDMI_I2S_MODE_RJT_16BIT, |
| 55 | HDMI_I2S_MODE_LJT_24BIT, |
| 56 | HDMI_I2S_MODE_LJT_16BIT, |
| 57 | HDMI_I2S_MODE_I2S_24BIT, |
| 58 | HDMI_I2S_MODE_I2S_16BIT |
| 59 | }; |
| 60 | |
| 61 | enum hdmi_aud_mclk { |
| 62 | HDMI_AUD_MCLK_128FS, |
| 63 | HDMI_AUD_MCLK_192FS, |
| 64 | HDMI_AUD_MCLK_256FS, |
| 65 | HDMI_AUD_MCLK_384FS, |
| 66 | HDMI_AUD_MCLK_512FS, |
| 67 | HDMI_AUD_MCLK_768FS, |
| 68 | HDMI_AUD_MCLK_1152FS, |
| 69 | }; |
| 70 | |
| 71 | enum hdmi_aud_channel_type { |
| 72 | HDMI_AUD_CHAN_TYPE_1_0 = 0, |
| 73 | HDMI_AUD_CHAN_TYPE_1_1, |
| 74 | HDMI_AUD_CHAN_TYPE_2_0, |
| 75 | HDMI_AUD_CHAN_TYPE_2_1, |
| 76 | HDMI_AUD_CHAN_TYPE_3_0, |
| 77 | HDMI_AUD_CHAN_TYPE_3_1, |
| 78 | HDMI_AUD_CHAN_TYPE_4_0, |
| 79 | HDMI_AUD_CHAN_TYPE_4_1, |
| 80 | HDMI_AUD_CHAN_TYPE_5_0, |
| 81 | HDMI_AUD_CHAN_TYPE_5_1, |
| 82 | HDMI_AUD_CHAN_TYPE_6_0, |
| 83 | HDMI_AUD_CHAN_TYPE_6_1, |
| 84 | HDMI_AUD_CHAN_TYPE_7_0, |
| 85 | HDMI_AUD_CHAN_TYPE_7_1, |
| 86 | HDMI_AUD_CHAN_TYPE_3_0_LRS, |
| 87 | HDMI_AUD_CHAN_TYPE_3_1_LRS, |
| 88 | HDMI_AUD_CHAN_TYPE_4_0_CLRS, |
| 89 | HDMI_AUD_CHAN_TYPE_4_1_CLRS, |
| 90 | HDMI_AUD_CHAN_TYPE_6_1_CS, |
| 91 | HDMI_AUD_CHAN_TYPE_6_1_CH, |
| 92 | HDMI_AUD_CHAN_TYPE_6_1_OH, |
| 93 | HDMI_AUD_CHAN_TYPE_6_1_CHR, |
| 94 | HDMI_AUD_CHAN_TYPE_7_1_LH_RH, |
| 95 | HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR, |
| 96 | HDMI_AUD_CHAN_TYPE_7_1_LC_RC, |
| 97 | HDMI_AUD_CHAN_TYPE_7_1_LW_RW, |
| 98 | HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD, |
| 99 | HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS, |
| 100 | HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS, |
| 101 | HDMI_AUD_CHAN_TYPE_7_1_CS_CH, |
| 102 | HDMI_AUD_CHAN_TYPE_7_1_CS_OH, |
| 103 | HDMI_AUD_CHAN_TYPE_7_1_CS_CHR, |
| 104 | HDMI_AUD_CHAN_TYPE_7_1_CH_OH, |
| 105 | HDMI_AUD_CHAN_TYPE_7_1_CH_CHR, |
| 106 | HDMI_AUD_CHAN_TYPE_7_1_OH_CHR, |
| 107 | HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR, |
| 108 | HDMI_AUD_CHAN_TYPE_6_0_CS, |
| 109 | HDMI_AUD_CHAN_TYPE_6_0_CH, |
| 110 | HDMI_AUD_CHAN_TYPE_6_0_OH, |
| 111 | HDMI_AUD_CHAN_TYPE_6_0_CHR, |
| 112 | HDMI_AUD_CHAN_TYPE_7_0_LH_RH, |
| 113 | HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR, |
| 114 | HDMI_AUD_CHAN_TYPE_7_0_LC_RC, |
| 115 | HDMI_AUD_CHAN_TYPE_7_0_LW_RW, |
| 116 | HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD, |
| 117 | HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS, |
| 118 | HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS, |
| 119 | HDMI_AUD_CHAN_TYPE_7_0_CS_CH, |
| 120 | HDMI_AUD_CHAN_TYPE_7_0_CS_OH, |
| 121 | HDMI_AUD_CHAN_TYPE_7_0_CS_CHR, |
| 122 | HDMI_AUD_CHAN_TYPE_7_0_CH_OH, |
| 123 | HDMI_AUD_CHAN_TYPE_7_0_CH_CHR, |
| 124 | HDMI_AUD_CHAN_TYPE_7_0_OH_CHR, |
| 125 | HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR, |
| 126 | HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS, |
| 127 | HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF |
| 128 | }; |
| 129 | |
| 130 | enum hdmi_aud_channel_swap_type { |
| 131 | HDMI_AUD_SWAP_LR, |
| 132 | HDMI_AUD_SWAP_LFE_CC, |
| 133 | HDMI_AUD_SWAP_LSRS, |
| 134 | HDMI_AUD_SWAP_RLS_RRS, |
| 135 | HDMI_AUD_SWAP_LR_STATUS, |
| 136 | }; |
| 137 | |
| 138 | struct hdmi_audio_param { |
| 139 | enum hdmi_audio_coding_type aud_codec; |
| 140 | enum hdmi_audio_sample_size aud_sampe_size; |
| 141 | enum hdmi_aud_input_type aud_input_type; |
| 142 | enum hdmi_aud_i2s_fmt aud_i2s_fmt; |
| 143 | enum hdmi_aud_mclk aud_mclk; |
| 144 | enum hdmi_aud_channel_type aud_input_chan_type; |
| 145 | struct hdmi_codec_params codec_params; |
| 146 | }; |
| 147 | |
| 148 | struct mtk_hdmi { |
| 149 | struct drm_bridge bridge; |
Laurent Pinchart | 3bb80f2 | 2016-11-28 17:59:08 +0200 | [diff] [blame] | 150 | struct drm_bridge *next_bridge; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 151 | struct drm_connector conn; |
| 152 | struct device *dev; |
| 153 | struct phy *phy; |
| 154 | struct device *cec_dev; |
| 155 | struct i2c_adapter *ddc_adpt; |
| 156 | struct clk *clk[MTK_HDMI_CLK_COUNT]; |
| 157 | struct drm_display_mode mode; |
| 158 | bool dvi_mode; |
| 159 | u32 min_clock; |
| 160 | u32 max_clock; |
| 161 | u32 max_hdisplay; |
| 162 | u32 max_vdisplay; |
| 163 | u32 ibias; |
| 164 | u32 ibias_up; |
| 165 | struct regmap *sys_regmap; |
| 166 | unsigned int sys_offset; |
| 167 | void __iomem *regs; |
| 168 | enum hdmi_colorspace csp; |
| 169 | struct hdmi_audio_param aud_param; |
| 170 | bool audio_enable; |
| 171 | bool powered; |
| 172 | bool enabled; |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 173 | hdmi_codec_plugged_cb plugged_cb; |
| 174 | struct device *codec_dev; |
Tzung-Bi Shih | f07980d | 2020-02-17 11:16:53 +0800 | [diff] [blame] | 175 | struct mutex update_plugged_status_lock; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b) |
| 179 | { |
| 180 | return container_of(b, struct mtk_hdmi, bridge); |
| 181 | } |
| 182 | |
| 183 | static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c) |
| 184 | { |
| 185 | return container_of(c, struct mtk_hdmi, conn); |
| 186 | } |
| 187 | |
| 188 | static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) |
| 189 | { |
| 190 | return readl(hdmi->regs + offset); |
| 191 | } |
| 192 | |
| 193 | static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) |
| 194 | { |
| 195 | writel(val, hdmi->regs + offset); |
| 196 | } |
| 197 | |
| 198 | static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) |
| 199 | { |
| 200 | void __iomem *reg = hdmi->regs + offset; |
| 201 | u32 tmp; |
| 202 | |
| 203 | tmp = readl(reg); |
| 204 | tmp &= ~bits; |
| 205 | writel(tmp, reg); |
| 206 | } |
| 207 | |
| 208 | static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) |
| 209 | { |
| 210 | void __iomem *reg = hdmi->regs + offset; |
| 211 | u32 tmp; |
| 212 | |
| 213 | tmp = readl(reg); |
| 214 | tmp |= bits; |
| 215 | writel(tmp, reg); |
| 216 | } |
| 217 | |
| 218 | static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) |
| 219 | { |
| 220 | void __iomem *reg = hdmi->regs + offset; |
| 221 | u32 tmp; |
| 222 | |
| 223 | tmp = readl(reg); |
| 224 | tmp = (tmp & ~mask) | (val & mask); |
| 225 | writel(tmp, reg); |
| 226 | } |
| 227 | |
| 228 | static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) |
| 229 | { |
| 230 | mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH, |
| 231 | VIDEO_SOURCE_SEL); |
| 232 | } |
| 233 | |
| 234 | static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) |
| 235 | { |
Jie Qiu | 56ba355 | 2016-01-04 18:36:39 +0100 | [diff] [blame] | 236 | struct arm_smccc_res res; |
chunhui dai | be28b65 | 2018-10-03 11:41:47 +0800 | [diff] [blame] | 237 | struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy); |
Jie Qiu | 56ba355 | 2016-01-04 18:36:39 +0100 | [diff] [blame] | 238 | |
| 239 | /* |
| 240 | * MT8173 HDMI hardware has an output control bit to enable/disable HDMI |
| 241 | * output. This bit can only be controlled in ARM supervisor mode. |
| 242 | * The ARM trusted firmware provides an API for the HDMI driver to set |
| 243 | * this control bit to enable HDMI output in supervisor mode. |
| 244 | */ |
chunhui dai | 0fc721b | 2018-10-03 11:41:49 +0800 | [diff] [blame] | 245 | if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled) |
| 246 | regmap_update_bits(hdmi->sys_regmap, |
| 247 | hdmi->sys_offset + HDMI_SYS_CFG20, |
| 248 | 0x80008005, enable ? 0x80000005 : 0x8000); |
| 249 | else |
| 250 | arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904, |
| 251 | 0x80000000, 0, 0, 0, 0, 0, &res); |
Jie Qiu | 56ba355 | 2016-01-04 18:36:39 +0100 | [diff] [blame] | 252 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 253 | regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, |
| 254 | HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); |
| 255 | regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, |
| 256 | HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0); |
| 257 | } |
| 258 | |
| 259 | static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable) |
| 260 | { |
| 261 | regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, |
| 262 | HDMI2P0_EN, enable ? 0 : HDMI2P0_EN); |
| 263 | } |
| 264 | |
| 265 | static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi) |
| 266 | { |
| 267 | mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); |
| 268 | } |
| 269 | |
| 270 | static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi) |
| 271 | { |
| 272 | mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO); |
| 273 | } |
| 274 | |
| 275 | static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi) |
| 276 | { |
| 277 | regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, |
| 278 | HDMI_RST, HDMI_RST); |
| 279 | regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, |
| 280 | HDMI_RST, 0); |
| 281 | mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY); |
| 282 | regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, |
| 283 | ANLG_ON, ANLG_ON); |
| 284 | } |
| 285 | |
| 286 | static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice) |
| 287 | { |
| 288 | mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0, |
| 289 | CFG2_NOTICE_EN); |
| 290 | } |
| 291 | |
| 292 | static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask) |
| 293 | { |
| 294 | mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask); |
| 295 | } |
| 296 | |
| 297 | static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable) |
| 298 | { |
| 299 | mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI); |
| 300 | } |
| 301 | |
| 302 | static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer, |
| 303 | u8 len) |
| 304 | { |
| 305 | u32 ctrl_reg = GRL_CTRL; |
| 306 | int i; |
| 307 | u8 *frame_data; |
| 308 | enum hdmi_infoframe_type frame_type; |
| 309 | u8 frame_ver; |
| 310 | u8 frame_len; |
| 311 | u8 checksum; |
| 312 | int ctrl_frame_en = 0; |
| 313 | |
Bernard Zhao | 3cda3d3 | 2020-05-06 05:33:55 -0700 | [diff] [blame] | 314 | frame_type = *buffer++; |
| 315 | frame_ver = *buffer++; |
| 316 | frame_len = *buffer++; |
| 317 | checksum = *buffer++; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 318 | frame_data = buffer; |
| 319 | |
| 320 | dev_dbg(hdmi->dev, |
| 321 | "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n", |
| 322 | frame_type, frame_ver, frame_len, checksum); |
| 323 | |
| 324 | switch (frame_type) { |
| 325 | case HDMI_INFOFRAME_TYPE_AVI: |
| 326 | ctrl_frame_en = CTRL_AVI_EN; |
| 327 | ctrl_reg = GRL_CTRL; |
| 328 | break; |
| 329 | case HDMI_INFOFRAME_TYPE_SPD: |
| 330 | ctrl_frame_en = CTRL_SPD_EN; |
| 331 | ctrl_reg = GRL_CTRL; |
| 332 | break; |
| 333 | case HDMI_INFOFRAME_TYPE_AUDIO: |
| 334 | ctrl_frame_en = CTRL_AUDIO_EN; |
| 335 | ctrl_reg = GRL_CTRL; |
| 336 | break; |
| 337 | case HDMI_INFOFRAME_TYPE_VENDOR: |
| 338 | ctrl_frame_en = VS_EN; |
| 339 | ctrl_reg = GRL_ACP_ISRC_CTRL; |
| 340 | break; |
Sean Paul | 1f1635b | 2019-05-22 16:21:54 -0400 | [diff] [blame] | 341 | default: |
| 342 | dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type); |
| 343 | return; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 344 | } |
| 345 | mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en); |
| 346 | mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type); |
| 347 | mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver); |
| 348 | mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len); |
| 349 | |
| 350 | mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum); |
| 351 | for (i = 0; i < frame_len; i++) |
| 352 | mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]); |
| 353 | |
| 354 | mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en); |
| 355 | } |
| 356 | |
| 357 | static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable) |
| 358 | { |
| 359 | mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF, |
| 360 | AUDIO_PACKET_OFF); |
| 361 | } |
| 362 | |
| 363 | static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi) |
| 364 | { |
| 365 | regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, |
| 366 | HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0); |
| 367 | usleep_range(2000, 4000); |
| 368 | regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, |
| 369 | HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN); |
| 370 | } |
| 371 | |
| 372 | static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi) |
| 373 | { |
| 374 | regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, |
| 375 | DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN, |
| 376 | COLOR_8BIT_MODE); |
| 377 | } |
| 378 | |
| 379 | static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi) |
| 380 | { |
| 381 | mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); |
| 382 | usleep_range(2000, 4000); |
| 383 | mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE); |
| 384 | } |
| 385 | |
| 386 | static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi) |
| 387 | { |
| 388 | mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN, |
| 389 | CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); |
| 390 | usleep_range(2000, 4000); |
| 391 | mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET, |
| 392 | CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET); |
| 393 | } |
| 394 | |
| 395 | static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on) |
| 396 | { |
| 397 | mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT, |
| 398 | CTS_CTRL_SOFT); |
| 399 | } |
| 400 | |
| 401 | static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi, |
| 402 | bool enable) |
| 403 | { |
| 404 | mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0, |
| 405 | NCTS_WRI_ANYTIME); |
| 406 | } |
| 407 | |
| 408 | static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi, |
| 409 | struct drm_display_mode *mode) |
| 410 | { |
| 411 | mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE); |
| 412 | |
| 413 | if (mode->flags & DRM_MODE_FLAG_INTERLACE && |
| 414 | mode->clock == 74250 && |
| 415 | mode->vdisplay == 1080) |
| 416 | mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); |
| 417 | else |
| 418 | mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL); |
| 419 | } |
| 420 | |
| 421 | static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi, |
| 422 | enum hdmi_aud_channel_swap_type swap) |
| 423 | { |
| 424 | u8 swap_bit; |
| 425 | |
| 426 | switch (swap) { |
| 427 | case HDMI_AUD_SWAP_LR: |
| 428 | swap_bit = LR_SWAP; |
| 429 | break; |
| 430 | case HDMI_AUD_SWAP_LFE_CC: |
| 431 | swap_bit = LFE_CC_SWAP; |
| 432 | break; |
| 433 | case HDMI_AUD_SWAP_LSRS: |
| 434 | swap_bit = LSRS_SWAP; |
| 435 | break; |
| 436 | case HDMI_AUD_SWAP_RLS_RRS: |
| 437 | swap_bit = RLS_RRS_SWAP; |
| 438 | break; |
| 439 | case HDMI_AUD_SWAP_LR_STATUS: |
| 440 | swap_bit = LR_STATUS_SWAP; |
| 441 | break; |
| 442 | default: |
| 443 | swap_bit = LFE_CC_SWAP; |
| 444 | break; |
| 445 | } |
| 446 | mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff); |
| 447 | } |
| 448 | |
| 449 | static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi, |
| 450 | enum hdmi_audio_sample_size bit_num) |
| 451 | { |
| 452 | u32 val; |
| 453 | |
| 454 | switch (bit_num) { |
| 455 | case HDMI_AUDIO_SAMPLE_SIZE_16: |
| 456 | val = AOUT_16BIT; |
| 457 | break; |
| 458 | case HDMI_AUDIO_SAMPLE_SIZE_20: |
| 459 | val = AOUT_20BIT; |
| 460 | break; |
| 461 | case HDMI_AUDIO_SAMPLE_SIZE_24: |
| 462 | case HDMI_AUDIO_SAMPLE_SIZE_STREAM: |
| 463 | val = AOUT_24BIT; |
| 464 | break; |
| 465 | } |
| 466 | |
| 467 | mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK); |
| 468 | } |
| 469 | |
| 470 | static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi, |
| 471 | enum hdmi_aud_i2s_fmt i2s_fmt) |
| 472 | { |
| 473 | u32 val; |
| 474 | |
| 475 | val = mtk_hdmi_read(hdmi, GRL_CFG0); |
| 476 | val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK); |
| 477 | |
| 478 | switch (i2s_fmt) { |
| 479 | case HDMI_I2S_MODE_RJT_24BIT: |
| 480 | val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT; |
| 481 | break; |
| 482 | case HDMI_I2S_MODE_RJT_16BIT: |
| 483 | val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT; |
| 484 | break; |
| 485 | case HDMI_I2S_MODE_LJT_24BIT: |
| 486 | default: |
| 487 | val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT; |
| 488 | break; |
| 489 | case HDMI_I2S_MODE_LJT_16BIT: |
| 490 | val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT; |
| 491 | break; |
| 492 | case HDMI_I2S_MODE_I2S_24BIT: |
| 493 | val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT; |
| 494 | break; |
| 495 | case HDMI_I2S_MODE_I2S_16BIT: |
| 496 | val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT; |
| 497 | break; |
| 498 | } |
| 499 | mtk_hdmi_write(hdmi, GRL_CFG0, val); |
| 500 | } |
| 501 | |
| 502 | static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst) |
| 503 | { |
| 504 | const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL; |
| 505 | u8 val; |
| 506 | |
| 507 | /* Disable high bitrate, set DST packet normal/double */ |
| 508 | mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN); |
| 509 | |
| 510 | if (dst) |
| 511 | val = DST_NORMAL_DOUBLE | SACD_DST; |
| 512 | else |
| 513 | val = 0; |
| 514 | |
| 515 | mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask); |
| 516 | } |
| 517 | |
| 518 | static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi, |
| 519 | enum hdmi_aud_channel_type channel_type, |
| 520 | u8 channel_count) |
| 521 | { |
| 522 | unsigned int ch_switch; |
| 523 | u8 i2s_uv; |
| 524 | |
| 525 | ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) | |
| 526 | CH_SWITCH(5, 5) | CH_SWITCH(4, 4) | |
| 527 | CH_SWITCH(3, 3) | CH_SWITCH(1, 2) | |
| 528 | CH_SWITCH(2, 1) | CH_SWITCH(0, 0); |
| 529 | |
| 530 | if (channel_count == 2) { |
| 531 | i2s_uv = I2S_UV_CH_EN(0); |
| 532 | } else if (channel_count == 3 || channel_count == 4) { |
| 533 | if (channel_count == 4 && |
| 534 | (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS || |
| 535 | channel_type == HDMI_AUD_CHAN_TYPE_4_0)) |
| 536 | i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0); |
| 537 | else |
| 538 | i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2); |
| 539 | } else if (channel_count == 6 || channel_count == 5) { |
| 540 | if (channel_count == 6 && |
| 541 | channel_type != HDMI_AUD_CHAN_TYPE_5_1 && |
| 542 | channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) { |
| 543 | i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | |
| 544 | I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); |
| 545 | } else { |
| 546 | i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) | |
| 547 | I2S_UV_CH_EN(0); |
| 548 | } |
| 549 | } else if (channel_count == 8 || channel_count == 7) { |
| 550 | i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) | |
| 551 | I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0); |
| 552 | } else { |
| 553 | i2s_uv = I2S_UV_CH_EN(0); |
| 554 | } |
| 555 | |
| 556 | mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff); |
| 557 | mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff); |
| 558 | mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff); |
| 559 | mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv); |
| 560 | } |
| 561 | |
| 562 | static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi, |
| 563 | enum hdmi_aud_input_type input_type) |
| 564 | { |
| 565 | u32 val; |
| 566 | |
| 567 | val = mtk_hdmi_read(hdmi, GRL_CFG1); |
| 568 | if (input_type == HDMI_AUD_INPUT_I2S && |
| 569 | (val & CFG1_SPDIF) == CFG1_SPDIF) { |
| 570 | val &= ~CFG1_SPDIF; |
| 571 | } else if (input_type == HDMI_AUD_INPUT_SPDIF && |
| 572 | (val & CFG1_SPDIF) == 0) { |
| 573 | val |= CFG1_SPDIF; |
| 574 | } |
| 575 | mtk_hdmi_write(hdmi, GRL_CFG1, val); |
| 576 | } |
| 577 | |
| 578 | static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, |
| 579 | u8 *channel_status) |
| 580 | { |
| 581 | int i; |
| 582 | |
| 583 | for (i = 0; i < 5; i++) { |
| 584 | mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]); |
| 585 | mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]); |
| 586 | mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]); |
| 587 | } |
| 588 | for (; i < 24; i++) { |
| 589 | mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0); |
| 590 | mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0); |
| 591 | } |
| 592 | } |
| 593 | |
| 594 | static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi) |
| 595 | { |
| 596 | u32 val; |
| 597 | |
| 598 | val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); |
| 599 | if (val & MIX_CTRL_SRC_EN) { |
| 600 | val &= ~MIX_CTRL_SRC_EN; |
| 601 | mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); |
| 602 | usleep_range(255, 512); |
| 603 | val |= MIX_CTRL_SRC_EN; |
| 604 | mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi) |
| 609 | { |
| 610 | u32 val; |
| 611 | |
| 612 | val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL); |
| 613 | val &= ~MIX_CTRL_SRC_EN; |
| 614 | mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val); |
| 615 | mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00); |
| 616 | } |
| 617 | |
| 618 | static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi, |
| 619 | enum hdmi_aud_mclk mclk) |
| 620 | { |
| 621 | u32 val; |
| 622 | |
| 623 | val = mtk_hdmi_read(hdmi, GRL_CFG5); |
| 624 | val &= CFG5_CD_RATIO_MASK; |
| 625 | |
| 626 | switch (mclk) { |
| 627 | case HDMI_AUD_MCLK_128FS: |
| 628 | val |= CFG5_FS128; |
| 629 | break; |
| 630 | case HDMI_AUD_MCLK_256FS: |
| 631 | val |= CFG5_FS256; |
| 632 | break; |
| 633 | case HDMI_AUD_MCLK_384FS: |
| 634 | val |= CFG5_FS384; |
| 635 | break; |
| 636 | case HDMI_AUD_MCLK_512FS: |
| 637 | val |= CFG5_FS512; |
| 638 | break; |
| 639 | case HDMI_AUD_MCLK_768FS: |
| 640 | val |= CFG5_FS768; |
| 641 | break; |
| 642 | default: |
| 643 | val |= CFG5_FS256; |
| 644 | break; |
| 645 | } |
| 646 | mtk_hdmi_write(hdmi, GRL_CFG5, val); |
| 647 | } |
| 648 | |
| 649 | struct hdmi_acr_n { |
| 650 | unsigned int clock; |
| 651 | unsigned int n[3]; |
| 652 | }; |
| 653 | |
| 654 | /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */ |
| 655 | static const struct hdmi_acr_n hdmi_rec_n_table[] = { |
| 656 | /* Clock, N: 32kHz 44.1kHz 48kHz */ |
| 657 | { 25175, { 4576, 7007, 6864 } }, |
| 658 | { 74176, { 11648, 17836, 11648 } }, |
| 659 | { 148352, { 11648, 8918, 5824 } }, |
| 660 | { 296703, { 5824, 4459, 5824 } }, |
| 661 | { 297000, { 3072, 4704, 5120 } }, |
| 662 | { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */ |
| 663 | }; |
| 664 | |
| 665 | /** |
| 666 | * hdmi_recommended_n() - Return N value recommended by HDMI specification |
| 667 | * @freq: audio sample rate in Hz |
| 668 | * @clock: rounded TMDS clock in kHz |
| 669 | */ |
| 670 | static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock) |
| 671 | { |
| 672 | const struct hdmi_acr_n *recommended; |
| 673 | unsigned int i; |
| 674 | |
| 675 | for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) { |
| 676 | if (clock == hdmi_rec_n_table[i].clock) |
| 677 | break; |
| 678 | } |
| 679 | recommended = hdmi_rec_n_table + i; |
| 680 | |
| 681 | switch (freq) { |
| 682 | case 32000: |
| 683 | return recommended->n[0]; |
| 684 | case 44100: |
| 685 | return recommended->n[1]; |
| 686 | case 48000: |
| 687 | return recommended->n[2]; |
| 688 | case 88200: |
| 689 | return recommended->n[1] * 2; |
| 690 | case 96000: |
| 691 | return recommended->n[2] * 2; |
| 692 | case 176400: |
| 693 | return recommended->n[1] * 4; |
| 694 | case 192000: |
| 695 | return recommended->n[2] * 4; |
| 696 | default: |
| 697 | return (128 * freq) / 1000; |
| 698 | } |
| 699 | } |
| 700 | |
| 701 | static unsigned int hdmi_mode_clock_to_hz(unsigned int clock) |
| 702 | { |
| 703 | switch (clock) { |
| 704 | case 25175: |
| 705 | return 25174825; /* 25.2/1.001 MHz */ |
| 706 | case 74176: |
| 707 | return 74175824; /* 74.25/1.001 MHz */ |
| 708 | case 148352: |
| 709 | return 148351648; /* 148.5/1.001 MHz */ |
| 710 | case 296703: |
| 711 | return 296703297; /* 297/1.001 MHz */ |
| 712 | default: |
| 713 | return clock * 1000; |
| 714 | } |
| 715 | } |
| 716 | |
| 717 | static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate, |
| 718 | unsigned int tmds_clock, unsigned int n) |
| 719 | { |
| 720 | return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n, |
| 721 | 128 * audio_sample_rate); |
| 722 | } |
| 723 | |
| 724 | static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n, |
| 725 | unsigned int cts) |
| 726 | { |
| 727 | unsigned char val[NCTS_BYTES]; |
| 728 | int i; |
| 729 | |
| 730 | mtk_hdmi_write(hdmi, GRL_NCTS, 0); |
| 731 | mtk_hdmi_write(hdmi, GRL_NCTS, 0); |
| 732 | mtk_hdmi_write(hdmi, GRL_NCTS, 0); |
| 733 | memset(val, 0, sizeof(val)); |
| 734 | |
| 735 | val[0] = (cts >> 24) & 0xff; |
| 736 | val[1] = (cts >> 16) & 0xff; |
| 737 | val[2] = (cts >> 8) & 0xff; |
| 738 | val[3] = cts & 0xff; |
| 739 | |
| 740 | val[4] = (n >> 16) & 0xff; |
| 741 | val[5] = (n >> 8) & 0xff; |
| 742 | val[6] = n & 0xff; |
| 743 | |
| 744 | for (i = 0; i < NCTS_BYTES; i++) |
| 745 | mtk_hdmi_write(hdmi, GRL_NCTS, val[i]); |
| 746 | } |
| 747 | |
| 748 | static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, |
| 749 | unsigned int sample_rate, |
| 750 | unsigned int clock) |
| 751 | { |
| 752 | unsigned int n, cts; |
| 753 | |
| 754 | n = hdmi_recommended_n(sample_rate, clock); |
| 755 | cts = hdmi_expected_cts(sample_rate, clock, n); |
| 756 | |
| 757 | dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n", |
| 758 | __func__, sample_rate, clock, n, cts); |
| 759 | |
| 760 | mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64, |
| 761 | AUDIO_I2S_NCTS_SEL); |
| 762 | do_hdmi_hw_aud_set_ncts(hdmi, n, cts); |
| 763 | } |
| 764 | |
| 765 | static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type) |
| 766 | { |
| 767 | switch (channel_type) { |
| 768 | case HDMI_AUD_CHAN_TYPE_1_0: |
| 769 | case HDMI_AUD_CHAN_TYPE_1_1: |
| 770 | case HDMI_AUD_CHAN_TYPE_2_0: |
| 771 | return 2; |
| 772 | case HDMI_AUD_CHAN_TYPE_2_1: |
| 773 | case HDMI_AUD_CHAN_TYPE_3_0: |
| 774 | return 3; |
| 775 | case HDMI_AUD_CHAN_TYPE_3_1: |
| 776 | case HDMI_AUD_CHAN_TYPE_4_0: |
| 777 | case HDMI_AUD_CHAN_TYPE_3_0_LRS: |
| 778 | return 4; |
| 779 | case HDMI_AUD_CHAN_TYPE_4_1: |
| 780 | case HDMI_AUD_CHAN_TYPE_5_0: |
| 781 | case HDMI_AUD_CHAN_TYPE_3_1_LRS: |
| 782 | case HDMI_AUD_CHAN_TYPE_4_0_CLRS: |
| 783 | return 5; |
| 784 | case HDMI_AUD_CHAN_TYPE_5_1: |
| 785 | case HDMI_AUD_CHAN_TYPE_6_0: |
| 786 | case HDMI_AUD_CHAN_TYPE_4_1_CLRS: |
| 787 | case HDMI_AUD_CHAN_TYPE_6_0_CS: |
| 788 | case HDMI_AUD_CHAN_TYPE_6_0_CH: |
| 789 | case HDMI_AUD_CHAN_TYPE_6_0_OH: |
| 790 | case HDMI_AUD_CHAN_TYPE_6_0_CHR: |
| 791 | return 6; |
| 792 | case HDMI_AUD_CHAN_TYPE_6_1: |
| 793 | case HDMI_AUD_CHAN_TYPE_6_1_CS: |
| 794 | case HDMI_AUD_CHAN_TYPE_6_1_CH: |
| 795 | case HDMI_AUD_CHAN_TYPE_6_1_OH: |
| 796 | case HDMI_AUD_CHAN_TYPE_6_1_CHR: |
| 797 | case HDMI_AUD_CHAN_TYPE_7_0: |
| 798 | case HDMI_AUD_CHAN_TYPE_7_0_LH_RH: |
| 799 | case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR: |
| 800 | case HDMI_AUD_CHAN_TYPE_7_0_LC_RC: |
| 801 | case HDMI_AUD_CHAN_TYPE_7_0_LW_RW: |
| 802 | case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD: |
| 803 | case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS: |
| 804 | case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS: |
| 805 | case HDMI_AUD_CHAN_TYPE_7_0_CS_CH: |
| 806 | case HDMI_AUD_CHAN_TYPE_7_0_CS_OH: |
| 807 | case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR: |
| 808 | case HDMI_AUD_CHAN_TYPE_7_0_CH_OH: |
| 809 | case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR: |
| 810 | case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR: |
| 811 | case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR: |
| 812 | case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS: |
| 813 | return 7; |
| 814 | case HDMI_AUD_CHAN_TYPE_7_1: |
| 815 | case HDMI_AUD_CHAN_TYPE_7_1_LH_RH: |
| 816 | case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR: |
| 817 | case HDMI_AUD_CHAN_TYPE_7_1_LC_RC: |
| 818 | case HDMI_AUD_CHAN_TYPE_7_1_LW_RW: |
| 819 | case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD: |
| 820 | case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS: |
| 821 | case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS: |
| 822 | case HDMI_AUD_CHAN_TYPE_7_1_CS_CH: |
| 823 | case HDMI_AUD_CHAN_TYPE_7_1_CS_OH: |
| 824 | case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR: |
| 825 | case HDMI_AUD_CHAN_TYPE_7_1_CH_OH: |
| 826 | case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR: |
| 827 | case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR: |
| 828 | case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR: |
| 829 | return 8; |
| 830 | default: |
| 831 | return 2; |
| 832 | } |
| 833 | } |
| 834 | |
| 835 | static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock) |
| 836 | { |
| 837 | unsigned long rate; |
| 838 | int ret; |
| 839 | |
| 840 | /* The DPI driver already should have set TVDPLL to the correct rate */ |
| 841 | ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock); |
| 842 | if (ret) { |
| 843 | dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock, |
| 844 | ret); |
| 845 | return ret; |
| 846 | } |
| 847 | |
| 848 | rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); |
| 849 | |
| 850 | if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000)) |
| 851 | dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, |
| 852 | rate); |
| 853 | else |
| 854 | dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate); |
| 855 | |
| 856 | mtk_hdmi_hw_config_sys(hdmi); |
| 857 | mtk_hdmi_hw_set_deep_color_mode(hdmi); |
| 858 | return 0; |
| 859 | } |
| 860 | |
| 861 | static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi, |
| 862 | struct drm_display_mode *mode) |
| 863 | { |
| 864 | mtk_hdmi_hw_reset(hdmi); |
| 865 | mtk_hdmi_hw_enable_notice(hdmi, true); |
| 866 | mtk_hdmi_hw_write_int_mask(hdmi, 0xff); |
| 867 | mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode); |
| 868 | mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true); |
| 869 | |
| 870 | mtk_hdmi_hw_msic_setting(hdmi, mode); |
| 871 | } |
| 872 | |
| 873 | static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable) |
| 874 | { |
| 875 | mtk_hdmi_hw_send_aud_packet(hdmi, enable); |
| 876 | return 0; |
| 877 | } |
| 878 | |
| 879 | static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on) |
| 880 | { |
| 881 | mtk_hdmi_hw_ncts_enable(hdmi, on); |
| 882 | return 0; |
| 883 | } |
| 884 | |
| 885 | static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi) |
| 886 | { |
| 887 | enum hdmi_aud_channel_type chan_type; |
| 888 | u8 chan_count; |
| 889 | bool dst; |
| 890 | |
| 891 | mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC); |
| 892 | mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT); |
| 893 | |
| 894 | if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF && |
| 895 | hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) { |
| 896 | mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); |
| 897 | } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) { |
| 898 | hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT; |
| 899 | } |
| 900 | |
| 901 | mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt); |
| 902 | mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24); |
| 903 | |
| 904 | dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) && |
| 905 | (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST)); |
| 906 | mtk_hdmi_hw_audio_config(hdmi, dst); |
| 907 | |
| 908 | if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) |
| 909 | chan_type = HDMI_AUD_CHAN_TYPE_2_0; |
| 910 | else |
| 911 | chan_type = hdmi->aud_param.aud_input_chan_type; |
| 912 | chan_count = mtk_hdmi_aud_get_chnl_count(chan_type); |
| 913 | mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count); |
| 914 | mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type); |
| 915 | |
| 916 | return 0; |
| 917 | } |
| 918 | |
| 919 | static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi, |
| 920 | struct drm_display_mode *display_mode) |
| 921 | { |
| 922 | unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate; |
| 923 | |
| 924 | mtk_hdmi_aud_on_off_hw_ncts(hdmi, false); |
| 925 | mtk_hdmi_hw_aud_src_disable(hdmi); |
| 926 | mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV); |
| 927 | |
| 928 | if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) { |
| 929 | switch (sample_rate) { |
| 930 | case 32000: |
| 931 | case 44100: |
| 932 | case 48000: |
| 933 | case 88200: |
| 934 | case 96000: |
| 935 | break; |
| 936 | default: |
| 937 | return -EINVAL; |
| 938 | } |
| 939 | mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk); |
| 940 | } else { |
| 941 | switch (sample_rate) { |
| 942 | case 32000: |
| 943 | case 44100: |
| 944 | case 48000: |
| 945 | break; |
| 946 | default: |
| 947 | return -EINVAL; |
| 948 | } |
| 949 | mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS); |
| 950 | } |
| 951 | |
| 952 | mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock); |
| 953 | |
| 954 | mtk_hdmi_hw_aud_src_reenable(hdmi); |
| 955 | return 0; |
| 956 | } |
| 957 | |
| 958 | static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi, |
| 959 | struct drm_display_mode *display_mode) |
| 960 | { |
| 961 | mtk_hdmi_hw_aud_mute(hdmi); |
| 962 | mtk_hdmi_aud_enable_packet(hdmi, false); |
| 963 | |
| 964 | mtk_hdmi_aud_set_input(hdmi); |
| 965 | mtk_hdmi_aud_set_src(hdmi, display_mode); |
| 966 | mtk_hdmi_hw_aud_set_channel_status(hdmi, |
| 967 | hdmi->aud_param.codec_params.iec.status); |
| 968 | |
| 969 | usleep_range(50, 100); |
| 970 | |
| 971 | mtk_hdmi_aud_on_off_hw_ncts(hdmi, true); |
| 972 | mtk_hdmi_aud_enable_packet(hdmi, true); |
| 973 | mtk_hdmi_hw_aud_unmute(hdmi); |
| 974 | return 0; |
| 975 | } |
| 976 | |
| 977 | static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, |
| 978 | struct drm_display_mode *mode) |
| 979 | { |
| 980 | struct hdmi_avi_infoframe frame; |
Bernard Zhao | 3852489 | 2020-05-06 05:42:55 -0700 | [diff] [blame] | 981 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 982 | ssize_t err; |
| 983 | |
Ville Syrjälä | 13d0add | 2019-01-08 19:28:25 +0200 | [diff] [blame] | 984 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, |
| 985 | &hdmi->conn, mode); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 986 | if (err < 0) { |
| 987 | dev_err(hdmi->dev, |
| 988 | "Failed to get AVI infoframe from mode: %zd\n", err); |
| 989 | return err; |
| 990 | } |
| 991 | |
| 992 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 993 | if (err < 0) { |
| 994 | dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err); |
| 995 | return err; |
| 996 | } |
| 997 | |
| 998 | mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); |
| 999 | return 0; |
| 1000 | } |
| 1001 | |
| 1002 | static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, |
| 1003 | const char *vendor, |
| 1004 | const char *product) |
| 1005 | { |
| 1006 | struct hdmi_spd_infoframe frame; |
Bernard Zhao | 3852489 | 2020-05-06 05:42:55 -0700 | [diff] [blame] | 1007 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE]; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1008 | ssize_t err; |
| 1009 | |
| 1010 | err = hdmi_spd_infoframe_init(&frame, vendor, product); |
| 1011 | if (err < 0) { |
| 1012 | dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", |
| 1013 | err); |
| 1014 | return err; |
| 1015 | } |
| 1016 | |
| 1017 | err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 1018 | if (err < 0) { |
| 1019 | dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err); |
| 1020 | return err; |
| 1021 | } |
| 1022 | |
| 1023 | mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); |
| 1024 | return 0; |
| 1025 | } |
| 1026 | |
| 1027 | static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi) |
| 1028 | { |
| 1029 | struct hdmi_audio_infoframe frame; |
Bernard Zhao | 3852489 | 2020-05-06 05:42:55 -0700 | [diff] [blame] | 1030 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1031 | ssize_t err; |
| 1032 | |
| 1033 | err = hdmi_audio_infoframe_init(&frame); |
| 1034 | if (err < 0) { |
| 1035 | dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n", |
| 1036 | err); |
| 1037 | return err; |
| 1038 | } |
| 1039 | |
| 1040 | frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; |
| 1041 | frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; |
| 1042 | frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; |
| 1043 | frame.channels = mtk_hdmi_aud_get_chnl_count( |
| 1044 | hdmi->aud_param.aud_input_chan_type); |
| 1045 | |
| 1046 | err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 1047 | if (err < 0) { |
| 1048 | dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n", |
| 1049 | err); |
| 1050 | return err; |
| 1051 | } |
| 1052 | |
| 1053 | mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); |
| 1054 | return 0; |
| 1055 | } |
| 1056 | |
| 1057 | static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi, |
| 1058 | struct drm_display_mode *mode) |
| 1059 | { |
| 1060 | struct hdmi_vendor_infoframe frame; |
| 1061 | u8 buffer[10]; |
| 1062 | ssize_t err; |
| 1063 | |
Ville Syrjälä | f1781e9 | 2017-11-13 19:04:19 +0200 | [diff] [blame] | 1064 | err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, |
| 1065 | &hdmi->conn, mode); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1066 | if (err) { |
| 1067 | dev_err(hdmi->dev, |
| 1068 | "Failed to get vendor infoframe from mode: %zd\n", err); |
| 1069 | return err; |
| 1070 | } |
| 1071 | |
| 1072 | err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); |
YYS | 014580f | 2017-03-21 16:27:03 +0800 | [diff] [blame] | 1073 | if (err < 0) { |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1074 | dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", |
| 1075 | err); |
| 1076 | return err; |
| 1077 | } |
| 1078 | |
| 1079 | mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer)); |
| 1080 | return 0; |
| 1081 | } |
| 1082 | |
| 1083 | static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi) |
| 1084 | { |
| 1085 | struct hdmi_audio_param *aud_param = &hdmi->aud_param; |
| 1086 | |
| 1087 | hdmi->csp = HDMI_COLORSPACE_RGB; |
| 1088 | aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; |
| 1089 | aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; |
| 1090 | aud_param->aud_input_type = HDMI_AUD_INPUT_I2S; |
| 1091 | aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; |
| 1092 | aud_param->aud_mclk = HDMI_AUD_MCLK_128FS; |
| 1093 | aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; |
| 1094 | |
| 1095 | return 0; |
| 1096 | } |
| 1097 | |
Baoyou Xie | 188af07 | 2016-09-25 15:38:29 +0800 | [diff] [blame] | 1098 | static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1099 | { |
| 1100 | mtk_hdmi_aud_enable_packet(hdmi, true); |
| 1101 | hdmi->audio_enable = true; |
| 1102 | } |
| 1103 | |
Baoyou Xie | 188af07 | 2016-09-25 15:38:29 +0800 | [diff] [blame] | 1104 | static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1105 | { |
| 1106 | mtk_hdmi_aud_enable_packet(hdmi, false); |
| 1107 | hdmi->audio_enable = false; |
| 1108 | } |
| 1109 | |
Baoyou Xie | 188af07 | 2016-09-25 15:38:29 +0800 | [diff] [blame] | 1110 | static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi, |
| 1111 | struct hdmi_audio_param *param) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1112 | { |
| 1113 | if (!hdmi->audio_enable) { |
| 1114 | dev_err(hdmi->dev, "hdmi audio is in disable state!\n"); |
| 1115 | return -EINVAL; |
| 1116 | } |
| 1117 | dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n", |
| 1118 | param->aud_codec, param->aud_input_type, |
| 1119 | param->aud_input_chan_type, param->codec_params.sample_rate); |
| 1120 | memcpy(&hdmi->aud_param, param, sizeof(*param)); |
| 1121 | return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode); |
| 1122 | } |
| 1123 | |
| 1124 | static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi, |
| 1125 | struct drm_display_mode *mode) |
| 1126 | { |
| 1127 | int ret; |
| 1128 | |
| 1129 | mtk_hdmi_hw_vid_black(hdmi, true); |
| 1130 | mtk_hdmi_hw_aud_mute(hdmi); |
| 1131 | mtk_hdmi_hw_send_av_mute(hdmi); |
| 1132 | phy_power_off(hdmi->phy); |
| 1133 | |
| 1134 | ret = mtk_hdmi_video_change_vpll(hdmi, |
| 1135 | mode->clock * 1000); |
| 1136 | if (ret) { |
| 1137 | dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret); |
| 1138 | return ret; |
| 1139 | } |
| 1140 | mtk_hdmi_video_set_display_mode(hdmi, mode); |
| 1141 | |
| 1142 | phy_power_on(hdmi->phy); |
| 1143 | mtk_hdmi_aud_output_config(hdmi, mode); |
| 1144 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1145 | mtk_hdmi_hw_vid_black(hdmi, false); |
| 1146 | mtk_hdmi_hw_aud_unmute(hdmi); |
| 1147 | mtk_hdmi_hw_send_av_unmute(hdmi); |
| 1148 | |
| 1149 | return 0; |
| 1150 | } |
| 1151 | |
| 1152 | static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = { |
| 1153 | [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel", |
| 1154 | [MTK_HDMI_CLK_HDMI_PLL] = "pll", |
| 1155 | [MTK_HDMI_CLK_AUD_BCLK] = "bclk", |
| 1156 | [MTK_HDMI_CLK_AUD_SPDIF] = "spdif", |
| 1157 | }; |
| 1158 | |
| 1159 | static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, |
| 1160 | struct device_node *np) |
| 1161 | { |
| 1162 | int i; |
| 1163 | |
| 1164 | for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) { |
| 1165 | hdmi->clk[i] = of_clk_get_by_name(np, |
| 1166 | mtk_hdmi_clk_names[i]); |
| 1167 | if (IS_ERR(hdmi->clk[i])) |
| 1168 | return PTR_ERR(hdmi->clk[i]); |
| 1169 | } |
| 1170 | return 0; |
| 1171 | } |
| 1172 | |
| 1173 | static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi) |
| 1174 | { |
| 1175 | int ret; |
| 1176 | |
| 1177 | ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); |
| 1178 | if (ret) |
| 1179 | return ret; |
| 1180 | |
| 1181 | ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); |
| 1182 | if (ret) |
| 1183 | goto err; |
| 1184 | |
| 1185 | return 0; |
| 1186 | err: |
| 1187 | clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); |
| 1188 | return ret; |
| 1189 | } |
| 1190 | |
| 1191 | static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi) |
| 1192 | { |
| 1193 | clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]); |
| 1194 | clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]); |
| 1195 | } |
| 1196 | |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1197 | static enum drm_connector_status |
| 1198 | mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi) |
| 1199 | { |
Tzung-Bi Shih | f07980d | 2020-02-17 11:16:53 +0800 | [diff] [blame] | 1200 | bool connected; |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1201 | |
Tzung-Bi Shih | f07980d | 2020-02-17 11:16:53 +0800 | [diff] [blame] | 1202 | mutex_lock(&hdmi->update_plugged_status_lock); |
| 1203 | connected = mtk_cec_hpd_high(hdmi->cec_dev); |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1204 | if (hdmi->plugged_cb && hdmi->codec_dev) |
| 1205 | hdmi->plugged_cb(hdmi->codec_dev, connected); |
Tzung-Bi Shih | f07980d | 2020-02-17 11:16:53 +0800 | [diff] [blame] | 1206 | mutex_unlock(&hdmi->update_plugged_status_lock); |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1207 | |
| 1208 | return connected ? |
| 1209 | connector_status_connected : connector_status_disconnected; |
| 1210 | } |
| 1211 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1212 | static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn, |
| 1213 | bool force) |
| 1214 | { |
| 1215 | struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1216 | return mtk_hdmi_update_plugged_status(hdmi); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1217 | } |
| 1218 | |
| 1219 | static void hdmi_conn_destroy(struct drm_connector *conn) |
| 1220 | { |
| 1221 | struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); |
| 1222 | |
| 1223 | mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL); |
| 1224 | |
| 1225 | drm_connector_cleanup(conn); |
| 1226 | } |
| 1227 | |
| 1228 | static int mtk_hdmi_conn_get_modes(struct drm_connector *conn) |
| 1229 | { |
| 1230 | struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); |
| 1231 | struct edid *edid; |
| 1232 | int ret; |
| 1233 | |
| 1234 | if (!hdmi->ddc_adpt) |
| 1235 | return -ENODEV; |
| 1236 | |
| 1237 | edid = drm_get_edid(conn, hdmi->ddc_adpt); |
| 1238 | if (!edid) |
| 1239 | return -ENODEV; |
| 1240 | |
| 1241 | hdmi->dvi_mode = !drm_detect_monitor_audio(edid); |
| 1242 | |
Daniel Vetter | c555f02 | 2018-07-09 10:40:06 +0200 | [diff] [blame] | 1243 | drm_connector_update_edid_property(conn, edid); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1244 | |
| 1245 | ret = drm_add_edid_modes(conn, edid); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1246 | kfree(edid); |
| 1247 | return ret; |
| 1248 | } |
| 1249 | |
| 1250 | static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn, |
| 1251 | struct drm_display_mode *mode) |
| 1252 | { |
| 1253 | struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); |
Boris Brezillon | fadf872 | 2019-12-03 15:15:06 +0100 | [diff] [blame] | 1254 | struct drm_bridge *next_bridge; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1255 | |
| 1256 | dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", |
| 1257 | mode->hdisplay, mode->vdisplay, mode->vrefresh, |
| 1258 | !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000); |
| 1259 | |
Boris Brezillon | fadf872 | 2019-12-03 15:15:06 +0100 | [diff] [blame] | 1260 | next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge); |
| 1261 | if (next_bridge) { |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1262 | struct drm_display_mode adjusted_mode; |
| 1263 | |
| 1264 | drm_mode_copy(&adjusted_mode, mode); |
Boris Brezillon | fadf872 | 2019-12-03 15:15:06 +0100 | [diff] [blame] | 1265 | if (!drm_bridge_chain_mode_fixup(next_bridge, mode, |
Boris Brezillon | ea099ad | 2019-12-03 15:15:05 +0100 | [diff] [blame] | 1266 | &adjusted_mode)) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1267 | return MODE_BAD; |
| 1268 | } |
| 1269 | |
| 1270 | if (mode->clock < 27000) |
| 1271 | return MODE_CLOCK_LOW; |
| 1272 | if (mode->clock > 297000) |
| 1273 | return MODE_CLOCK_HIGH; |
| 1274 | |
| 1275 | return drm_mode_validate_size(mode, 0x1fff, 0x1fff); |
| 1276 | } |
| 1277 | |
| 1278 | static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn) |
| 1279 | { |
| 1280 | struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn); |
| 1281 | |
| 1282 | return hdmi->bridge.encoder; |
| 1283 | } |
| 1284 | |
| 1285 | static const struct drm_connector_funcs mtk_hdmi_connector_funcs = { |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1286 | .detect = hdmi_conn_detect, |
| 1287 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 1288 | .destroy = hdmi_conn_destroy, |
| 1289 | .reset = drm_atomic_helper_connector_reset, |
| 1290 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
| 1291 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
| 1292 | }; |
| 1293 | |
| 1294 | static const struct drm_connector_helper_funcs |
| 1295 | mtk_hdmi_connector_helper_funcs = { |
| 1296 | .get_modes = mtk_hdmi_conn_get_modes, |
| 1297 | .mode_valid = mtk_hdmi_conn_mode_valid, |
| 1298 | .best_encoder = mtk_hdmi_conn_best_enc, |
| 1299 | }; |
| 1300 | |
| 1301 | static void mtk_hdmi_hpd_event(bool hpd, struct device *dev) |
| 1302 | { |
| 1303 | struct mtk_hdmi *hdmi = dev_get_drvdata(dev); |
| 1304 | |
| 1305 | if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) |
| 1306 | drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); |
| 1307 | } |
| 1308 | |
| 1309 | /* |
| 1310 | * Bridge callbacks |
| 1311 | */ |
| 1312 | |
Laurent Pinchart | a25b988 | 2020-02-26 13:24:29 +0200 | [diff] [blame] | 1313 | static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge, |
| 1314 | enum drm_bridge_attach_flags flags) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1315 | { |
| 1316 | struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); |
| 1317 | int ret; |
| 1318 | |
Laurent Pinchart | a25b988 | 2020-02-26 13:24:29 +0200 | [diff] [blame] | 1319 | if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { |
| 1320 | DRM_ERROR("Fix bridge driver to make connector optional!"); |
| 1321 | return -EINVAL; |
| 1322 | } |
| 1323 | |
Andrzej Pietrasiewicz | 3577dc0 | 2019-07-31 18:58:16 +0200 | [diff] [blame] | 1324 | ret = drm_connector_init_with_ddc(bridge->encoder->dev, &hdmi->conn, |
| 1325 | &mtk_hdmi_connector_funcs, |
| 1326 | DRM_MODE_CONNECTOR_HDMIA, |
| 1327 | hdmi->ddc_adpt); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1328 | if (ret) { |
| 1329 | dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret); |
| 1330 | return ret; |
| 1331 | } |
| 1332 | drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs); |
| 1333 | |
| 1334 | hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD; |
| 1335 | hdmi->conn.interlace_allowed = true; |
| 1336 | hdmi->conn.doublescan_allowed = false; |
| 1337 | |
Daniel Vetter | cde4c44 | 2018-07-09 10:40:07 +0200 | [diff] [blame] | 1338 | ret = drm_connector_attach_encoder(&hdmi->conn, |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1339 | bridge->encoder); |
| 1340 | if (ret) { |
| 1341 | dev_err(hdmi->dev, |
| 1342 | "Failed to attach connector to encoder: %d\n", ret); |
| 1343 | return ret; |
| 1344 | } |
| 1345 | |
Laurent Pinchart | 3bb80f2 | 2016-11-28 17:59:08 +0200 | [diff] [blame] | 1346 | if (hdmi->next_bridge) { |
| 1347 | ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, |
Laurent Pinchart | a25b988 | 2020-02-26 13:24:29 +0200 | [diff] [blame] | 1348 | bridge, flags); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1349 | if (ret) { |
| 1350 | dev_err(hdmi->dev, |
| 1351 | "Failed to attach external bridge: %d\n", ret); |
| 1352 | return ret; |
| 1353 | } |
| 1354 | } |
| 1355 | |
| 1356 | mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev); |
| 1357 | |
| 1358 | return 0; |
| 1359 | } |
| 1360 | |
| 1361 | static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, |
| 1362 | const struct drm_display_mode *mode, |
| 1363 | struct drm_display_mode *adjusted_mode) |
| 1364 | { |
| 1365 | return true; |
| 1366 | } |
| 1367 | |
| 1368 | static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge) |
| 1369 | { |
| 1370 | struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); |
| 1371 | |
| 1372 | if (!hdmi->enabled) |
| 1373 | return; |
| 1374 | |
| 1375 | phy_power_off(hdmi->phy); |
| 1376 | clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); |
| 1377 | clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); |
| 1378 | |
| 1379 | hdmi->enabled = false; |
| 1380 | } |
| 1381 | |
| 1382 | static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge) |
| 1383 | { |
| 1384 | struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); |
| 1385 | |
| 1386 | if (!hdmi->powered) |
| 1387 | return; |
| 1388 | |
| 1389 | mtk_hdmi_hw_1p4_version_enable(hdmi, true); |
| 1390 | mtk_hdmi_hw_make_reg_writable(hdmi, false); |
| 1391 | |
| 1392 | hdmi->powered = false; |
| 1393 | } |
| 1394 | |
| 1395 | static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge, |
Laurent Pinchart | 63f8f3b | 2018-04-06 17:39:01 +0300 | [diff] [blame] | 1396 | const struct drm_display_mode *mode, |
| 1397 | const struct drm_display_mode *adjusted_mode) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1398 | { |
| 1399 | struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); |
| 1400 | |
| 1401 | dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n", |
| 1402 | adjusted_mode->name, adjusted_mode->hdisplay); |
| 1403 | dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d", |
| 1404 | adjusted_mode->hsync_start, adjusted_mode->hsync_end, |
| 1405 | adjusted_mode->htotal); |
| 1406 | dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n", |
| 1407 | adjusted_mode->hskew, adjusted_mode->vdisplay); |
| 1408 | dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d", |
| 1409 | adjusted_mode->vsync_start, adjusted_mode->vsync_end, |
| 1410 | adjusted_mode->vtotal); |
| 1411 | dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n", |
| 1412 | adjusted_mode->vscan, adjusted_mode->flags); |
| 1413 | |
| 1414 | drm_mode_copy(&hdmi->mode, adjusted_mode); |
| 1415 | } |
| 1416 | |
| 1417 | static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge) |
| 1418 | { |
| 1419 | struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); |
| 1420 | |
| 1421 | mtk_hdmi_hw_make_reg_writable(hdmi, true); |
| 1422 | mtk_hdmi_hw_1p4_version_enable(hdmi, true); |
| 1423 | |
| 1424 | hdmi->powered = true; |
| 1425 | } |
| 1426 | |
Junzhi Zhao | d542b7c | 2016-09-29 11:02:13 +0800 | [diff] [blame] | 1427 | static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, |
| 1428 | struct drm_display_mode *mode) |
| 1429 | { |
| 1430 | mtk_hdmi_setup_audio_infoframe(hdmi); |
| 1431 | mtk_hdmi_setup_avi_infoframe(hdmi, mode); |
| 1432 | mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI"); |
| 1433 | if (mode->flags & DRM_MODE_FLAG_3D_MASK) |
| 1434 | mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode); |
| 1435 | } |
| 1436 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1437 | static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge) |
| 1438 | { |
| 1439 | struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); |
| 1440 | |
| 1441 | mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode); |
| 1442 | clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]); |
| 1443 | clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]); |
| 1444 | phy_power_on(hdmi->phy); |
Junzhi Zhao | d542b7c | 2016-09-29 11:02:13 +0800 | [diff] [blame] | 1445 | mtk_hdmi_send_infoframe(hdmi, &hdmi->mode); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1446 | |
| 1447 | hdmi->enabled = true; |
| 1448 | } |
| 1449 | |
| 1450 | static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = { |
| 1451 | .attach = mtk_hdmi_bridge_attach, |
| 1452 | .mode_fixup = mtk_hdmi_bridge_mode_fixup, |
| 1453 | .disable = mtk_hdmi_bridge_disable, |
| 1454 | .post_disable = mtk_hdmi_bridge_post_disable, |
| 1455 | .mode_set = mtk_hdmi_bridge_mode_set, |
| 1456 | .pre_enable = mtk_hdmi_bridge_pre_enable, |
| 1457 | .enable = mtk_hdmi_bridge_enable, |
| 1458 | }; |
| 1459 | |
| 1460 | static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, |
| 1461 | struct platform_device *pdev) |
| 1462 | { |
| 1463 | struct device *dev = &pdev->dev; |
| 1464 | struct device_node *np = dev->of_node; |
Rob Herring | 86418f90 | 2017-03-22 08:26:06 -0500 | [diff] [blame] | 1465 | struct device_node *cec_np, *remote, *i2c_np; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1466 | struct platform_device *cec_pdev; |
| 1467 | struct regmap *regmap; |
| 1468 | struct resource *mem; |
| 1469 | int ret; |
| 1470 | |
| 1471 | ret = mtk_hdmi_get_all_clk(hdmi, np); |
| 1472 | if (ret) { |
Matthias Brugger | af19d64 | 2020-03-25 18:31:19 +0100 | [diff] [blame] | 1473 | if (ret != -EPROBE_DEFER) |
| 1474 | dev_err(dev, "Failed to get clocks: %d\n", ret); |
| 1475 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1476 | return ret; |
| 1477 | } |
| 1478 | |
| 1479 | /* The CEC module handles HDMI hotplug detection */ |
Johan Hovold | ceff2f4dc | 2018-08-27 10:21:46 +0200 | [diff] [blame] | 1480 | cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec"); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1481 | if (!cec_np) { |
| 1482 | dev_err(dev, "Failed to find CEC node\n"); |
| 1483 | return -EINVAL; |
| 1484 | } |
| 1485 | |
| 1486 | cec_pdev = of_find_device_by_node(cec_np); |
| 1487 | if (!cec_pdev) { |
Rob Herring | 4bf9914 | 2017-07-18 16:43:04 -0500 | [diff] [blame] | 1488 | dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", |
| 1489 | cec_np); |
Johan Hovold | ceff2f4dc | 2018-08-27 10:21:46 +0200 | [diff] [blame] | 1490 | of_node_put(cec_np); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1491 | return -EPROBE_DEFER; |
| 1492 | } |
Johan Hovold | ceff2f4dc | 2018-08-27 10:21:46 +0200 | [diff] [blame] | 1493 | of_node_put(cec_np); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1494 | hdmi->cec_dev = &cec_pdev->dev; |
| 1495 | |
| 1496 | /* |
| 1497 | * The mediatek,syscon-hdmi property contains a phandle link to the |
| 1498 | * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG |
| 1499 | * registers it contains. |
| 1500 | */ |
| 1501 | regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi"); |
| 1502 | ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, |
| 1503 | &hdmi->sys_offset); |
| 1504 | if (IS_ERR(regmap)) |
| 1505 | ret = PTR_ERR(regmap); |
| 1506 | if (ret) { |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1507 | dev_err(dev, |
| 1508 | "Failed to get system configuration registers: %d\n", |
| 1509 | ret); |
| 1510 | return ret; |
| 1511 | } |
| 1512 | hdmi->sys_regmap = regmap; |
| 1513 | |
| 1514 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1515 | hdmi->regs = devm_ioremap_resource(dev, mem); |
| 1516 | if (IS_ERR(hdmi->regs)) |
| 1517 | return PTR_ERR(hdmi->regs); |
| 1518 | |
Rob Herring | 86418f90 | 2017-03-22 08:26:06 -0500 | [diff] [blame] | 1519 | remote = of_graph_get_remote_node(np, 1, 0); |
| 1520 | if (!remote) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1521 | return -EINVAL; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1522 | |
| 1523 | if (!of_device_is_compatible(remote, "hdmi-connector")) { |
Laurent Pinchart | 3bb80f2 | 2016-11-28 17:59:08 +0200 | [diff] [blame] | 1524 | hdmi->next_bridge = of_drm_find_bridge(remote); |
| 1525 | if (!hdmi->next_bridge) { |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1526 | dev_err(dev, "Waiting for external bridge\n"); |
| 1527 | of_node_put(remote); |
| 1528 | return -EPROBE_DEFER; |
| 1529 | } |
| 1530 | } |
| 1531 | |
| 1532 | i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0); |
| 1533 | if (!i2c_np) { |
Rob Herring | 4bf9914 | 2017-07-18 16:43:04 -0500 | [diff] [blame] | 1534 | dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n", |
| 1535 | remote); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1536 | of_node_put(remote); |
| 1537 | return -EINVAL; |
| 1538 | } |
| 1539 | of_node_put(remote); |
| 1540 | |
| 1541 | hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np); |
Wen Yang | 2ae2c33 | 2019-04-04 00:04:09 +0800 | [diff] [blame] | 1542 | of_node_put(i2c_np); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1543 | if (!hdmi->ddc_adpt) { |
| 1544 | dev_err(dev, "Failed to get ddc i2c adapter by node\n"); |
| 1545 | return -EINVAL; |
| 1546 | } |
| 1547 | |
| 1548 | return 0; |
| 1549 | } |
| 1550 | |
| 1551 | /* |
| 1552 | * HDMI audio codec callbacks |
| 1553 | */ |
| 1554 | |
Dave Airlie | 5dd0775 | 2016-07-05 09:43:02 +1000 | [diff] [blame] | 1555 | static int mtk_hdmi_audio_hw_params(struct device *dev, void *data, |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1556 | struct hdmi_codec_daifmt *daifmt, |
| 1557 | struct hdmi_codec_params *params) |
| 1558 | { |
| 1559 | struct mtk_hdmi *hdmi = dev_get_drvdata(dev); |
| 1560 | struct hdmi_audio_param hdmi_params; |
| 1561 | unsigned int chan = params->cea.channels; |
| 1562 | |
| 1563 | dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, |
| 1564 | params->sample_rate, params->sample_width, chan); |
| 1565 | |
| 1566 | if (!hdmi->bridge.encoder) |
| 1567 | return -ENODEV; |
| 1568 | |
| 1569 | switch (chan) { |
| 1570 | case 2: |
| 1571 | hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0; |
| 1572 | break; |
| 1573 | case 4: |
| 1574 | hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0; |
| 1575 | break; |
| 1576 | case 6: |
| 1577 | hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1; |
| 1578 | break; |
| 1579 | case 8: |
| 1580 | hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1; |
| 1581 | break; |
| 1582 | default: |
| 1583 | dev_err(hdmi->dev, "channel[%d] not supported!\n", chan); |
| 1584 | return -EINVAL; |
| 1585 | } |
| 1586 | |
| 1587 | switch (params->sample_rate) { |
| 1588 | case 32000: |
| 1589 | case 44100: |
| 1590 | case 48000: |
| 1591 | case 88200: |
| 1592 | case 96000: |
| 1593 | case 176400: |
| 1594 | case 192000: |
| 1595 | break; |
| 1596 | default: |
| 1597 | dev_err(hdmi->dev, "rate[%d] not supported!\n", |
| 1598 | params->sample_rate); |
| 1599 | return -EINVAL; |
| 1600 | } |
| 1601 | |
| 1602 | switch (daifmt->fmt) { |
| 1603 | case HDMI_I2S: |
| 1604 | hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; |
| 1605 | hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; |
| 1606 | hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S; |
| 1607 | hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT; |
| 1608 | hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS; |
| 1609 | break; |
chunhui dai | d1ef028 | 2018-10-03 11:41:48 +0800 | [diff] [blame] | 1610 | case HDMI_SPDIF: |
| 1611 | hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM; |
| 1612 | hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16; |
| 1613 | hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF; |
| 1614 | break; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1615 | default: |
| 1616 | dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__, |
| 1617 | daifmt->fmt); |
| 1618 | return -EINVAL; |
| 1619 | } |
| 1620 | |
| 1621 | memcpy(&hdmi_params.codec_params, params, |
| 1622 | sizeof(hdmi_params.codec_params)); |
| 1623 | |
| 1624 | mtk_hdmi_audio_set_param(hdmi, &hdmi_params); |
| 1625 | |
| 1626 | return 0; |
| 1627 | } |
| 1628 | |
Dave Airlie | 5dd0775 | 2016-07-05 09:43:02 +1000 | [diff] [blame] | 1629 | static int mtk_hdmi_audio_startup(struct device *dev, void *data) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1630 | { |
| 1631 | struct mtk_hdmi *hdmi = dev_get_drvdata(dev); |
| 1632 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1633 | mtk_hdmi_audio_enable(hdmi); |
| 1634 | |
| 1635 | return 0; |
| 1636 | } |
| 1637 | |
Dave Airlie | 5dd0775 | 2016-07-05 09:43:02 +1000 | [diff] [blame] | 1638 | static void mtk_hdmi_audio_shutdown(struct device *dev, void *data) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1639 | { |
| 1640 | struct mtk_hdmi *hdmi = dev_get_drvdata(dev); |
| 1641 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1642 | mtk_hdmi_audio_disable(hdmi); |
| 1643 | } |
| 1644 | |
Baoyou Xie | 188af07 | 2016-09-25 15:38:29 +0800 | [diff] [blame] | 1645 | static int |
| 1646 | mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1647 | { |
| 1648 | struct mtk_hdmi *hdmi = dev_get_drvdata(dev); |
| 1649 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1650 | if (enable) |
| 1651 | mtk_hdmi_hw_aud_mute(hdmi); |
| 1652 | else |
| 1653 | mtk_hdmi_hw_aud_unmute(hdmi); |
| 1654 | |
| 1655 | return 0; |
| 1656 | } |
| 1657 | |
Dave Airlie | 5dd0775 | 2016-07-05 09:43:02 +1000 | [diff] [blame] | 1658 | static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1659 | { |
| 1660 | struct mtk_hdmi *hdmi = dev_get_drvdata(dev); |
| 1661 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1662 | memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len)); |
| 1663 | |
| 1664 | return 0; |
| 1665 | } |
| 1666 | |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1667 | static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data, |
| 1668 | hdmi_codec_plugged_cb fn, |
| 1669 | struct device *codec_dev) |
| 1670 | { |
| 1671 | struct mtk_hdmi *hdmi = data; |
| 1672 | |
Tzung-Bi Shih | f07980d | 2020-02-17 11:16:53 +0800 | [diff] [blame] | 1673 | mutex_lock(&hdmi->update_plugged_status_lock); |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1674 | hdmi->plugged_cb = fn; |
| 1675 | hdmi->codec_dev = codec_dev; |
Tzung-Bi Shih | f07980d | 2020-02-17 11:16:53 +0800 | [diff] [blame] | 1676 | mutex_unlock(&hdmi->update_plugged_status_lock); |
| 1677 | |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1678 | mtk_hdmi_update_plugged_status(hdmi); |
| 1679 | |
| 1680 | return 0; |
| 1681 | } |
| 1682 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1683 | static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = { |
| 1684 | .hw_params = mtk_hdmi_audio_hw_params, |
| 1685 | .audio_startup = mtk_hdmi_audio_startup, |
| 1686 | .audio_shutdown = mtk_hdmi_audio_shutdown, |
| 1687 | .digital_mute = mtk_hdmi_audio_digital_mute, |
| 1688 | .get_eld = mtk_hdmi_audio_get_eld, |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1689 | .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb, |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1690 | }; |
| 1691 | |
Tzung-Bi Shih | f9eb06c | 2020-02-06 11:17:50 +0800 | [diff] [blame] | 1692 | static int mtk_hdmi_register_audio_driver(struct device *dev) |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1693 | { |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1694 | struct mtk_hdmi *hdmi = dev_get_drvdata(dev); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1695 | struct hdmi_codec_pdata codec_data = { |
| 1696 | .ops = &mtk_hdmi_audio_codec_ops, |
| 1697 | .max_i2s_channels = 2, |
| 1698 | .i2s = 1, |
Tzung-Bi Shih | 5d3c644 | 2020-02-06 11:17:51 +0800 | [diff] [blame] | 1699 | .data = hdmi, |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1700 | }; |
| 1701 | struct platform_device *pdev; |
| 1702 | |
| 1703 | pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, |
| 1704 | PLATFORM_DEVID_AUTO, &codec_data, |
| 1705 | sizeof(codec_data)); |
| 1706 | if (IS_ERR(pdev)) |
Tzung-Bi Shih | f9eb06c | 2020-02-06 11:17:50 +0800 | [diff] [blame] | 1707 | return PTR_ERR(pdev); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1708 | |
| 1709 | DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME); |
Tzung-Bi Shih | f9eb06c | 2020-02-06 11:17:50 +0800 | [diff] [blame] | 1710 | return 0; |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1711 | } |
| 1712 | |
| 1713 | static int mtk_drm_hdmi_probe(struct platform_device *pdev) |
| 1714 | { |
| 1715 | struct mtk_hdmi *hdmi; |
| 1716 | struct device *dev = &pdev->dev; |
| 1717 | int ret; |
| 1718 | |
| 1719 | hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); |
| 1720 | if (!hdmi) |
| 1721 | return -ENOMEM; |
| 1722 | |
| 1723 | hdmi->dev = dev; |
| 1724 | |
| 1725 | ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev); |
| 1726 | if (ret) |
| 1727 | return ret; |
| 1728 | |
| 1729 | hdmi->phy = devm_phy_get(dev, "hdmi"); |
| 1730 | if (IS_ERR(hdmi->phy)) { |
| 1731 | ret = PTR_ERR(hdmi->phy); |
| 1732 | dev_err(dev, "Failed to get HDMI PHY: %d\n", ret); |
| 1733 | return ret; |
| 1734 | } |
| 1735 | |
Tzung-Bi Shih | f07980d | 2020-02-17 11:16:53 +0800 | [diff] [blame] | 1736 | mutex_init(&hdmi->update_plugged_status_lock); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1737 | platform_set_drvdata(pdev, hdmi); |
| 1738 | |
| 1739 | ret = mtk_hdmi_output_init(hdmi); |
| 1740 | if (ret) { |
| 1741 | dev_err(dev, "Failed to initialize hdmi output\n"); |
| 1742 | return ret; |
| 1743 | } |
| 1744 | |
Tzung-Bi Shih | f9eb06c | 2020-02-06 11:17:50 +0800 | [diff] [blame] | 1745 | ret = mtk_hdmi_register_audio_driver(dev); |
| 1746 | if (ret) { |
| 1747 | dev_err(dev, "Failed to register audio driver: %d\n", ret); |
| 1748 | return ret; |
| 1749 | } |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1750 | |
| 1751 | hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs; |
| 1752 | hdmi->bridge.of_node = pdev->dev.of_node; |
Inki Dae | e691009 | 2017-07-03 17:42:29 +0900 | [diff] [blame] | 1753 | drm_bridge_add(&hdmi->bridge); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1754 | |
| 1755 | ret = mtk_hdmi_clk_enable_audio(hdmi); |
| 1756 | if (ret) { |
| 1757 | dev_err(dev, "Failed to enable audio clocks: %d\n", ret); |
| 1758 | goto err_bridge_remove; |
| 1759 | } |
| 1760 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1761 | return 0; |
| 1762 | |
| 1763 | err_bridge_remove: |
| 1764 | drm_bridge_remove(&hdmi->bridge); |
| 1765 | return ret; |
| 1766 | } |
| 1767 | |
| 1768 | static int mtk_drm_hdmi_remove(struct platform_device *pdev) |
| 1769 | { |
| 1770 | struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); |
| 1771 | |
| 1772 | drm_bridge_remove(&hdmi->bridge); |
| 1773 | mtk_hdmi_clk_disable_audio(hdmi); |
| 1774 | return 0; |
| 1775 | } |
| 1776 | |
| 1777 | #ifdef CONFIG_PM_SLEEP |
| 1778 | static int mtk_hdmi_suspend(struct device *dev) |
| 1779 | { |
| 1780 | struct mtk_hdmi *hdmi = dev_get_drvdata(dev); |
| 1781 | |
| 1782 | mtk_hdmi_clk_disable_audio(hdmi); |
Enric Balletbo i Serra | 5ab546f | 2020-05-19 11:41:15 +0200 | [diff] [blame] | 1783 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1784 | return 0; |
| 1785 | } |
| 1786 | |
| 1787 | static int mtk_hdmi_resume(struct device *dev) |
| 1788 | { |
| 1789 | struct mtk_hdmi *hdmi = dev_get_drvdata(dev); |
| 1790 | int ret = 0; |
| 1791 | |
| 1792 | ret = mtk_hdmi_clk_enable_audio(hdmi); |
| 1793 | if (ret) { |
| 1794 | dev_err(dev, "hdmi resume failed!\n"); |
| 1795 | return ret; |
| 1796 | } |
| 1797 | |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1798 | return 0; |
| 1799 | } |
| 1800 | #endif |
| 1801 | static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, |
| 1802 | mtk_hdmi_suspend, mtk_hdmi_resume); |
| 1803 | |
| 1804 | static const struct of_device_id mtk_drm_hdmi_of_ids[] = { |
| 1805 | { .compatible = "mediatek,mt8173-hdmi", }, |
| 1806 | {} |
| 1807 | }; |
| 1808 | |
| 1809 | static struct platform_driver mtk_hdmi_driver = { |
| 1810 | .probe = mtk_drm_hdmi_probe, |
| 1811 | .remove = mtk_drm_hdmi_remove, |
| 1812 | .driver = { |
| 1813 | .name = "mediatek-drm-hdmi", |
| 1814 | .of_match_table = mtk_drm_hdmi_of_ids, |
| 1815 | .pm = &mtk_hdmi_pm_ops, |
| 1816 | }, |
| 1817 | }; |
| 1818 | |
| 1819 | static struct platform_driver * const mtk_hdmi_drivers[] = { |
| 1820 | &mtk_hdmi_phy_driver, |
| 1821 | &mtk_hdmi_ddc_driver, |
| 1822 | &mtk_cec_driver, |
| 1823 | &mtk_hdmi_driver, |
| 1824 | }; |
| 1825 | |
| 1826 | static int __init mtk_hdmitx_init(void) |
| 1827 | { |
Philipp Zabel | 446b8c5 | 2017-03-17 18:00:23 +0100 | [diff] [blame] | 1828 | return platform_register_drivers(mtk_hdmi_drivers, |
| 1829 | ARRAY_SIZE(mtk_hdmi_drivers)); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1830 | } |
| 1831 | |
| 1832 | static void __exit mtk_hdmitx_exit(void) |
| 1833 | { |
Philipp Zabel | 446b8c5 | 2017-03-17 18:00:23 +0100 | [diff] [blame] | 1834 | platform_unregister_drivers(mtk_hdmi_drivers, |
| 1835 | ARRAY_SIZE(mtk_hdmi_drivers)); |
Jie Qiu | 8f83f26 | 2016-01-04 18:36:38 +0100 | [diff] [blame] | 1836 | } |
| 1837 | |
| 1838 | module_init(mtk_hdmitx_init); |
| 1839 | module_exit(mtk_hdmitx_exit); |
| 1840 | |
| 1841 | MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>"); |
| 1842 | MODULE_DESCRIPTION("MediaTek HDMI Driver"); |
| 1843 | MODULE_LICENSE("GPL v2"); |