Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/mfd/mcp-sa11x0.c |
| 3 | * |
| 4 | * Copyright (C) 2001-2005 Russell King |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License. |
| 9 | * |
| 10 | * SA11x0 MCP (Multimedia Communications Port) driver. |
| 11 | * |
| 12 | * MCP read/write timeouts from Jordi Colomer, rehacked by rmk. |
| 13 | */ |
| 14 | #include <linux/module.h> |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 15 | #include <linux/io.h> |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 16 | #include <linux/errno.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/spinlock.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 20 | #include <linux/platform_device.h> |
Russell King | 2796e39 | 2012-01-21 09:34:30 +0000 | [diff] [blame] | 21 | #include <linux/pm.h> |
Thomas Kunze | c8602ed | 2009-02-10 14:54:57 +0100 | [diff] [blame] | 22 | #include <linux/mfd/mcp.h> |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 23 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 24 | #include <mach/hardware.h> |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 25 | #include <asm/mach-types.h> |
Arnd Bergmann | a1fd844 | 2012-08-24 15:17:38 +0200 | [diff] [blame] | 26 | #include <linux/platform_data/mfd-mcp-sa11x0.h> |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 27 | |
Russell King | c4592ce | 2012-01-20 22:30:15 +0000 | [diff] [blame] | 28 | #define DRIVER_NAME "sa11x0-mcp" |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 29 | |
| 30 | struct mcp_sa11x0 { |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 31 | void __iomem *base0; |
| 32 | void __iomem *base1; |
| 33 | u32 mccr0; |
| 34 | u32 mccr1; |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 35 | }; |
| 36 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 37 | /* Register offsets */ |
| 38 | #define MCCR0(m) ((m)->base0 + 0x00) |
| 39 | #define MCDR0(m) ((m)->base0 + 0x08) |
| 40 | #define MCDR1(m) ((m)->base0 + 0x0c) |
| 41 | #define MCDR2(m) ((m)->base0 + 0x10) |
| 42 | #define MCSR(m) ((m)->base0 + 0x18) |
| 43 | #define MCCR1(m) ((m)->base1 + 0x00) |
| 44 | |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 45 | #define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp)) |
| 46 | |
| 47 | static void |
| 48 | mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor) |
| 49 | { |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 50 | struct mcp_sa11x0 *m = priv(mcp); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 51 | |
| 52 | divisor /= 32; |
| 53 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 54 | m->mccr0 &= ~0x00007f00; |
| 55 | m->mccr0 |= divisor << 8; |
| 56 | writel_relaxed(m->mccr0, MCCR0(m)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | static void |
| 60 | mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor) |
| 61 | { |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 62 | struct mcp_sa11x0 *m = priv(mcp); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 63 | |
| 64 | divisor /= 32; |
| 65 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 66 | m->mccr0 &= ~0x0000007f; |
| 67 | m->mccr0 |= divisor; |
| 68 | writel_relaxed(m->mccr0, MCCR0(m)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 69 | } |
| 70 | |
| 71 | /* |
| 72 | * Write data to the device. The bit should be set after 3 subframe |
| 73 | * times (each frame is 64 clocks). We wait a maximum of 6 subframes. |
| 74 | * We really should try doing something more productive while we |
| 75 | * wait. |
| 76 | */ |
| 77 | static void |
| 78 | mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val) |
| 79 | { |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 80 | struct mcp_sa11x0 *m = priv(mcp); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 81 | int ret = -ETIME; |
| 82 | int i; |
| 83 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 84 | writel_relaxed(reg << 17 | MCDR2_Wr | (val & 0xffff), MCDR2(m)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 85 | |
| 86 | for (i = 0; i < 2; i++) { |
| 87 | udelay(mcp->rw_timeout); |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 88 | if (readl_relaxed(MCSR(m)) & MCSR_CWC) { |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 89 | ret = 0; |
| 90 | break; |
| 91 | } |
| 92 | } |
| 93 | |
| 94 | if (ret < 0) |
| 95 | printk(KERN_WARNING "mcp: write timed out\n"); |
| 96 | } |
| 97 | |
| 98 | /* |
| 99 | * Read data from the device. The bit should be set after 3 subframe |
| 100 | * times (each frame is 64 clocks). We wait a maximum of 6 subframes. |
| 101 | * We really should try doing something more productive while we |
| 102 | * wait. |
| 103 | */ |
| 104 | static unsigned int |
| 105 | mcp_sa11x0_read(struct mcp *mcp, unsigned int reg) |
| 106 | { |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 107 | struct mcp_sa11x0 *m = priv(mcp); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 108 | int ret = -ETIME; |
| 109 | int i; |
| 110 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 111 | writel_relaxed(reg << 17 | MCDR2_Rd, MCDR2(m)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 112 | |
| 113 | for (i = 0; i < 2; i++) { |
| 114 | udelay(mcp->rw_timeout); |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 115 | if (readl_relaxed(MCSR(m)) & MCSR_CRC) { |
| 116 | ret = readl_relaxed(MCDR2(m)) & 0xffff; |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 117 | break; |
| 118 | } |
| 119 | } |
| 120 | |
| 121 | if (ret < 0) |
| 122 | printk(KERN_WARNING "mcp: read timed out\n"); |
| 123 | |
| 124 | return ret; |
| 125 | } |
| 126 | |
| 127 | static void mcp_sa11x0_enable(struct mcp *mcp) |
| 128 | { |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 129 | struct mcp_sa11x0 *m = priv(mcp); |
| 130 | |
| 131 | writel(-1, MCSR(m)); |
| 132 | m->mccr0 |= MCCR0_MCE; |
| 133 | writel_relaxed(m->mccr0, MCCR0(m)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 134 | } |
| 135 | |
| 136 | static void mcp_sa11x0_disable(struct mcp *mcp) |
| 137 | { |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 138 | struct mcp_sa11x0 *m = priv(mcp); |
| 139 | |
| 140 | m->mccr0 &= ~MCCR0_MCE; |
| 141 | writel_relaxed(m->mccr0, MCCR0(m)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | /* |
| 145 | * Our methods. |
| 146 | */ |
| 147 | static struct mcp_ops mcp_sa11x0 = { |
| 148 | .set_telecom_divisor = mcp_sa11x0_set_telecom_divisor, |
| 149 | .set_audio_divisor = mcp_sa11x0_set_audio_divisor, |
| 150 | .reg_write = mcp_sa11x0_write, |
| 151 | .reg_read = mcp_sa11x0_read, |
| 152 | .enable = mcp_sa11x0_enable, |
| 153 | .disable = mcp_sa11x0_disable, |
| 154 | }; |
| 155 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 156 | static int mcp_sa11x0_probe(struct platform_device *dev) |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 157 | { |
Jingoo Han | 334a41ce | 2013-07-30 17:10:05 +0900 | [diff] [blame] | 158 | struct mcp_plat_data *data = dev_get_platdata(&dev->dev); |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 159 | struct resource *mem0, *mem1; |
| 160 | struct mcp_sa11x0 *m; |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 161 | struct mcp *mcp; |
| 162 | int ret; |
| 163 | |
Russell King | 323cdfc | 2005-08-18 10:10:46 +0100 | [diff] [blame] | 164 | if (!data) |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 165 | return -ENODEV; |
| 166 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 167 | mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0); |
| 168 | mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1); |
| 169 | if (!mem0 || !mem1) |
| 170 | return -ENXIO; |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 171 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 172 | if (!request_mem_region(mem0->start, resource_size(mem0), |
| 173 | DRIVER_NAME)) { |
| 174 | ret = -EBUSY; |
| 175 | goto err_mem0; |
| 176 | } |
| 177 | |
| 178 | if (!request_mem_region(mem1->start, resource_size(mem1), |
| 179 | DRIVER_NAME)) { |
| 180 | ret = -EBUSY; |
| 181 | goto err_mem1; |
| 182 | } |
| 183 | |
| 184 | mcp = mcp_host_alloc(&dev->dev, sizeof(struct mcp_sa11x0)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 185 | if (!mcp) { |
| 186 | ret = -ENOMEM; |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 187 | goto err_alloc; |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | mcp->owner = THIS_MODULE; |
| 191 | mcp->ops = &mcp_sa11x0; |
Russell King | 323cdfc | 2005-08-18 10:10:46 +0100 | [diff] [blame] | 192 | mcp->sclk_rate = data->sclk_rate; |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 193 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 194 | m = priv(mcp); |
| 195 | m->mccr0 = data->mccr0 | 0x7f7f; |
| 196 | m->mccr1 = data->mccr1; |
| 197 | |
| 198 | m->base0 = ioremap(mem0->start, resource_size(mem0)); |
| 199 | m->base1 = ioremap(mem1->start, resource_size(mem1)); |
| 200 | if (!m->base0 || !m->base1) { |
| 201 | ret = -ENOMEM; |
| 202 | goto err_ioremap; |
| 203 | } |
| 204 | |
| 205 | platform_set_drvdata(dev, mcp); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 206 | |
Russell King | 216f63c | 2012-01-20 17:37:21 +0000 | [diff] [blame] | 207 | /* |
Russell King | 323cdfc | 2005-08-18 10:10:46 +0100 | [diff] [blame] | 208 | * Initialise device. Note that we initially |
| 209 | * set the sampling rate to minimum. |
| 210 | */ |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 211 | writel_relaxed(-1, MCSR(m)); |
| 212 | writel_relaxed(m->mccr1, MCCR1(m)); |
| 213 | writel_relaxed(m->mccr0, MCCR0(m)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 214 | |
| 215 | /* |
| 216 | * Calculate the read/write timeout (us) from the bit clock |
| 217 | * rate. This is the period for 3 64-bit frames. Always |
| 218 | * round this time up. |
| 219 | */ |
| 220 | mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) / |
| 221 | mcp->sclk_rate; |
| 222 | |
Russell King | abe0608 | 2012-01-20 22:13:52 +0000 | [diff] [blame] | 223 | ret = mcp_host_add(mcp, data->codec_pdata); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 224 | if (ret == 0) |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 225 | return 0; |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 226 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 227 | err_ioremap: |
| 228 | iounmap(m->base1); |
| 229 | iounmap(m->base0); |
Russell King | 30816ac | 2012-01-20 22:51:07 +0000 | [diff] [blame] | 230 | mcp_host_free(mcp); |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 231 | err_alloc: |
| 232 | release_mem_region(mem1->start, resource_size(mem1)); |
| 233 | err_mem1: |
| 234 | release_mem_region(mem0->start, resource_size(mem0)); |
| 235 | err_mem0: |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 236 | return ret; |
| 237 | } |
| 238 | |
Russell King | 216f63c | 2012-01-20 17:37:21 +0000 | [diff] [blame] | 239 | static int mcp_sa11x0_remove(struct platform_device *dev) |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 240 | { |
Russell King | 216f63c | 2012-01-20 17:37:21 +0000 | [diff] [blame] | 241 | struct mcp *mcp = platform_get_drvdata(dev); |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 242 | struct mcp_sa11x0 *m = priv(mcp); |
| 243 | struct resource *mem0, *mem1; |
| 244 | |
Russell King | a4b54ac | 2012-01-21 18:26:17 +0000 | [diff] [blame] | 245 | if (m->mccr0 & MCCR0_MCE) |
| 246 | dev_warn(&dev->dev, |
| 247 | "device left active (missing disable call?)\n"); |
| 248 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 249 | mem0 = platform_get_resource(dev, IORESOURCE_MEM, 0); |
| 250 | mem1 = platform_get_resource(dev, IORESOURCE_MEM, 1); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 251 | |
Russell King | 30816ac | 2012-01-20 22:51:07 +0000 | [diff] [blame] | 252 | mcp_host_del(mcp); |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 253 | iounmap(m->base1); |
| 254 | iounmap(m->base0); |
Russell King | 30816ac | 2012-01-20 22:51:07 +0000 | [diff] [blame] | 255 | mcp_host_free(mcp); |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 256 | release_mem_region(mem1->start, resource_size(mem1)); |
| 257 | release_mem_region(mem0->start, resource_size(mem0)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
Russell King | 2796e39 | 2012-01-21 09:34:30 +0000 | [diff] [blame] | 262 | #ifdef CONFIG_PM_SLEEP |
| 263 | static int mcp_sa11x0_suspend(struct device *dev) |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 264 | { |
Russell King | 2796e39 | 2012-01-21 09:34:30 +0000 | [diff] [blame] | 265 | struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 266 | |
Russell King | a4b54ac | 2012-01-21 18:26:17 +0000 | [diff] [blame] | 267 | if (m->mccr0 & MCCR0_MCE) |
| 268 | dev_warn(dev, "device left active (missing disable call?)\n"); |
| 269 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 270 | writel(m->mccr0 & ~MCCR0_MCE, MCCR0(m)); |
Russell King | 9480e30 | 2005-10-28 09:52:56 -0700 | [diff] [blame] | 271 | |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 272 | return 0; |
| 273 | } |
| 274 | |
Russell King | 2796e39 | 2012-01-21 09:34:30 +0000 | [diff] [blame] | 275 | static int mcp_sa11x0_resume(struct device *dev) |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 276 | { |
Russell King | 2796e39 | 2012-01-21 09:34:30 +0000 | [diff] [blame] | 277 | struct mcp_sa11x0 *m = priv(dev_get_drvdata(dev)); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 278 | |
Russell King | 45c7f75 | 2012-01-20 23:09:42 +0000 | [diff] [blame] | 279 | writel_relaxed(m->mccr1, MCCR1(m)); |
| 280 | writel_relaxed(m->mccr0, MCCR0(m)); |
Russell King | 9480e30 | 2005-10-28 09:52:56 -0700 | [diff] [blame] | 281 | |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 282 | return 0; |
| 283 | } |
Russell King | 2796e39 | 2012-01-21 09:34:30 +0000 | [diff] [blame] | 284 | #endif |
| 285 | |
| 286 | static const struct dev_pm_ops mcp_sa11x0_pm_ops = { |
Russell King | a6aecae | 2012-01-21 18:03:00 +0000 | [diff] [blame] | 287 | #ifdef CONFIG_PM_SLEEP |
| 288 | .suspend = mcp_sa11x0_suspend, |
| 289 | .freeze = mcp_sa11x0_suspend, |
| 290 | .poweroff = mcp_sa11x0_suspend, |
| 291 | .resume_noirq = mcp_sa11x0_resume, |
| 292 | .thaw_noirq = mcp_sa11x0_resume, |
| 293 | .restore_noirq = mcp_sa11x0_resume, |
| 294 | #endif |
Russell King | 2796e39 | 2012-01-21 09:34:30 +0000 | [diff] [blame] | 295 | }; |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 296 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 297 | static struct platform_driver mcp_sa11x0_driver = { |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 298 | .probe = mcp_sa11x0_probe, |
| 299 | .remove = mcp_sa11x0_remove, |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 300 | .driver = { |
Russell King | c4592ce | 2012-01-20 22:30:15 +0000 | [diff] [blame] | 301 | .name = DRIVER_NAME, |
Russell King | 2796e39 | 2012-01-21 09:34:30 +0000 | [diff] [blame] | 302 | .pm = &mcp_sa11x0_pm_ops, |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 303 | }, |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 304 | }; |
| 305 | |
| 306 | /* |
| 307 | * This needs re-working |
| 308 | */ |
Mark Brown | 65349d6 | 2011-11-23 22:58:34 +0000 | [diff] [blame] | 309 | module_platform_driver(mcp_sa11x0_driver); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 310 | |
Russell King | c4592ce | 2012-01-20 22:30:15 +0000 | [diff] [blame] | 311 | MODULE_ALIAS("platform:" DRIVER_NAME); |
Russell King | 5e742ad | 2005-08-18 10:08:15 +0100 | [diff] [blame] | 312 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
| 313 | MODULE_DESCRIPTION("SA11x0 multimedia communications port driver"); |
| 314 | MODULE_LICENSE("GPL"); |