blob: a2abfe987ab123c148c9b792ecadefa149989cf6 [file] [log] [blame]
Thomas Gleixner97fb5e82019-05-29 07:17:58 -07001// SPDX-License-Identifier: GPL-2.0-only
Bjorn Anderssonf365be02013-12-05 18:10:03 -08002/*
3 * Copyright (c) 2013, Sony Mobile Communications AB.
4 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
Bjorn Anderssonf365be02013-12-05 18:10:03 -08005 */
6
Pramod Gurav32745582014-08-29 20:00:59 +05307#include <linux/delay.h>
Bjorn Anderssonf365be02013-12-05 18:10:03 -08008#include <linux/err.h>
Bjorn Anderssonf365be02013-12-05 18:10:03 -08009#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/pinctrl/machine.h>
14#include <linux/pinctrl/pinctrl.h>
15#include <linux/pinctrl/pinmux.h>
16#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinconf-generic.h>
18#include <linux/slab.h>
Linus Walleij1c5fb662018-09-13 13:58:21 +020019#include <linux/gpio/driver.h>
Bjorn Anderssonf365be02013-12-05 18:10:03 -080020#include <linux/interrupt.h>
Bjorn Anderssonf365be02013-12-05 18:10:03 -080021#include <linux/spinlock.h>
Josh Cartwrightcf1fc182014-09-23 15:59:53 -050022#include <linux/reboot.h>
Stephen Boydad644982015-07-06 18:09:30 -070023#include <linux/pm.h>
Stephen Boyd47a01ee2016-06-25 22:21:31 -070024#include <linux/log2.h>
Ajay Kishore13bec8d2020-03-27 23:32:08 +010025#include <linux/qcom_scm.h>
Pramod Gurav32745582014-08-29 20:00:59 +053026
Lina Iyere35a6ae2019-11-15 15:11:51 -070027#include <linux/soc/qcom/irq.h>
28
Linus Walleij69b78b82014-07-09 13:55:12 +020029#include "../core.h"
30#include "../pinconf.h"
Bjorn Anderssonf365be02013-12-05 18:10:03 -080031#include "pinctrl-msm.h"
Linus Walleij69b78b82014-07-09 13:55:12 +020032#include "../pinctrl-utils.h"
Bjorn Anderssonf365be02013-12-05 18:10:03 -080033
Bjorn Andersson408e3c62013-12-14 23:01:53 -080034#define MAX_NR_GPIO 300
Bjorn Anderssona46d5e92018-09-24 15:17:46 -070035#define MAX_NR_TILES 4
Pramod Gurav32745582014-08-29 20:00:59 +053036#define PS_HOLD_OFFSET 0x820
Bjorn Andersson408e3c62013-12-14 23:01:53 -080037
Bjorn Anderssonf365be02013-12-05 18:10:03 -080038/**
39 * struct msm_pinctrl - state for a pinctrl-msm device
40 * @dev: device handle.
41 * @pctrl: pinctrl handle.
Bjorn Anderssonf365be02013-12-05 18:10:03 -080042 * @chip: gpiochip handle.
Lee Jones0b33c722020-07-13 15:49:10 +010043 * @desc: pin controller descriptor
Josh Cartwrightcf1fc182014-09-23 15:59:53 -050044 * @restart_nb: restart notifier block.
Bjorn Anderssonf365be02013-12-05 18:10:03 -080045 * @irq: parent irq for the TLMM irq_chip.
Lee Jones0b33c722020-07-13 15:49:10 +010046 * @intr_target_use_scm: route irq to application cpu using scm calls
Bjorn Anderssonf365be02013-12-05 18:10:03 -080047 * @lock: Spinlock to protect register resources as well
48 * as msm_pinctrl data structures.
49 * @enabled_irqs: Bitmap of currently enabled irqs.
50 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
51 * detection.
Lina Iyere35a6ae2019-11-15 15:11:51 -070052 * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
Douglas Andersoncf9d0522021-01-14 19:16:24 -080053 * @disabled_for_mux: These IRQs were disabled because we muxed away.
Lee Jones0b33c722020-07-13 15:49:10 +010054 * @soc: Reference to soc_data of platform specific data.
Bjorn Anderssona46d5e92018-09-24 15:17:46 -070055 * @regs: Base addresses for the TLMM tiles.
Lee Jones0b33c722020-07-13 15:49:10 +010056 * @phys_base: Physical base address
Bjorn Anderssonf365be02013-12-05 18:10:03 -080057 */
58struct msm_pinctrl {
59 struct device *dev;
60 struct pinctrl_dev *pctrl;
Bjorn Anderssonf365be02013-12-05 18:10:03 -080061 struct gpio_chip chip;
Timur Tabif265e8b2018-04-25 17:43:26 -050062 struct pinctrl_desc desc;
Josh Cartwrightcf1fc182014-09-23 15:59:53 -050063 struct notifier_block restart_nb;
Timur Tabif265e8b2018-04-25 17:43:26 -050064
Bjorn Anderssonf393e482013-12-14 23:01:52 -080065 int irq;
Bjorn Anderssonf365be02013-12-05 18:10:03 -080066
Ajay Kishore13bec8d2020-03-27 23:32:08 +010067 bool intr_target_use_scm;
68
Julia Cartwright47b03ca2017-01-20 10:13:47 -060069 raw_spinlock_t lock;
Bjorn Anderssonf365be02013-12-05 18:10:03 -080070
Bjorn Andersson408e3c62013-12-14 23:01:53 -080071 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
72 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
Lina Iyere35a6ae2019-11-15 15:11:51 -070073 DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
Douglas Andersoncf9d0522021-01-14 19:16:24 -080074 DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO);
Bjorn Anderssonf365be02013-12-05 18:10:03 -080075
76 const struct msm_pinctrl_soc_data *soc;
Bjorn Anderssona46d5e92018-09-24 15:17:46 -070077 void __iomem *regs[MAX_NR_TILES];
Ajay Kishore13bec8d2020-03-27 23:32:08 +010078 u32 phys_base[MAX_NR_TILES];
Bjorn Anderssonf365be02013-12-05 18:10:03 -080079};
80
Bjorn Andersson6c736982018-09-24 15:17:45 -070081#define MSM_ACCESSOR(name) \
82static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
83 const struct msm_pingroup *g) \
84{ \
Bjorn Anderssona46d5e92018-09-24 15:17:46 -070085 return readl(pctrl->regs[g->tile] + g->name##_reg); \
Bjorn Andersson6c736982018-09-24 15:17:45 -070086} \
87static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
88 const struct msm_pingroup *g) \
89{ \
Bjorn Anderssona46d5e92018-09-24 15:17:46 -070090 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
Bjorn Andersson6c736982018-09-24 15:17:45 -070091}
92
93MSM_ACCESSOR(ctl)
94MSM_ACCESSOR(io)
95MSM_ACCESSOR(intr_cfg)
96MSM_ACCESSOR(intr_status)
97MSM_ACCESSOR(intr_target)
98
Douglas Andersona95881d2021-01-14 19:16:23 -080099static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
100 const struct msm_pingroup *g)
101{
102 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
103
104 msm_writel_intr_status(val, pctrl, g);
105}
106
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800107static int msm_get_groups_count(struct pinctrl_dev *pctldev)
108{
109 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
110
111 return pctrl->soc->ngroups;
112}
113
114static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
115 unsigned group)
116{
117 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
118
119 return pctrl->soc->groups[group].name;
120}
121
122static int msm_get_group_pins(struct pinctrl_dev *pctldev,
123 unsigned group,
124 const unsigned **pins,
125 unsigned *num_pins)
126{
127 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
128
129 *pins = pctrl->soc->groups[group].pins;
130 *num_pins = pctrl->soc->groups[group].npins;
131 return 0;
132}
133
Bjorn Andersson1f2b2392013-12-14 23:01:51 -0800134static const struct pinctrl_ops msm_pinctrl_ops = {
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800135 .get_groups_count = msm_get_groups_count,
136 .get_group_name = msm_get_group_name,
137 .get_group_pins = msm_get_group_pins,
138 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
Irina Tirdead32f7fd2016-03-31 14:44:42 +0300139 .dt_free_map = pinctrl_utils_free_map,
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800140};
141
Stephen Boyd691bf5d2018-03-23 09:34:53 -0700142static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
143{
144 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
145 struct gpio_chip *chip = &pctrl->chip;
146
147 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
148}
149
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800150static int msm_get_functions_count(struct pinctrl_dev *pctldev)
151{
152 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
153
154 return pctrl->soc->nfunctions;
155}
156
157static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
158 unsigned function)
159{
160 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
161
162 return pctrl->soc->functions[function].name;
163}
164
165static int msm_get_function_groups(struct pinctrl_dev *pctldev,
166 unsigned function,
167 const char * const **groups,
168 unsigned * const num_groups)
169{
170 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
171
172 *groups = pctrl->soc->functions[function].groups;
173 *num_groups = pctrl->soc->functions[function].ngroups;
174 return 0;
175}
176
Linus Walleij03e9f0c2014-09-03 13:02:56 +0200177static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
178 unsigned function,
179 unsigned group)
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800180{
181 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
Douglas Andersoncf9d0522021-01-14 19:16:24 -0800182 struct gpio_chip *gc = &pctrl->chip;
183 unsigned int irq = irq_find_mapping(gc->irq.domain, group);
184 struct irq_data *d = irq_get_irq_data(irq);
185 unsigned int gpio_func = pctrl->soc->gpio_func;
Prasad Sodagudibebc49c2021-11-16 11:08:03 +0530186 unsigned int egpio_func = pctrl->soc->egpio_func;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800187 const struct msm_pingroup *g;
188 unsigned long flags;
Stephen Boyd47a01ee2016-06-25 22:21:31 -0700189 u32 val, mask;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800190 int i;
191
192 g = &pctrl->soc->groups[group];
Stephen Boyd47a01ee2016-06-25 22:21:31 -0700193 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800194
Bjorn Andersson3c253812014-03-31 14:49:55 -0700195 for (i = 0; i < g->nfuncs; i++) {
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800196 if (g->funcs[i] == function)
197 break;
198 }
199
Bjorn Andersson3c253812014-03-31 14:49:55 -0700200 if (WARN_ON(i == g->nfuncs))
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800201 return -EINVAL;
202
Douglas Andersoncf9d0522021-01-14 19:16:24 -0800203 /*
204 * If an GPIO interrupt is setup on this pin then we need special
205 * handling. Specifically interrupt detection logic will still see
206 * the pin twiddle even when we're muxed away.
207 *
208 * When we see a pin with an interrupt setup on it then we'll disable
209 * (mask) interrupts on it when we mux away until we mux back. Note
210 * that disable_irq() refcounts and interrupts are disabled as long as
211 * at least one disable_irq() has been called.
212 */
213 if (d && i != gpio_func &&
214 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
215 disable_irq(irq);
216
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600217 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800218
Bjorn Andersson6c736982018-09-24 15:17:45 -0700219 val = msm_readl_ctl(pctrl, g);
Prasad Sodagudibebc49c2021-11-16 11:08:03 +0530220
221 if (egpio_func && i == egpio_func) {
222 if (val & BIT(g->egpio_present))
223 val &= ~BIT(g->egpio_enable);
224 } else {
225 val &= ~mask;
226 val |= i << g->mux_bit;
227 /* Claim ownership of pin if egpio capable */
228 if (egpio_func && val & BIT(g->egpio_present))
229 val |= BIT(g->egpio_enable);
230 }
231
Bjorn Andersson6c736982018-09-24 15:17:45 -0700232 msm_writel_ctl(val, pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800233
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600234 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800235
Douglas Andersoncf9d0522021-01-14 19:16:24 -0800236 if (d && i == gpio_func &&
237 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
238 /*
239 * Clear interrupts detected while not GPIO since we only
240 * masked things.
241 */
242 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
243 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
244 else
245 msm_ack_intr_status(pctrl, g);
246
247 enable_irq(irq);
248 }
249
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800250 return 0;
251}
252
Stephen Boyd1de7ddb2018-08-16 13:06:47 -0700253static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
254 struct pinctrl_gpio_range *range,
255 unsigned offset)
256{
257 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
258 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
259
260 /* No funcs? Probably ACPI so can't do anything here */
261 if (!g->nfuncs)
262 return 0;
263
Douglas Andersona82e5372021-01-14 19:16:21 -0800264 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
Stephen Boyd1de7ddb2018-08-16 13:06:47 -0700265}
266
Bjorn Andersson1f2b2392013-12-14 23:01:51 -0800267static const struct pinmux_ops msm_pinmux_ops = {
Stephen Boyd691bf5d2018-03-23 09:34:53 -0700268 .request = msm_pinmux_request,
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800269 .get_functions_count = msm_get_functions_count,
270 .get_function_name = msm_get_function_name,
271 .get_function_groups = msm_get_function_groups,
Stephen Boyd1de7ddb2018-08-16 13:06:47 -0700272 .gpio_request_enable = msm_pinmux_request_gpio,
Linus Walleij03e9f0c2014-09-03 13:02:56 +0200273 .set_mux = msm_pinmux_set_mux,
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800274};
275
276static int msm_config_reg(struct msm_pinctrl *pctrl,
277 const struct msm_pingroup *g,
278 unsigned param,
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800279 unsigned *mask,
280 unsigned *bit)
281{
282 switch (param) {
283 case PIN_CONFIG_BIAS_DISABLE:
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800284 case PIN_CONFIG_BIAS_PULL_DOWN:
Andy Grossb831a152014-06-17 23:49:11 -0500285 case PIN_CONFIG_BIAS_BUS_HOLD:
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800286 case PIN_CONFIG_BIAS_PULL_UP:
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800287 *bit = g->pull_bit;
288 *mask = 3;
289 break;
Jaiganesh Narayanan13355ca2020-07-03 01:06:45 -0700290 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
291 *bit = g->od_bit;
292 *mask = 1;
293 break;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800294 case PIN_CONFIG_DRIVE_STRENGTH:
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800295 *bit = g->drv_bit;
296 *mask = 7;
297 break;
Bjorn Anderssoned118a52014-02-04 19:55:31 -0800298 case PIN_CONFIG_OUTPUT:
Stanimir Varbanov407f5e32015-03-04 12:41:57 +0200299 case PIN_CONFIG_INPUT_ENABLE:
Bjorn Anderssoned118a52014-02-04 19:55:31 -0800300 *bit = g->oe_bit;
301 *mask = 1;
302 break;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800303 default:
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800304 return -ENOTSUPP;
305 }
306
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800307 return 0;
308}
309
Ram Chandra Jangir83cf5fa2017-07-14 16:14:11 +0200310#define MSM_NO_PULL 0
311#define MSM_PULL_DOWN 1
312#define MSM_KEEPER 2
313#define MSM_PULL_UP_NO_KEEPER 2
314#define MSM_PULL_UP 3
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800315
Stephen Boyd7cc34e22014-03-06 22:44:44 -0800316static unsigned msm_regval_to_drive(u32 val)
317{
318 return (val + 1) * 2;
319}
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800320
321static int msm_config_group_get(struct pinctrl_dev *pctldev,
322 unsigned int group,
323 unsigned long *config)
324{
325 const struct msm_pingroup *g;
326 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
327 unsigned param = pinconf_to_config_param(*config);
328 unsigned mask;
329 unsigned arg;
330 unsigned bit;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800331 int ret;
332 u32 val;
333
334 g = &pctrl->soc->groups[group];
335
Stephen Boyd051a58b2014-03-06 22:44:46 -0800336 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800337 if (ret < 0)
338 return ret;
339
Bjorn Andersson6c736982018-09-24 15:17:45 -0700340 val = msm_readl_ctl(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800341 arg = (val >> bit) & mask;
342
343 /* Convert register value to pinconf value */
344 switch (param) {
345 case PIN_CONFIG_BIAS_DISABLE:
Douglas Anderson05e0c822018-07-02 15:59:38 -0700346 if (arg != MSM_NO_PULL)
347 return -EINVAL;
348 arg = 1;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800349 break;
350 case PIN_CONFIG_BIAS_PULL_DOWN:
Douglas Anderson05e0c822018-07-02 15:59:38 -0700351 if (arg != MSM_PULL_DOWN)
352 return -EINVAL;
353 arg = 1;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800354 break;
Andy Grossb831a152014-06-17 23:49:11 -0500355 case PIN_CONFIG_BIAS_BUS_HOLD:
Ram Chandra Jangir83cf5fa2017-07-14 16:14:11 +0200356 if (pctrl->soc->pull_no_keeper)
357 return -ENOTSUPP;
358
Douglas Anderson05e0c822018-07-02 15:59:38 -0700359 if (arg != MSM_KEEPER)
360 return -EINVAL;
361 arg = 1;
Andy Grossb831a152014-06-17 23:49:11 -0500362 break;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800363 case PIN_CONFIG_BIAS_PULL_UP:
Ram Chandra Jangir83cf5fa2017-07-14 16:14:11 +0200364 if (pctrl->soc->pull_no_keeper)
365 arg = arg == MSM_PULL_UP_NO_KEEPER;
366 else
367 arg = arg == MSM_PULL_UP;
Douglas Anderson05e0c822018-07-02 15:59:38 -0700368 if (!arg)
369 return -EINVAL;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800370 break;
Jaiganesh Narayanan13355ca2020-07-03 01:06:45 -0700371 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
372 /* Pin is not open-drain */
373 if (!arg)
374 return -EINVAL;
375 arg = 1;
376 break;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800377 case PIN_CONFIG_DRIVE_STRENGTH:
Stephen Boyd7cc34e22014-03-06 22:44:44 -0800378 arg = msm_regval_to_drive(arg);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800379 break;
Bjorn Anderssoned118a52014-02-04 19:55:31 -0800380 case PIN_CONFIG_OUTPUT:
381 /* Pin is not output */
382 if (!arg)
383 return -EINVAL;
384
Bjorn Andersson6c736982018-09-24 15:17:45 -0700385 val = msm_readl_io(pctrl, g);
Bjorn Anderssoned118a52014-02-04 19:55:31 -0800386 arg = !!(val & BIT(g->in_bit));
387 break;
Stanimir Varbanov407f5e32015-03-04 12:41:57 +0200388 case PIN_CONFIG_INPUT_ENABLE:
389 /* Pin is output */
390 if (arg)
391 return -EINVAL;
392 arg = 1;
393 break;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800394 default:
Stanimir Varbanov38d756a2015-03-04 12:41:56 +0200395 return -ENOTSUPP;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800396 }
397
398 *config = pinconf_to_config_packed(param, arg);
399
400 return 0;
401}
402
403static int msm_config_group_set(struct pinctrl_dev *pctldev,
404 unsigned group,
405 unsigned long *configs,
406 unsigned num_configs)
407{
408 const struct msm_pingroup *g;
409 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
410 unsigned long flags;
411 unsigned param;
412 unsigned mask;
413 unsigned arg;
414 unsigned bit;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800415 int ret;
416 u32 val;
417 int i;
418
419 g = &pctrl->soc->groups[group];
420
421 for (i = 0; i < num_configs; i++) {
422 param = pinconf_to_config_param(configs[i]);
423 arg = pinconf_to_config_argument(configs[i]);
424
Stephen Boyd051a58b2014-03-06 22:44:46 -0800425 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800426 if (ret < 0)
427 return ret;
428
429 /* Convert pinconf values to register values */
430 switch (param) {
431 case PIN_CONFIG_BIAS_DISABLE:
432 arg = MSM_NO_PULL;
433 break;
434 case PIN_CONFIG_BIAS_PULL_DOWN:
435 arg = MSM_PULL_DOWN;
436 break;
Andy Grossb831a152014-06-17 23:49:11 -0500437 case PIN_CONFIG_BIAS_BUS_HOLD:
Ram Chandra Jangir83cf5fa2017-07-14 16:14:11 +0200438 if (pctrl->soc->pull_no_keeper)
439 return -ENOTSUPP;
440
Andy Grossb831a152014-06-17 23:49:11 -0500441 arg = MSM_KEEPER;
442 break;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800443 case PIN_CONFIG_BIAS_PULL_UP:
Ram Chandra Jangir83cf5fa2017-07-14 16:14:11 +0200444 if (pctrl->soc->pull_no_keeper)
445 arg = MSM_PULL_UP_NO_KEEPER;
446 else
447 arg = MSM_PULL_UP;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800448 break;
Jaiganesh Narayanan13355ca2020-07-03 01:06:45 -0700449 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
450 arg = 1;
451 break;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800452 case PIN_CONFIG_DRIVE_STRENGTH:
453 /* Check for invalid values */
Stephen Boyd7cc34e22014-03-06 22:44:44 -0800454 if (arg > 16 || arg < 2 || (arg % 2) != 0)
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800455 arg = -1;
456 else
Stephen Boyd7cc34e22014-03-06 22:44:44 -0800457 arg = (arg / 2) - 1;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800458 break;
Bjorn Anderssoned118a52014-02-04 19:55:31 -0800459 case PIN_CONFIG_OUTPUT:
460 /* set output value */
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600461 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Andersson6c736982018-09-24 15:17:45 -0700462 val = msm_readl_io(pctrl, g);
Bjorn Anderssoned118a52014-02-04 19:55:31 -0800463 if (arg)
464 val |= BIT(g->out_bit);
465 else
466 val &= ~BIT(g->out_bit);
Bjorn Andersson6c736982018-09-24 15:17:45 -0700467 msm_writel_io(val, pctrl, g);
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600468 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssoned118a52014-02-04 19:55:31 -0800469
470 /* enable output */
471 arg = 1;
472 break;
Stanimir Varbanov407f5e32015-03-04 12:41:57 +0200473 case PIN_CONFIG_INPUT_ENABLE:
474 /* disable output */
475 arg = 0;
476 break;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800477 default:
478 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
479 param);
480 return -EINVAL;
481 }
482
483 /* Range-check user-supplied value */
484 if (arg & ~mask) {
485 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
486 return -EINVAL;
487 }
488
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600489 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Andersson6c736982018-09-24 15:17:45 -0700490 val = msm_readl_ctl(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800491 val &= ~(mask << bit);
492 val |= arg << bit;
Bjorn Andersson6c736982018-09-24 15:17:45 -0700493 msm_writel_ctl(val, pctrl, g);
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600494 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800495 }
496
497 return 0;
498}
499
Bjorn Andersson1f2b2392013-12-14 23:01:51 -0800500static const struct pinconf_ops msm_pinconf_ops = {
Stanimir Varbanov38d756a2015-03-04 12:41:56 +0200501 .is_generic = true,
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800502 .pin_config_group_get = msm_config_group_get,
503 .pin_config_group_set = msm_config_group_set,
504};
505
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800506static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
507{
508 const struct msm_pingroup *g;
Linus Walleijfded3f42015-12-08 09:49:18 +0100509 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800510 unsigned long flags;
511 u32 val;
512
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800513 g = &pctrl->soc->groups[offset];
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800514
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600515 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800516
Bjorn Andersson6c736982018-09-24 15:17:45 -0700517 val = msm_readl_ctl(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800518 val &= ~BIT(g->oe_bit);
Bjorn Andersson6c736982018-09-24 15:17:45 -0700519 msm_writel_ctl(val, pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800520
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600521 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800522
523 return 0;
524}
525
526static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
527{
528 const struct msm_pingroup *g;
Linus Walleijfded3f42015-12-08 09:49:18 +0100529 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800530 unsigned long flags;
531 u32 val;
532
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800533 g = &pctrl->soc->groups[offset];
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800534
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600535 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800536
Bjorn Andersson6c736982018-09-24 15:17:45 -0700537 val = msm_readl_io(pctrl, g);
Axel Line476e772013-12-13 21:35:55 +0800538 if (value)
539 val |= BIT(g->out_bit);
540 else
541 val &= ~BIT(g->out_bit);
Bjorn Andersson6c736982018-09-24 15:17:45 -0700542 msm_writel_io(val, pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800543
Bjorn Andersson6c736982018-09-24 15:17:45 -0700544 val = msm_readl_ctl(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800545 val |= BIT(g->oe_bit);
Bjorn Andersson6c736982018-09-24 15:17:45 -0700546 msm_writel_ctl(val, pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800547
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600548 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800549
550 return 0;
551}
552
Timur Tabi8e515332017-02-10 17:21:00 -0600553static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
554{
555 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
556 const struct msm_pingroup *g;
557 u32 val;
558
559 g = &pctrl->soc->groups[offset];
560
Bjorn Andersson6c736982018-09-24 15:17:45 -0700561 val = msm_readl_ctl(pctrl, g);
Timur Tabi8e515332017-02-10 17:21:00 -0600562
Matti Vaittinen3c827872020-02-14 15:57:12 +0200563 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
564 GPIO_LINE_DIRECTION_IN;
Timur Tabi8e515332017-02-10 17:21:00 -0600565}
566
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800567static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
568{
569 const struct msm_pingroup *g;
Linus Walleijfded3f42015-12-08 09:49:18 +0100570 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800571 u32 val;
572
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800573 g = &pctrl->soc->groups[offset];
574
Bjorn Andersson6c736982018-09-24 15:17:45 -0700575 val = msm_readl_io(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800576 return !!(val & BIT(g->in_bit));
577}
578
579static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
580{
581 const struct msm_pingroup *g;
Linus Walleijfded3f42015-12-08 09:49:18 +0100582 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800583 unsigned long flags;
584 u32 val;
585
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800586 g = &pctrl->soc->groups[offset];
587
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600588 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800589
Bjorn Andersson6c736982018-09-24 15:17:45 -0700590 val = msm_readl_io(pctrl, g);
Axel Line476e772013-12-13 21:35:55 +0800591 if (value)
592 val |= BIT(g->out_bit);
593 else
594 val &= ~BIT(g->out_bit);
Bjorn Andersson6c736982018-09-24 15:17:45 -0700595 msm_writel_io(val, pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800596
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600597 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800598}
599
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800600#ifdef CONFIG_DEBUG_FS
601#include <linux/seq_file.h>
602
603static void msm_gpio_dbg_show_one(struct seq_file *s,
604 struct pinctrl_dev *pctldev,
605 struct gpio_chip *chip,
606 unsigned offset,
607 unsigned gpio)
608{
609 const struct msm_pingroup *g;
Linus Walleijfded3f42015-12-08 09:49:18 +0100610 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800611 unsigned func;
612 int is_out;
613 int drive;
614 int pull;
Stephen Boyd59a18c242018-05-07 17:15:23 -0700615 int val;
Jonathan Marek06e12b72022-02-10 08:12:09 -0500616 int egpio_enable;
Stephen Boyd59a18c242018-05-07 17:15:23 -0700617 u32 ctl_reg, io_reg;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800618
Clément Péron53e73a22018-05-04 16:57:28 -0700619 static const char * const pulls_keeper[] = {
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800620 "no pull",
621 "pull down",
622 "keeper",
623 "pull up"
624 };
625
Clément Péron53e73a22018-05-04 16:57:28 -0700626 static const char * const pulls_no_keeper[] = {
627 "no pull",
628 "pull down",
629 "pull up",
630 };
631
Stephen Boyd691bf5d2018-03-23 09:34:53 -0700632 if (!gpiochip_line_is_valid(chip, offset))
633 return;
634
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800635 g = &pctrl->soc->groups[offset];
Bjorn Andersson6c736982018-09-24 15:17:45 -0700636 ctl_reg = msm_readl_ctl(pctrl, g);
637 io_reg = msm_readl_io(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800638
639 is_out = !!(ctl_reg & BIT(g->oe_bit));
640 func = (ctl_reg >> g->mux_bit) & 7;
641 drive = (ctl_reg >> g->drv_bit) & 7;
642 pull = (ctl_reg >> g->pull_bit) & 3;
Jonathan Marek06e12b72022-02-10 08:12:09 -0500643 egpio_enable = 0;
644 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present))
645 egpio_enable = !(ctl_reg & BIT(g->egpio_enable));
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800646
Stephen Boyd59a18c242018-05-07 17:15:23 -0700647 if (is_out)
648 val = !!(io_reg & BIT(g->out_bit));
649 else
650 val = !!(io_reg & BIT(g->in_bit));
651
Jonathan Marek06e12b72022-02-10 08:12:09 -0500652 if (egpio_enable) {
653 seq_printf(s, " %-8s: egpio\n", g->name);
654 return;
655 }
656
Stephen Boyd59a18c242018-05-07 17:15:23 -0700657 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
658 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
Stephen Boyd7cc34e22014-03-06 22:44:44 -0800659 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
Clément Péron53e73a22018-05-04 16:57:28 -0700660 if (pctrl->soc->pull_no_keeper)
661 seq_printf(s, " %s", pulls_no_keeper[pull]);
662 else
663 seq_printf(s, " %s", pulls_keeper[pull]);
Stephen Boyd691bf5d2018-03-23 09:34:53 -0700664 seq_puts(s, "\n");
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800665}
666
667static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
668{
669 unsigned gpio = chip->base;
670 unsigned i;
671
Stephen Boyd691bf5d2018-03-23 09:34:53 -0700672 for (i = 0; i < chip->ngpio; i++, gpio++)
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800673 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800674}
675
676#else
677#define msm_gpio_dbg_show NULL
678#endif
679
Linus Walleijc9fc5af2019-08-19 10:49:04 +0200680static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
681 unsigned long *valid_mask,
682 unsigned int ngpios)
Ricardo Ribalda Delgado6f0ec092018-10-05 08:52:59 +0200683{
Linus Walleijc9fc5af2019-08-19 10:49:04 +0200684 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
Ricardo Ribalda Delgado6f0ec092018-10-05 08:52:59 +0200685 int ret;
686 unsigned int len, i;
Lee Jones4c0efbf2019-06-10 09:42:08 +0100687 const int *reserved = pctrl->soc->reserved_gpios;
Ricardo Ribalda Delgado6f0ec092018-10-05 08:52:59 +0200688 u16 *tmp;
689
Lee Jones4c0efbf2019-06-10 09:42:08 +0100690 /* Driver provided reserved list overrides DT and ACPI */
691 if (reserved) {
Linus Walleijc9fc5af2019-08-19 10:49:04 +0200692 bitmap_fill(valid_mask, ngpios);
Lee Jones4c0efbf2019-06-10 09:42:08 +0100693 for (i = 0; reserved[i] >= 0; i++) {
Linus Walleijc9fc5af2019-08-19 10:49:04 +0200694 if (i >= ngpios || reserved[i] >= ngpios) {
Lee Jones4c0efbf2019-06-10 09:42:08 +0100695 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
696 return -EINVAL;
697 }
Linus Walleijc9fc5af2019-08-19 10:49:04 +0200698 clear_bit(reserved[i], valid_mask);
Lee Jones4c0efbf2019-06-10 09:42:08 +0100699 }
700
701 return 0;
702 }
703
Ricardo Ribalda Delgado6f0ec092018-10-05 08:52:59 +0200704 /* The number of GPIOs in the ACPI tables */
Andy Shevchenko720b8ec2019-07-23 22:27:37 +0300705 len = ret = device_property_count_u16(pctrl->dev, "gpios");
Ricardo Ribalda Delgado6f0ec092018-10-05 08:52:59 +0200706 if (ret < 0)
707 return 0;
708
Linus Walleijc9fc5af2019-08-19 10:49:04 +0200709 if (ret > ngpios)
Ricardo Ribalda Delgado6f0ec092018-10-05 08:52:59 +0200710 return -EINVAL;
711
712 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
713 if (!tmp)
714 return -ENOMEM;
715
716 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
717 if (ret < 0) {
718 dev_err(pctrl->dev, "could not read list of GPIOs\n");
719 goto out;
720 }
721
Linus Walleijc9fc5af2019-08-19 10:49:04 +0200722 bitmap_zero(valid_mask, ngpios);
Ricardo Ribalda Delgado6f0ec092018-10-05 08:52:59 +0200723 for (i = 0; i < len; i++)
Linus Walleijc9fc5af2019-08-19 10:49:04 +0200724 set_bit(tmp[i], valid_mask);
Ricardo Ribalda Delgado6f0ec092018-10-05 08:52:59 +0200725
726out:
727 kfree(tmp);
728 return ret;
729}
730
Gustavo A. R. Silva12cb90ba2017-07-11 13:34:14 -0500731static const struct gpio_chip msm_gpio_template = {
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800732 .direction_input = msm_gpio_direction_input,
733 .direction_output = msm_gpio_direction_output,
Timur Tabi8e515332017-02-10 17:21:00 -0600734 .get_direction = msm_gpio_get_direction,
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800735 .get = msm_gpio_get,
736 .set = msm_gpio_set,
Jonas Gorski98c85d52015-10-11 17:34:19 +0200737 .request = gpiochip_generic_request,
738 .free = gpiochip_generic_free,
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800739 .dbg_show = msm_gpio_dbg_show,
740};
741
742/* For dual-edge interrupts in software, since some hardware has no
743 * such support:
744 *
745 * At appropriate moments, this function may be called to flip the polarity
746 * settings of both-edge irq lines to try and catch the next edge.
747 *
748 * The attempt is considered successful if:
749 * - the status bit goes high, indicating that an edge was caught, or
750 * - the input value of the gpio doesn't change during the attempt.
751 * If the value changes twice during the process, that would cause the first
752 * test to fail but would force the second, as two opposite
753 * transitions would cause a detection no matter the polarity setting.
754 *
755 * The do-loop tries to sledge-hammer closed the timing hole between
756 * the initial value-read and the polarity-write - if the line value changes
757 * during that window, an interrupt is lost, the new polarity setting is
758 * incorrect, and the first success test will fail, causing a retry.
759 *
760 * Algorithm comes from Google's msmgpio driver.
761 */
762static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
763 const struct msm_pingroup *g,
764 struct irq_data *d)
765{
766 int loop_limit = 100;
767 unsigned val, val2, intstat;
768 unsigned pol;
769
770 do {
Bjorn Andersson6c736982018-09-24 15:17:45 -0700771 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800772
Bjorn Andersson6c736982018-09-24 15:17:45 -0700773 pol = msm_readl_intr_cfg(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800774 pol ^= BIT(g->intr_polarity_bit);
Ansuel Smith90bcb0c2020-04-14 02:37:26 +0200775 msm_writel_intr_cfg(pol, pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800776
Bjorn Andersson6c736982018-09-24 15:17:45 -0700777 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
778 intstat = msm_readl_intr_status(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800779 if (intstat || (val == val2))
780 return;
781 } while (loop_limit-- > 0);
782 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
783 val, val2);
784}
785
786static void msm_gpio_irq_mask(struct irq_data *d)
787{
Linus Walleijcdcb0ab2014-04-29 11:00:40 -0700788 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijfded3f42015-12-08 09:49:18 +0100789 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800790 const struct msm_pingroup *g;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800791 unsigned long flags;
792 u32 val;
793
Lina Iyere35a6ae2019-11-15 15:11:51 -0700794 if (d->parent_data)
795 irq_chip_mask_parent(d);
796
797 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
798 return;
799
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800800 g = &pctrl->soc->groups[d->hwirq];
801
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600802 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800803
Bjorn Andersson6c736982018-09-24 15:17:45 -0700804 val = msm_readl_intr_cfg(pctrl, g);
Stephen Boydb55326d2018-08-16 13:06:46 -0700805 /*
806 * There are two bits that control interrupt forwarding to the CPU. The
807 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
808 * latched into the interrupt status register when the hardware detects
809 * an irq that it's configured for (either edge for edge type or level
810 * for level type irq). The 'non-raw' status enable bit causes the
811 * hardware to assert the summary interrupt to the CPU if the latched
812 * status bit is set. There's a bug though, the edge detection logic
813 * seems to have a problem where toggling the RAW_STATUS_EN bit may
814 * cause the status bit to latch spuriously when there isn't any edge
815 * so we can't touch that bit for edge type irqs and we have to keep
816 * the bit set anyway so that edges are latched while the line is masked.
817 *
818 * To make matters more complicated, leaving the RAW_STATUS_EN bit
819 * enabled all the time causes level interrupts to re-latch into the
820 * status register because the level is still present on the line after
821 * we ack it. We clear the raw status enable bit during mask here and
822 * set the bit on unmask so the interrupt can't latch into the hardware
823 * while it's masked.
824 */
825 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
826 val &= ~BIT(g->intr_raw_status_bit);
827
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800828 val &= ~BIT(g->intr_enable_bit);
Bjorn Andersson6c736982018-09-24 15:17:45 -0700829 msm_writel_intr_cfg(val, pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800830
831 clear_bit(d->hwirq, pctrl->enabled_irqs);
832
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600833 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800834}
835
Douglas Andersoncf9d0522021-01-14 19:16:24 -0800836static void msm_gpio_irq_unmask(struct irq_data *d)
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800837{
Linus Walleijcdcb0ab2014-04-29 11:00:40 -0700838 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijfded3f42015-12-08 09:49:18 +0100839 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800840 const struct msm_pingroup *g;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800841 unsigned long flags;
842 u32 val;
843
Lina Iyere35a6ae2019-11-15 15:11:51 -0700844 if (d->parent_data)
845 irq_chip_unmask_parent(d);
846
847 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
848 return;
849
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800850 g = &pctrl->soc->groups[d->hwirq];
851
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600852 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800853
Bjorn Andersson6c736982018-09-24 15:17:45 -0700854 val = msm_readl_intr_cfg(pctrl, g);
Stephen Boydb55326d2018-08-16 13:06:46 -0700855 val |= BIT(g->intr_raw_status_bit);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800856 val |= BIT(g->intr_enable_bit);
Bjorn Andersson6c736982018-09-24 15:17:45 -0700857 msm_writel_intr_cfg(val, pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800858
859 set_bit(d->hwirq, pctrl->enabled_irqs);
860
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600861 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800862}
863
Srinivas Ramana4b7618f2019-06-25 19:44:46 +0530864static void msm_gpio_irq_enable(struct irq_data *d)
865{
Maulik Shah71266d92020-11-05 13:08:04 +0530866 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
867 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
Srinivas Ramana4b7618f2019-06-25 19:44:46 +0530868
Marc Zyngier14dbe182022-04-19 15:18:43 +0100869 gpiochip_enable_irq(gc, d->hwirq);
870
Maulik Shah71266d92020-11-05 13:08:04 +0530871 if (d->parent_data)
872 irq_chip_enable_parent(d);
873
874 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
Douglas Andersoncf9d0522021-01-14 19:16:24 -0800875 msm_gpio_irq_unmask(d);
Srinivas Ramana4b7618f2019-06-25 19:44:46 +0530876}
877
Lina Iyere35a6ae2019-11-15 15:11:51 -0700878static void msm_gpio_irq_disable(struct irq_data *d)
879{
880 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
881 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
882
883 if (d->parent_data)
884 irq_chip_disable_parent(d);
885
886 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
887 msm_gpio_irq_mask(d);
Marc Zyngier14dbe182022-04-19 15:18:43 +0100888
889 gpiochip_disable_irq(gc, d->hwirq);
Lina Iyere35a6ae2019-11-15 15:11:51 -0700890}
891
Douglas Andersonc3c0c2e2020-07-14 08:04:17 -0700892/**
893 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
894 * @d: The irq dta.
895 *
896 * This is much like msm_gpio_update_dual_edge_pos() but for IRQs that are
897 * normally handled by the parent irqchip. The logic here is slightly
898 * different due to what's easy to do with our parent, but in principle it's
899 * the same.
900 */
901static void msm_gpio_update_dual_edge_parent(struct irq_data *d)
902{
903 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
904 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
905 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
906 int loop_limit = 100;
907 unsigned int val;
908 unsigned int type;
909
910 /* Read the value and make a guess about what edge we need to catch */
911 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
912 type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
913
914 do {
915 /* Set the parent to catch the next edge */
916 irq_chip_set_type_parent(d, type);
917
918 /*
919 * Possibly the line changed between when we last read "val"
920 * (and decided what edge we needed) and when set the edge.
921 * If the value didn't change (or changed and then changed
922 * back) then we're done.
923 */
924 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
925 if (type == IRQ_TYPE_EDGE_RISING) {
926 if (!val)
927 return;
928 type = IRQ_TYPE_EDGE_FALLING;
929 } else if (type == IRQ_TYPE_EDGE_FALLING) {
930 if (val)
931 return;
932 type = IRQ_TYPE_EDGE_RISING;
933 }
934 } while (loop_limit-- > 0);
935 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
936}
937
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800938static void msm_gpio_irq_ack(struct irq_data *d)
939{
Linus Walleijcdcb0ab2014-04-29 11:00:40 -0700940 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijfded3f42015-12-08 09:49:18 +0100941 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800942 const struct msm_pingroup *g;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800943 unsigned long flags;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800944
Douglas Andersonc3c0c2e2020-07-14 08:04:17 -0700945 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
946 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
947 msm_gpio_update_dual_edge_parent(d);
Lina Iyere35a6ae2019-11-15 15:11:51 -0700948 return;
Douglas Andersonc3c0c2e2020-07-14 08:04:17 -0700949 }
Lina Iyere35a6ae2019-11-15 15:11:51 -0700950
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800951 g = &pctrl->soc->groups[d->hwirq];
952
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600953 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800954
Douglas Andersona95881d2021-01-14 19:16:23 -0800955 msm_ack_intr_status(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800956
957 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
958 msm_gpio_update_dual_edge_pos(pctrl, g, d);
959
Julia Cartwright47b03ca2017-01-20 10:13:47 -0600960 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800961}
962
Marc Zyngier14dbe182022-04-19 15:18:43 +0100963static void msm_gpio_irq_eoi(struct irq_data *d)
964{
965 d = d->parent_data;
966
967 if (d)
968 d->chip->irq_eoi(d);
969}
970
Douglas Andersonc3c0c2e2020-07-14 08:04:17 -0700971static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
972 unsigned int type)
973{
974 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
975 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
976
977 return type == IRQ_TYPE_EDGE_BOTH &&
978 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
979 test_bit(d->hwirq, pctrl->skip_wake_irqs);
980}
981
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800982static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
983{
Linus Walleijcdcb0ab2014-04-29 11:00:40 -0700984 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijfded3f42015-12-08 09:49:18 +0100985 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800986 const struct msm_pingroup *g;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800987 unsigned long flags;
Douglas Andersoncf9d0522021-01-14 19:16:24 -0800988 bool was_enabled;
Bjorn Anderssonf365be02013-12-05 18:10:03 -0800989 u32 val;
990
Douglas Andersonc3c0c2e2020-07-14 08:04:17 -0700991 if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
992 set_bit(d->hwirq, pctrl->dual_edge_irqs);
993 irq_set_handler_locked(d, handle_fasteoi_ack_irq);
994 msm_gpio_update_dual_edge_parent(d);
995 return 0;
996 }
997
Lina Iyere35a6ae2019-11-15 15:11:51 -0700998 if (d->parent_data)
999 irq_chip_set_type_parent(d, type);
1000
Douglas Andersonc3c0c2e2020-07-14 08:04:17 -07001001 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
1002 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
1003 irq_set_handler_locked(d, handle_fasteoi_irq);
Lina Iyere35a6ae2019-11-15 15:11:51 -07001004 return 0;
Douglas Andersonc3c0c2e2020-07-14 08:04:17 -07001005 }
Lina Iyere35a6ae2019-11-15 15:11:51 -07001006
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001007 g = &pctrl->soc->groups[d->hwirq];
1008
Julia Cartwright47b03ca2017-01-20 10:13:47 -06001009 raw_spin_lock_irqsave(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001010
1011 /*
1012 * For hw without possibility of detecting both edges
1013 */
1014 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
1015 set_bit(d->hwirq, pctrl->dual_edge_irqs);
1016 else
1017 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
1018
Ajay Kishore13bec8d2020-03-27 23:32:08 +01001019 /* Route interrupts to application cpu.
1020 * With intr_target_use_scm interrupts are routed to
1021 * application cpu using scm calls.
1022 */
1023 if (pctrl->intr_target_use_scm) {
1024 u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
1025 int ret;
1026
1027 qcom_scm_io_readl(addr, &val);
1028
1029 val &= ~(7 << g->intr_target_bit);
1030 val |= g->intr_target_kpss_val << g->intr_target_bit;
1031
1032 ret = qcom_scm_io_writel(addr, val);
1033 if (ret)
1034 dev_err(pctrl->dev,
1035 "Failed routing %lu interrupt to Apps proc",
1036 d->hwirq);
Ajay Kishore13bec8d2020-03-27 23:32:08 +01001037 } else {
1038 val = msm_readl_intr_target(pctrl, g);
1039 val &= ~(7 << g->intr_target_bit);
1040 val |= g->intr_target_kpss_val << g->intr_target_bit;
1041 msm_writel_intr_target(val, pctrl, g);
1042 }
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001043
1044 /* Update configuration for gpio.
1045 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
1046 * internal circuitry of TLMM, toggling the RAW_STATUS
1047 * could cause the INTR_STATUS to be set for EDGE interrupts.
1048 */
Bjorn Andersson6c736982018-09-24 15:17:45 -07001049 val = msm_readl_intr_cfg(pctrl, g);
Douglas Andersoncf9d0522021-01-14 19:16:24 -08001050 was_enabled = val & BIT(g->intr_raw_status_bit);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001051 val |= BIT(g->intr_raw_status_bit);
1052 if (g->intr_detection_width == 2) {
1053 val &= ~(3 << g->intr_detection_bit);
1054 val &= ~(1 << g->intr_polarity_bit);
1055 switch (type) {
1056 case IRQ_TYPE_EDGE_RISING:
1057 val |= 1 << g->intr_detection_bit;
1058 val |= BIT(g->intr_polarity_bit);
1059 break;
1060 case IRQ_TYPE_EDGE_FALLING:
1061 val |= 2 << g->intr_detection_bit;
1062 val |= BIT(g->intr_polarity_bit);
1063 break;
1064 case IRQ_TYPE_EDGE_BOTH:
1065 val |= 3 << g->intr_detection_bit;
1066 val |= BIT(g->intr_polarity_bit);
1067 break;
1068 case IRQ_TYPE_LEVEL_LOW:
1069 break;
1070 case IRQ_TYPE_LEVEL_HIGH:
1071 val |= BIT(g->intr_polarity_bit);
1072 break;
1073 }
1074 } else if (g->intr_detection_width == 1) {
1075 val &= ~(1 << g->intr_detection_bit);
1076 val &= ~(1 << g->intr_polarity_bit);
1077 switch (type) {
1078 case IRQ_TYPE_EDGE_RISING:
1079 val |= BIT(g->intr_detection_bit);
1080 val |= BIT(g->intr_polarity_bit);
1081 break;
1082 case IRQ_TYPE_EDGE_FALLING:
1083 val |= BIT(g->intr_detection_bit);
1084 break;
1085 case IRQ_TYPE_EDGE_BOTH:
1086 val |= BIT(g->intr_detection_bit);
Bjorn Andersson48f15e92014-03-31 14:49:54 -07001087 val |= BIT(g->intr_polarity_bit);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001088 break;
1089 case IRQ_TYPE_LEVEL_LOW:
1090 break;
1091 case IRQ_TYPE_LEVEL_HIGH:
1092 val |= BIT(g->intr_polarity_bit);
1093 break;
1094 }
1095 } else {
1096 BUG();
1097 }
Bjorn Andersson6c736982018-09-24 15:17:45 -07001098 msm_writel_intr_cfg(val, pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001099
Douglas Andersoncf9d0522021-01-14 19:16:24 -08001100 /*
1101 * The first time we set RAW_STATUS_EN it could trigger an interrupt.
1102 * Clear the interrupt. This is safe because we have
1103 * IRQCHIP_SET_TYPE_MASKED.
1104 */
1105 if (!was_enabled)
1106 msm_ack_intr_status(pctrl, g);
1107
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001108 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1109 msm_gpio_update_dual_edge_pos(pctrl, g, d);
1110
Julia Cartwright47b03ca2017-01-20 10:13:47 -06001111 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001112
1113 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixner34c0ad82015-06-23 15:52:51 +02001114 irq_set_handler_locked(d, handle_level_irq);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001115 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thomas Gleixner34c0ad82015-06-23 15:52:51 +02001116 irq_set_handler_locked(d, handle_edge_irq);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001117
1118 return 0;
1119}
1120
1121static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1122{
Linus Walleijcdcb0ab2014-04-29 11:00:40 -07001123 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
Linus Walleijfded3f42015-12-08 09:49:18 +01001124 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001125
Lina Iyere35a6ae2019-11-15 15:11:51 -07001126 /*
1127 * While they may not wake up when the TLMM is powered off,
1128 * some GPIOs would like to wakeup the system from suspend
1129 * when TLMM is powered on. To allow that, enable the GPIO
1130 * summary line to be wakeup capable at GIC.
1131 */
Maulik Shahf41aaca2020-09-28 10:02:00 +05301132 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1133 return irq_chip_set_wake_parent(d, on);
Lina Iyere35a6ae2019-11-15 15:11:51 -07001134
Maulik Shahf41aaca2020-09-28 10:02:00 +05301135 return irq_set_irq_wake(pctrl->irq, on);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001136}
1137
Stephen Boydfe273122018-08-16 13:06:48 -07001138static int msm_gpio_irq_reqres(struct irq_data *d)
1139{
1140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1141 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1142 int ret;
1143
1144 if (!try_module_get(gc->owner))
1145 return -ENODEV;
1146
1147 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1148 if (ret)
1149 goto out;
1150 msm_gpio_direction_input(gc, d->hwirq);
1151
1152 if (gpiochip_lock_as_irq(gc, d->hwirq)) {
1153 dev_err(gc->parent,
1154 "unable to lock HW IRQ %lu for IRQ\n",
1155 d->hwirq);
1156 ret = -EINVAL;
1157 goto out;
1158 }
Maulik Shah71266d92020-11-05 13:08:04 +05301159
1160 /*
Douglas Andersoncf9d0522021-01-14 19:16:24 -08001161 * The disable / clear-enable workaround we do in msm_pinmux_set_mux()
1162 * only works if disable is not lazy since we only clear any bogus
1163 * interrupt in hardware. Explicitly mark the interrupt as UNLAZY.
Maulik Shah71266d92020-11-05 13:08:04 +05301164 */
Douglas Andersoncf9d0522021-01-14 19:16:24 -08001165 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
Maulik Shah71266d92020-11-05 13:08:04 +05301166
Stephen Boydfe273122018-08-16 13:06:48 -07001167 return 0;
1168out:
1169 module_put(gc->owner);
1170 return ret;
1171}
1172
1173static void msm_gpio_irq_relres(struct irq_data *d)
1174{
1175 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1176
1177 gpiochip_unlock_as_irq(gc, d->hwirq);
1178 module_put(gc->owner);
1179}
1180
Venkata Narendra Kumar Guttadca4f402020-05-01 12:00:17 +05301181static int msm_gpio_irq_set_affinity(struct irq_data *d,
1182 const struct cpumask *dest, bool force)
1183{
1184 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1185 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1186
1187 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1188 return irq_chip_set_affinity_parent(d, dest, force);
1189
Manivannan Sadhasivamb9dc88d2022-01-13 21:56:17 +05301190 return -EINVAL;
Venkata Narendra Kumar Guttadca4f402020-05-01 12:00:17 +05301191}
1192
1193static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1194{
1195 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1196 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1197
1198 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1199 return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
1200
Manivannan Sadhasivamb9dc88d2022-01-13 21:56:17 +05301201 return -EINVAL;
Venkata Narendra Kumar Guttadca4f402020-05-01 12:00:17 +05301202}
1203
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +02001204static void msm_gpio_irq_handler(struct irq_desc *desc)
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001205{
Linus Walleijcdcb0ab2014-04-29 11:00:40 -07001206 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001207 const struct msm_pingroup *g;
Linus Walleijfded3f42015-12-08 09:49:18 +01001208 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
Jiang Liu5663bb22015-06-04 12:13:16 +08001209 struct irq_chip *chip = irq_desc_get_chip(desc);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001210 int handled = 0;
1211 u32 val;
1212 int i;
1213
1214 chained_irq_enter(chip, desc);
1215
1216 /*
Bjorn Andersson1f2b2392013-12-14 23:01:51 -08001217 * Each pin has it's own IRQ status register, so use
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001218 * enabled_irq bitmap to limit the number of reads.
1219 */
1220 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1221 g = &pctrl->soc->groups[i];
Bjorn Andersson6c736982018-09-24 15:17:45 -07001222 val = msm_readl_intr_status(pctrl, g);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001223 if (val & BIT(g->intr_status_bit)) {
Marc Zyngiera9cb09b2021-05-04 17:42:18 +01001224 generic_handle_domain_irq(gc->irq.domain, i);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001225 handled++;
1226 }
1227 }
1228
Bjorn Andersson1f2b2392013-12-14 23:01:51 -08001229 /* No interrupts were flagged */
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001230 if (handled == 0)
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +02001231 handle_bad_irq(desc);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001232
1233 chained_irq_exit(chip, desc);
1234}
1235
Lina Iyere35a6ae2019-11-15 15:11:51 -07001236static int msm_gpio_wakeirq(struct gpio_chip *gc,
1237 unsigned int child,
1238 unsigned int child_type,
1239 unsigned int *parent,
1240 unsigned int *parent_type)
1241{
1242 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1243 const struct msm_gpio_wakeirq_map *map;
1244 int i;
1245
1246 *parent = GPIO_NO_WAKE_IRQ;
1247 *parent_type = IRQ_TYPE_EDGE_RISING;
1248
1249 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1250 map = &pctrl->soc->wakeirq_map[i];
1251 if (map->gpio == child) {
1252 *parent = map->wakeirq;
1253 break;
1254 }
1255 }
1256
1257 return 0;
1258}
1259
Stephen Boyd691bf5d2018-03-23 09:34:53 -07001260static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1261{
Lee Jones4c0efbf2019-06-10 09:42:08 +01001262 if (pctrl->soc->reserved_gpios)
1263 return true;
1264
Andy Shevchenko720b8ec2019-07-23 22:27:37 +03001265 return device_property_count_u16(pctrl->dev, "gpios") > 0;
Stephen Boyd691bf5d2018-03-23 09:34:53 -07001266}
1267
Marc Zyngier14dbe182022-04-19 15:18:43 +01001268static const struct irq_chip msm_gpio_irq_chip = {
1269 .name = "msmgpio",
1270 .irq_enable = msm_gpio_irq_enable,
1271 .irq_disable = msm_gpio_irq_disable,
1272 .irq_mask = msm_gpio_irq_mask,
1273 .irq_unmask = msm_gpio_irq_unmask,
1274 .irq_ack = msm_gpio_irq_ack,
1275 .irq_eoi = msm_gpio_irq_eoi,
1276 .irq_set_type = msm_gpio_irq_set_type,
1277 .irq_set_wake = msm_gpio_irq_set_wake,
1278 .irq_request_resources = msm_gpio_irq_reqres,
1279 .irq_release_resources = msm_gpio_irq_relres,
1280 .irq_set_affinity = msm_gpio_irq_set_affinity,
1281 .irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity,
1282 .flags = (IRQCHIP_MASK_ON_SUSPEND |
1283 IRQCHIP_SET_TYPE_MASKED |
1284 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND |
1285 IRQCHIP_IMMUTABLE),
1286};
1287
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001288static int msm_gpio_init(struct msm_pinctrl *pctrl)
1289{
1290 struct gpio_chip *chip;
Linus Walleij0ce242a2019-07-24 10:38:28 +02001291 struct gpio_irq_chip *girq;
Lina Iyere35a6ae2019-11-15 15:11:51 -07001292 int i, ret;
1293 unsigned gpio, ngpio = pctrl->soc->ngpios;
1294 struct device_node *np;
1295 bool skip;
Stephen Boyddcd278b2014-03-06 22:44:41 -08001296
1297 if (WARN_ON(ngpio > MAX_NR_GPIO))
1298 return -EINVAL;
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001299
1300 chip = &pctrl->chip;
Bjorn Anderssona7aa75a2018-01-28 16:59:48 -08001301 chip->base = -1;
Stephen Boyddcd278b2014-03-06 22:44:41 -08001302 chip->ngpio = ngpio;
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001303 chip->label = dev_name(pctrl->dev);
Linus Walleij58383c782015-11-04 09:56:26 +01001304 chip->parent = pctrl->dev;
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001305 chip->owner = THIS_MODULE;
Linus Walleijeb1e8bd2019-08-19 11:30:58 +02001306 if (msm_gpio_needs_valid_mask(pctrl))
1307 chip->init_valid_mask = msm_gpio_init_valid_mask;
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001308
Lina Iyere35a6ae2019-11-15 15:11:51 -07001309 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1310 if (np) {
1311 chip->irq.parent_domain = irq_find_matching_host(np,
1312 DOMAIN_BUS_WAKEUP);
1313 of_node_put(np);
1314 if (!chip->irq.parent_domain)
1315 return -EPROBE_DEFER;
1316 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
Lina Iyere35a6ae2019-11-15 15:11:51 -07001317 /*
1318 * Let's skip handling the GPIOs, if the parent irqchip
1319 * is handling the direct connect IRQ of the GPIO.
1320 */
1321 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1322 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1323 gpio = pctrl->soc->wakeirq_map[i].gpio;
1324 set_bit(gpio, pctrl->skip_wake_irqs);
1325 }
1326 }
1327
Linus Walleij0ce242a2019-07-24 10:38:28 +02001328 girq = &chip->irq;
Marc Zyngier14dbe182022-04-19 15:18:43 +01001329 gpio_irq_chip_set_chip(girq, &msm_gpio_irq_chip);
Linus Walleij0ce242a2019-07-24 10:38:28 +02001330 girq->parent_handler = msm_gpio_irq_handler;
Lina Iyere35a6ae2019-11-15 15:11:51 -07001331 girq->fwnode = pctrl->dev->fwnode;
Linus Walleij0ce242a2019-07-24 10:38:28 +02001332 girq->num_parents = 1;
1333 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1334 GFP_KERNEL);
1335 if (!girq->parents)
1336 return -ENOMEM;
1337 girq->default_type = IRQ_TYPE_NONE;
1338 girq->handler = handle_bad_irq;
1339 girq->parents[0] = pctrl->irq;
1340
Linus Walleijfded3f42015-12-08 09:49:18 +01001341 ret = gpiochip_add_data(&pctrl->chip, pctrl);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001342 if (ret) {
1343 dev_err(pctrl->dev, "Failed register gpiochip\n");
1344 return ret;
1345 }
1346
Christian Lampartera86caa92018-05-21 22:57:37 +02001347 /*
1348 * For DeviceTree-supported systems, the gpio core checks the
1349 * pinctrl's device node for the "gpio-ranges" property.
1350 * If it is present, it takes care of adding the pin ranges
1351 * for the driver. In this case the driver can skip ahead.
1352 *
1353 * In order to remain compatible with older, existing DeviceTree
1354 * files which don't set the "gpio-ranges" property or systems that
1355 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1356 */
1357 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1358 ret = gpiochip_add_pin_range(&pctrl->chip,
1359 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1360 if (ret) {
1361 dev_err(pctrl->dev, "Failed to add pin range\n");
1362 gpiochip_remove(&pctrl->chip);
1363 return ret;
1364 }
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001365 }
1366
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001367 return 0;
1368}
1369
Josh Cartwrightcf1fc182014-09-23 15:59:53 -05001370static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1371 void *data)
Pramod Gurav32745582014-08-29 20:00:59 +05301372{
Josh Cartwrightcf1fc182014-09-23 15:59:53 -05001373 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1374
Bjorn Anderssona46d5e92018-09-24 15:17:46 -07001375 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
Josh Cartwrightcf1fc182014-09-23 15:59:53 -05001376 mdelay(1000);
1377 return NOTIFY_DONE;
Pramod Gurav32745582014-08-29 20:00:59 +05301378}
1379
Stephen Boydad644982015-07-06 18:09:30 -07001380static struct msm_pinctrl *poweroff_pctrl;
1381
1382static void msm_ps_hold_poweroff(void)
1383{
1384 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1385}
1386
Pramod Gurav32745582014-08-29 20:00:59 +05301387static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1388{
Stephen Boydbcd53f82015-01-19 11:17:45 +01001389 int i;
Pramod Gurav32745582014-08-29 20:00:59 +05301390 const struct msm_function *func = pctrl->soc->functions;
1391
Stephen Boydbcd53f82015-01-19 11:17:45 +01001392 for (i = 0; i < pctrl->soc->nfunctions; i++)
Pramod Gurav32745582014-08-29 20:00:59 +05301393 if (!strcmp(func[i].name, "ps_hold")) {
Josh Cartwrightcf1fc182014-09-23 15:59:53 -05001394 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1395 pctrl->restart_nb.priority = 128;
1396 if (register_restart_handler(&pctrl->restart_nb))
1397 dev_err(pctrl->dev,
1398 "failed to setup restart handler.\n");
Stephen Boydad644982015-07-06 18:09:30 -07001399 poweroff_pctrl = pctrl;
1400 pm_power_off = msm_ps_hold_poweroff;
Josh Cartwrightcf1fc182014-09-23 15:59:53 -05001401 break;
Pramod Gurav32745582014-08-29 20:00:59 +05301402 }
1403}
Pramod Gurav32745582014-08-29 20:00:59 +05301404
Arnd Bergmannd1040ea2018-12-10 21:59:45 +01001405static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
Evan Green977d0572018-11-16 10:58:53 -08001406{
1407 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1408
1409 return pinctrl_force_sleep(pctrl->pctrl);
1410}
1411
Arnd Bergmannd1040ea2018-12-10 21:59:45 +01001412static __maybe_unused int msm_pinctrl_resume(struct device *dev)
Evan Green977d0572018-11-16 10:58:53 -08001413{
1414 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1415
1416 return pinctrl_force_default(pctrl->pctrl);
1417}
1418
1419SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1420 msm_pinctrl_resume);
1421
1422EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1423
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001424int msm_pinctrl_probe(struct platform_device *pdev,
1425 const struct msm_pinctrl_soc_data *soc_data)
1426{
1427 struct msm_pinctrl *pctrl;
1428 struct resource *res;
1429 int ret;
Bjorn Anderssona46d5e92018-09-24 15:17:46 -07001430 int i;
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001431
1432 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
Markus Elfring203f4b02017-12-27 22:04:22 +01001433 if (!pctrl)
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001434 return -ENOMEM;
Markus Elfring203f4b02017-12-27 22:04:22 +01001435
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001436 pctrl->dev = &pdev->dev;
1437 pctrl->soc = soc_data;
1438 pctrl->chip = msm_gpio_template;
Ajay Kishore13bec8d2020-03-27 23:32:08 +01001439 pctrl->intr_target_use_scm = of_device_is_compatible(
1440 pctrl->dev->of_node,
1441 "qcom,ipq8064-pinctrl");
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001442
Julia Cartwright47b03ca2017-01-20 10:13:47 -06001443 raw_spin_lock_init(&pctrl->lock);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001444
Bjorn Anderssona46d5e92018-09-24 15:17:46 -07001445 if (soc_data->tiles) {
1446 for (i = 0; i < soc_data->ntiles; i++) {
1447 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1448 soc_data->tiles[i]);
1449 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1450 if (IS_ERR(pctrl->regs[i]))
1451 return PTR_ERR(pctrl->regs[i]);
1452 }
1453 } else {
Ajay Kishore13bec8d2020-03-27 23:32:08 +01001454 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1455 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
Bjorn Anderssona46d5e92018-09-24 15:17:46 -07001456 if (IS_ERR(pctrl->regs[0]))
1457 return PTR_ERR(pctrl->regs[0]);
Ajay Kishore13bec8d2020-03-27 23:32:08 +01001458
1459 pctrl->phys_base[0] = res->start;
Bjorn Anderssona46d5e92018-09-24 15:17:46 -07001460 }
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001461
Pramod Gurav32745582014-08-29 20:00:59 +05301462 msm_pinctrl_setup_pm_reset(pctrl);
1463
Bjorn Anderssonf393e482013-12-14 23:01:52 -08001464 pctrl->irq = platform_get_irq(pdev, 0);
Stephen Boyd64c4dcb2019-07-30 11:15:33 -07001465 if (pctrl->irq < 0)
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001466 return pctrl->irq;
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001467
Timur Tabif265e8b2018-04-25 17:43:26 -05001468 pctrl->desc.owner = THIS_MODULE;
1469 pctrl->desc.pctlops = &msm_pinctrl_ops;
1470 pctrl->desc.pmxops = &msm_pinmux_ops;
1471 pctrl->desc.confops = &msm_pinconf_ops;
1472 pctrl->desc.name = dev_name(&pdev->dev);
1473 pctrl->desc.pins = pctrl->soc->pins;
1474 pctrl->desc.npins = pctrl->soc->npins;
1475
1476 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
Masahiro Yamada323de9e2015-06-09 13:01:16 +09001477 if (IS_ERR(pctrl->pctrl)) {
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001478 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
Masahiro Yamada323de9e2015-06-09 13:01:16 +09001479 return PTR_ERR(pctrl->pctrl);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001480 }
1481
1482 ret = msm_gpio_init(pctrl);
Laxman Dewanganfe0267f2016-02-24 14:44:07 +05301483 if (ret)
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001484 return ret;
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001485
1486 platform_set_drvdata(pdev, pctrl);
1487
1488 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1489
1490 return 0;
1491}
1492EXPORT_SYMBOL(msm_pinctrl_probe);
1493
1494int msm_pinctrl_remove(struct platform_device *pdev)
1495{
1496 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001497
Linus Walleij2fcea6c2014-09-16 15:05:41 -07001498 gpiochip_remove(&pctrl->chip);
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001499
Josh Cartwrightcf1fc182014-09-23 15:59:53 -05001500 unregister_restart_handler(&pctrl->restart_nb);
1501
Bjorn Anderssonf365be02013-12-05 18:10:03 -08001502 return 0;
1503}
1504EXPORT_SYMBOL(msm_pinctrl_remove);
1505
John Stultz38e86f52020-11-06 04:27:09 +00001506MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver");
1507MODULE_LICENSE("GPL v2");